xref: /freebsd/sys/dev/ice/ice_adminq_cmd.h (revision a90b9d0159070121c221b966469c3e36d912bf82)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*  Copyright (c) 2024, Intel Corporation
3  *  All rights reserved.
4  *
5  *  Redistribution and use in source and binary forms, with or without
6  *  modification, are permitted provided that the following conditions are met:
7  *
8  *   1. Redistributions of source code must retain the above copyright notice,
9  *      this list of conditions and the following disclaimer.
10  *
11  *   2. Redistributions in binary form must reproduce the above copyright
12  *      notice, this list of conditions and the following disclaimer in the
13  *      documentation and/or other materials provided with the distribution.
14  *
15  *   3. Neither the name of the Intel Corporation nor the names of its
16  *      contributors may be used to endorse or promote products derived from
17  *      this software without specific prior written permission.
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19  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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29  *  POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef _ICE_ADMINQ_CMD_H_
33 #define _ICE_ADMINQ_CMD_H_
34 
35 /* This header file defines the Admin Queue commands, error codes and
36  * descriptor format. It is shared between Firmware and Software.
37  */
38 
39 #include "ice_osdep.h"
40 #include "ice_defs.h"
41 #include "ice_bitops.h"
42 
43 #define ICE_MAX_VSI			768
44 #define ICE_AQC_TOPO_MAX_LEVEL_NUM	0x9
45 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX	9728
46 
47 enum ice_aq_res_access_type {
48 	ICE_RES_READ = 1,
49 	ICE_RES_WRITE
50 };
51 
52 struct ice_aqc_generic {
53 	__le32 param0;
54 	__le32 param1;
55 	__le32 addr_high;
56 	__le32 addr_low;
57 };
58 
59 /* Get version (direct 0x0001) */
60 struct ice_aqc_get_ver {
61 	__le32 rom_ver;
62 	__le32 fw_build;
63 	u8 fw_branch;
64 	u8 fw_major;
65 	u8 fw_minor;
66 	u8 fw_patch;
67 	u8 api_branch;
68 	u8 api_major;
69 	u8 api_minor;
70 	u8 api_patch;
71 };
72 
73 /* Send driver version (indirect 0x0002) */
74 struct ice_aqc_driver_ver {
75 	u8 major_ver;
76 	u8 minor_ver;
77 	u8 build_ver;
78 	u8 subbuild_ver;
79 	u8 reserved[4];
80 	__le32 addr_high;
81 	__le32 addr_low;
82 };
83 
84 /* Queue Shutdown (direct 0x0003) */
85 struct ice_aqc_q_shutdown {
86 	u8 driver_unloading;
87 #define ICE_AQC_DRIVER_UNLOADING	BIT(0)
88 	u8 reserved[15];
89 };
90 
91 /* Get Expanded Error Code (0x0005, direct) */
92 struct ice_aqc_get_exp_err {
93 	__le32 reason;
94 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED	0xFFFFFFFF
95 	__le32 identifier;
96 	u8 rsvd[8];
97 };
98 
99 /* Request resource ownership (direct 0x0008)
100  * Release resource ownership (direct 0x0009)
101  */
102 struct ice_aqc_req_res {
103 	__le16 res_id;
104 #define ICE_AQC_RES_ID_NVM		1
105 #define ICE_AQC_RES_ID_SDP		2
106 #define ICE_AQC_RES_ID_CHNG_LOCK	3
107 #define ICE_AQC_RES_ID_GLBL_LOCK	4
108 	__le16 access_type;
109 #define ICE_AQC_RES_ACCESS_READ		1
110 #define ICE_AQC_RES_ACCESS_WRITE	2
111 
112 	/* Upon successful completion, FW writes this value and driver is
113 	 * expected to release resource before timeout. This value is provided
114 	 * in milliseconds.
115 	 */
116 	__le32 timeout;
117 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS	3000
118 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS	180000
119 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS	1000
120 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS	3000
121 	/* For SDP: pin ID of the SDP */
122 	__le32 res_number;
123 	/* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
124 	__le16 status;
125 #define ICE_AQ_RES_GLBL_SUCCESS		0
126 #define ICE_AQ_RES_GLBL_IN_PROG		1
127 #define ICE_AQ_RES_GLBL_DONE		2
128 	u8 reserved[2];
129 };
130 
131 /* Get function capabilities (indirect 0x000A)
132  * Get device capabilities (indirect 0x000B)
133  */
134 struct ice_aqc_list_caps {
135 	u8 cmd_flags;
136 	u8 pf_index;
137 	u8 reserved[2];
138 	__le32 count;
139 	__le32 addr_high;
140 	__le32 addr_low;
141 };
142 
143 /* Device/Function buffer entry, repeated per reported capability */
144 struct ice_aqc_list_caps_elem {
145 	__le16 cap;
146 #define ICE_AQC_CAPS_SWITCHING_MODE			0x0001
147 #define ICE_AQC_CAPS_MANAGEABILITY_MODE			0x0002
148 #define ICE_AQC_CAPS_OS2BMC				0x0004
149 #define ICE_AQC_CAPS_VALID_FUNCTIONS			0x0005
150 #define ICE_AQC_MAX_VALID_FUNCTIONS			0x8
151 #define ICE_AQC_CAPS_ALTERNATE_RAM			0x0006
152 #define ICE_AQC_CAPS_WOL_PROXY				0x0008
153 #define ICE_AQC_CAPS_SRIOV				0x0012
154 #define ICE_AQC_CAPS_VF					0x0013
155 #define ICE_AQC_CAPS_VMDQ				0x0014
156 #define ICE_AQC_CAPS_802_1QBG				0x0015
157 #define ICE_AQC_CAPS_802_1BR				0x0016
158 #define ICE_AQC_CAPS_VSI				0x0017
159 #define ICE_AQC_CAPS_DCB				0x0018
160 #define ICE_AQC_CAPS_RSVD				0x0021
161 #define ICE_AQC_CAPS_ISCSI				0x0022
162 #define ICE_AQC_CAPS_RSS				0x0040
163 #define ICE_AQC_CAPS_RXQS				0x0041
164 #define ICE_AQC_CAPS_TXQS				0x0042
165 #define ICE_AQC_CAPS_MSIX				0x0043
166 #define ICE_AQC_CAPS_MAX_MTU				0x0047
167 #define ICE_AQC_CAPS_CEM				0x00F2
168 #define ICE_AQC_CAPS_IWARP				0x0051
169 #define ICE_AQC_CAPS_LED				0x0061
170 #define ICE_AQC_CAPS_SDP				0x0062
171 #define ICE_AQC_CAPS_WR_CSR_PROT			0x0064
172 #define ICE_AQC_CAPS_SENSOR_READING			0x0067
173 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP		0x0073
174 #define ICE_AQC_CAPS_SKU				0x0074
175 #define ICE_AQC_CAPS_PORT_MAP				0x0075
176 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE		0x0076
177 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT		0x0077
178 #define ICE_AQC_CAPS_NVM_MGMT				0x0080
179 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0			0x0081
180 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1			0x0082
181 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2			0x0083
182 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3			0x0084
183 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE		0x0085
184 #define ICE_AQC_CAPS_NAC_TOPOLOGY			0x0087
185 #define ICE_AQC_CAPS_DYN_FLATTENING			0x008A
186 #define ICE_AQC_CAPS_OROM_RECOVERY_UPDATE		0x0090
187 #define ICE_AQC_CAPS_ROCEV2_LAG				0x0092
188 #define ICE_AQC_BIT_ROCEV2_LAG				0x01
189 #define ICE_AQC_BIT_SRIOV_LAG				0x02
190 
191 	u8 major_ver;
192 	u8 minor_ver;
193 	/* Number of resources described by this capability */
194 	__le32 number;
195 	/* Only meaningful for some types of resources */
196 	__le32 logical_id;
197 	/* Only meaningful for some types of resources */
198 	__le32 phys_id;
199 	__le64 rsvd1;
200 	__le64 rsvd2;
201 };
202 
203 /* Manage MAC address, read command - indirect (0x0107)
204  * This struct is also used for the response
205  */
206 struct ice_aqc_manage_mac_read {
207 	__le16 flags; /* Zeroed by device driver */
208 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID		BIT(4)
209 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID		BIT(5)
210 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID		BIT(6)
211 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID		BIT(7)
212 #define ICE_AQC_MAN_MAC_MC_MAG_EN		BIT(8)
213 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR	BIT(9)
214 #define ICE_AQC_MAN_MAC_READ_S			4
215 #define ICE_AQC_MAN_MAC_READ_M			(0xF << ICE_AQC_MAN_MAC_READ_S)
216 	u8 rsvd[2];
217 	u8 num_addr; /* Used in response */
218 	u8 rsvd1[3];
219 	__le32 addr_high;
220 	__le32 addr_low;
221 };
222 
223 /* Response buffer format for manage MAC read command */
224 struct ice_aqc_manage_mac_read_resp {
225 	u8 lport_num;
226 	u8 addr_type;
227 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN		0
228 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL		1
229 	u8 mac_addr[ETH_ALEN];
230 };
231 
232 /* Manage MAC address, write command - direct (0x0108) */
233 struct ice_aqc_manage_mac_write {
234 	u8 rsvd;
235 	u8 flags;
236 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN		BIT(0)
237 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP	BIT(1)
238 #define ICE_AQC_MAN_MAC_WR_S		6
239 #define ICE_AQC_MAN_MAC_WR_M		MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S)
240 #define ICE_AQC_MAN_MAC_UPDATE_LAA	0
241 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL	BIT(ICE_AQC_MAN_MAC_WR_S)
242 	/* byte stream in network order */
243 	u8 mac_addr[ETH_ALEN];
244 	__le32 addr_high;
245 	__le32 addr_low;
246 };
247 
248 /* Clear PXE Command and response (direct 0x0110) */
249 struct ice_aqc_clear_pxe {
250 	u8 rx_cnt;
251 #define ICE_AQC_CLEAR_PXE_RX_CNT		0x2
252 	u8 reserved[15];
253 };
254 
255 /* Configure No-Drop Policy Command (direct 0x0112) */
256 struct ice_aqc_config_no_drop_policy {
257 	u8 opts;
258 #define ICE_AQC_FORCE_NO_DROP			BIT(0)
259 	u8 rsvd[15];
260 };
261 
262 /* Get switch configuration (0x0200) */
263 struct ice_aqc_get_sw_cfg {
264 	/* Reserved for command and copy of request flags for response */
265 	__le16 flags;
266 	/* First desc in case of command and next_elem in case of response
267 	 * In case of response, if it is not zero, means all the configuration
268 	 * was not returned and new command shall be sent with this value in
269 	 * the 'first desc' field
270 	 */
271 	__le16 element;
272 	/* Reserved for command, only used for response */
273 	__le16 num_elems;
274 	__le16 rsvd;
275 	__le32 addr_high;
276 	__le32 addr_low;
277 };
278 
279 /* Each entry in the response buffer is of the following type: */
280 struct ice_aqc_get_sw_cfg_resp_elem {
281 	/* VSI/Port Number */
282 	__le16 vsi_port_num;
283 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S	0
284 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M	\
285 			(0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
286 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S	14
287 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M	(0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
288 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT	0
289 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT	1
290 #define ICE_AQC_GET_SW_CONF_RESP_VSI		2
291 
292 	/* SWID VSI/Port belongs to */
293 	__le16 swid;
294 
295 	/* Bit 14..0 : PF/VF number VSI belongs to
296 	 * Bit 15 : VF indication bit
297 	 */
298 	__le16 pf_vf_num;
299 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S	0
300 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M	\
301 				(0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
302 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF		BIT(15)
303 };
304 
305 /* Set Port parameters, (direct, 0x0203) */
306 struct ice_aqc_set_port_params {
307 	__le16 cmd_flags;
308 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS	BIT(0)
309 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS	BIT(1)
310 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA	BIT(2)
311 	__le16 bad_frame_vsi;
312 #define ICE_AQC_SET_P_PARAMS_VSI_S	0
313 #define ICE_AQC_SET_P_PARAMS_VSI_M	(0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S)
314 #define ICE_AQC_SET_P_PARAMS_VSI_VALID	BIT(15)
315 	__le16 swid;
316 #define ICE_AQC_SET_P_PARAMS_SWID_S	0
317 #define ICE_AQC_SET_P_PARAMS_SWID_M	(0xFF << ICE_AQC_SET_P_PARAMS_SWID_S)
318 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S	8
319 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M	\
320 				(0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S)
321 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT	BIT(14)
322 #define ICE_AQC_SET_P_PARAMS_SWID_VALID		BIT(15)
323 	u8 reserved[10];
324 };
325 
326 /* These resource type defines are used for all switch resource
327  * commands where a resource type is required, such as:
328  * Get Resource Allocation command (indirect 0x0204)
329  * Allocate Resources command (indirect 0x0208)
330  * Free Resources command (indirect 0x0209)
331  * Get Allocated Resource Descriptors Command (indirect 0x020A)
332  */
333 #define ICE_AQC_RES_TYPE_VEB_COUNTER			0x00
334 #define ICE_AQC_RES_TYPE_VLAN_COUNTER			0x01
335 #define ICE_AQC_RES_TYPE_MIRROR_RULE			0x02
336 #define ICE_AQC_RES_TYPE_VSI_LIST_REP			0x03
337 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE			0x04
338 #define ICE_AQC_RES_TYPE_RECIPE				0x05
339 #define ICE_AQC_RES_TYPE_PROFILE			0x06
340 #define ICE_AQC_RES_TYPE_SWID				0x07
341 #define ICE_AQC_RES_TYPE_VSI				0x08
342 #define ICE_AQC_RES_TYPE_FLU				0x09
343 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1			0x0A
344 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2			0x0B
345 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4			0x0C
346 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH		0x20
347 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK		0x21
348 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES	0x22
349 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES		0x23
350 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG			0x30
351 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID	0x48
352 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM		0x49
353 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID		0x50
354 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM		0x51
355 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID		0x60
356 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM		0x61
357 /* Resource types 0x62-67 are reserved for Hash profile builder */
358 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID		0x68
359 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM		0x69
360 
361 #define ICE_AQC_RES_TYPE_FLAG_SHARED			BIT(7)
362 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM		BIT(12)
363 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX		BIT(13)
364 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED		BIT(14)
365 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL		BIT(15)
366 
367 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED			0x00
368 
369 #define ICE_AQC_RES_TYPE_S	0
370 #define ICE_AQC_RES_TYPE_M	(0x07F << ICE_AQC_RES_TYPE_S)
371 
372 /* Get Resource Allocation command (indirect 0x0204) */
373 struct ice_aqc_get_res_alloc {
374 	__le16 resp_elem_num; /* Used in response, reserved in command */
375 	u8 reserved[6];
376 	__le32 addr_high;
377 	__le32 addr_low;
378 };
379 
380 /* Get Resource Allocation Response Buffer per response */
381 struct ice_aqc_get_res_resp_elem {
382 	__le16 res_type; /* Types defined above cmd 0x0204 */
383 	__le16 total_capacity; /* Resources available to all PF's */
384 	__le16 total_function; /* Resources allocated for a PF */
385 	__le16 total_shared; /* Resources allocated as shared */
386 	__le16 total_free; /* Resources un-allocated/not reserved by any PF */
387 };
388 
389 /* Allocate Resources command (indirect 0x0208)
390  * Free Resources command (indirect 0x0209)
391  */
392 struct ice_aqc_alloc_free_res_cmd {
393 	__le16 num_entries; /* Number of Resource entries */
394 	u8 reserved[6];
395 	__le32 addr_high;
396 	__le32 addr_low;
397 };
398 
399 /* Resource descriptor */
400 struct ice_aqc_res_elem {
401 	union {
402 		__le16 sw_resp;
403 		__le16 flu_resp;
404 	} e;
405 };
406 
407 /* Buffer for Allocate/Free Resources commands */
408 struct ice_aqc_alloc_free_res_elem {
409 	__le16 res_type; /* Types defined above cmd 0x0204 */
410 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S	8
411 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M	\
412 				(0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
413 	__le16 num_elems;
414 	struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN];
415 };
416 
417 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */
418 struct ice_aqc_get_allocd_res_desc {
419 	union {
420 		struct {
421 			__le16 res; /* Types defined above cmd 0x0204 */
422 			__le16 first_desc;
423 			__le32 reserved;
424 		} cmd;
425 		struct {
426 			__le16 res;
427 			__le16 next_desc;
428 			__le16 num_desc;
429 			__le16 reserved;
430 		} resp;
431 	} ops;
432 	__le32 addr_high;
433 	__le32 addr_low;
434 };
435 
436 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
437 struct ice_aqc_set_vlan_mode {
438 	u8 reserved;
439 	u8 l2tag_prio_tagging;
440 #define ICE_AQ_VLAN_PRIO_TAG_S			0
441 #define ICE_AQ_VLAN_PRIO_TAG_M			(0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
442 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED	0x0
443 #define ICE_AQ_VLAN_PRIO_TAG_STAG		0x1
444 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG		0x2
445 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN		0x3
446 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG		0x4
447 #define ICE_AQ_VLAN_PRIO_TAG_MAX		0x4
448 #define ICE_AQ_VLAN_PRIO_TAG_ERROR		0x7
449 	u8 l2tag_reserved[64];
450 	u8 rdma_packet;
451 #define ICE_AQ_VLAN_RDMA_TAG_S			0
452 #define ICE_AQ_VLAN_RDMA_TAG_M			(0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
453 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING	0x10
454 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING	0x1A
455 	u8 rdma_reserved[2];
456 	u8 mng_vlan_prot_id;
457 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER	0x10
458 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER	0x11
459 	u8 prot_id_reserved[30];
460 };
461 
462 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
463 struct ice_aqc_get_vlan_mode {
464 	u8 vlan_mode;
465 #define ICE_AQ_VLAN_MODE_DVM_ENA	BIT(0)
466 	u8 l2tag_prio_tagging;
467 	u8 reserved[98];
468 };
469 
470 /* Add VSI (indirect 0x0210)
471  * Update VSI (indirect 0x0211)
472  * Get VSI (indirect 0x0212)
473  * Free VSI (indirect 0x0213)
474  */
475 struct ice_aqc_add_get_update_free_vsi {
476 	__le16 vsi_num;
477 #define ICE_AQ_VSI_NUM_S	0
478 #define ICE_AQ_VSI_NUM_M	(0x03FF << ICE_AQ_VSI_NUM_S)
479 #define ICE_AQ_VSI_IS_VALID	BIT(15)
480 	__le16 cmd_flags;
481 #define ICE_AQ_VSI_KEEP_ALLOC	0x1
482 	u8 vf_id;
483 	u8 reserved;
484 	__le16 vsi_flags;
485 #define ICE_AQ_VSI_TYPE_S	0
486 #define ICE_AQ_VSI_TYPE_M	(0x3 << ICE_AQ_VSI_TYPE_S)
487 #define ICE_AQ_VSI_TYPE_VF	0x0
488 #define ICE_AQ_VSI_TYPE_VMDQ2	0x1
489 #define ICE_AQ_VSI_TYPE_PF	0x2
490 #define ICE_AQ_VSI_TYPE_EMP_MNG	0x3
491 	__le32 addr_high;
492 	__le32 addr_low;
493 };
494 
495 /* Response descriptor for:
496  * Add VSI (indirect 0x0210)
497  * Update VSI (indirect 0x0211)
498  * Free VSI (indirect 0x0213)
499  */
500 struct ice_aqc_add_update_free_vsi_resp {
501 	__le16 vsi_num;
502 	__le16 ext_status;
503 	__le16 vsi_used;
504 	__le16 vsi_free;
505 	__le32 addr_high;
506 	__le32 addr_low;
507 };
508 
509 struct ice_aqc_get_vsi_resp {
510 	__le16 vsi_num;
511 	u8 vf_id;
512 	/* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values.
513 	 * These are found above in struct ice_aqc_add_get_update_free_vsi.
514 	 */
515 	u8 vsi_flags;
516 	__le16 vsi_used;
517 	__le16 vsi_free;
518 	__le32 addr_high;
519 	__le32 addr_low;
520 };
521 
522 struct ice_aqc_vsi_props {
523 	__le16 valid_sections;
524 #define ICE_AQ_VSI_PROP_SW_VALID		BIT(0)
525 #define ICE_AQ_VSI_PROP_SECURITY_VALID		BIT(1)
526 #define ICE_AQ_VSI_PROP_VLAN_VALID		BIT(2)
527 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID		BIT(3)
528 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID	BIT(4)
529 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID		BIT(5)
530 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID		BIT(6)
531 #define ICE_AQ_VSI_PROP_Q_OPT_VALID		BIT(7)
532 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID		BIT(8)
533 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID		BIT(11)
534 #define ICE_AQ_VSI_PROP_PASID_VALID		BIT(12)
535 	/* switch section */
536 	u8 sw_id;
537 	u8 sw_flags;
538 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB		BIT(5)
539 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB		BIT(6)
540 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE		BIT(7)
541 	u8 sw_flags2;
542 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S	0
543 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M	(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
544 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA	BIT(0)
545 #define ICE_AQ_VSI_SW_FLAG_RX_PASS_PRUNE_ENA	BIT(3)
546 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA		BIT(4)
547 	u8 veb_stat_id;
548 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S		0
549 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M		(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
550 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID		BIT(5)
551 	/* security section */
552 	u8 sec_flags;
553 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD	BIT(0)
554 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF	BIT(2)
555 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S		4
556 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M		(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
557 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA	BIT(0)
558 	u8 sec_reserved;
559 	/* VLAN section */
560 	__le16 port_based_inner_vlan; /* VLANS include priority bits */
561 	u8 inner_vlan_reserved[2];
562 	u8 inner_vlan_flags;
563 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S		0
564 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M		(0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
565 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED	0x1
566 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED	0x2
567 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL	0x3
568 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID	BIT(2)
569 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S		3
570 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M		(0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
571 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH	(0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
572 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP	(0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
573 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR		(0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
574 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING	(0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
575 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC	BIT(5)
576 	u8 inner_vlan_reserved2[3];
577 	/* ingress egress up sections */
578 	__le32 ingress_table; /* bitmap, 3 bits per up */
579 #define ICE_AQ_VSI_UP_TABLE_UP0_S		0
580 #define ICE_AQ_VSI_UP_TABLE_UP0_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
581 #define ICE_AQ_VSI_UP_TABLE_UP1_S		3
582 #define ICE_AQ_VSI_UP_TABLE_UP1_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
583 #define ICE_AQ_VSI_UP_TABLE_UP2_S		6
584 #define ICE_AQ_VSI_UP_TABLE_UP2_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
585 #define ICE_AQ_VSI_UP_TABLE_UP3_S		9
586 #define ICE_AQ_VSI_UP_TABLE_UP3_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
587 #define ICE_AQ_VSI_UP_TABLE_UP4_S		12
588 #define ICE_AQ_VSI_UP_TABLE_UP4_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
589 #define ICE_AQ_VSI_UP_TABLE_UP5_S		15
590 #define ICE_AQ_VSI_UP_TABLE_UP5_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
591 #define ICE_AQ_VSI_UP_TABLE_UP6_S		18
592 #define ICE_AQ_VSI_UP_TABLE_UP6_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
593 #define ICE_AQ_VSI_UP_TABLE_UP7_S		21
594 #define ICE_AQ_VSI_UP_TABLE_UP7_M		(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
595 	__le32 egress_table;   /* same defines as for ingress table */
596 	/* outer tags section */
597 	__le16 port_based_outer_vlan;
598 	u8 outer_vlan_flags;
599 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S		0
600 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M		(0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
601 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH	0x0
602 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP	0x1
603 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW	0x2
604 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING	0x3
605 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S		2
606 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M		(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
607 #define ICE_AQ_VSI_OUTER_TAG_NONE		0x0
608 #define ICE_AQ_VSI_OUTER_TAG_STAG		0x1
609 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100		0x2
610 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100		0x3
611 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT		BIT(4)
612 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S			5
613 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M			(0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
614 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED	0x1
615 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED	0x2
616 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL		0x3
617 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC		BIT(7)
618 	u8 outer_vlan_reserved;
619 	/* queue mapping section */
620 	__le16 mapping_flags;
621 #define ICE_AQ_VSI_Q_MAP_CONTIG			0x0
622 #define ICE_AQ_VSI_Q_MAP_NONCONTIG		BIT(0)
623 	__le16 q_mapping[16];
624 #define ICE_AQ_VSI_Q_S				0
625 #define ICE_AQ_VSI_Q_M				(0x7FF << ICE_AQ_VSI_Q_S)
626 	__le16 tc_mapping[8];
627 #define ICE_AQ_VSI_TC_Q_OFFSET_S		0
628 #define ICE_AQ_VSI_TC_Q_OFFSET_M		(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
629 #define ICE_AQ_VSI_TC_Q_NUM_S			11
630 #define ICE_AQ_VSI_TC_Q_NUM_M			(0xF << ICE_AQ_VSI_TC_Q_NUM_S)
631 	/* queueing option section */
632 	u8 q_opt_rss;
633 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S		0
634 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M		(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
635 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI		0x0
636 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF		0x2
637 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL		0x3
638 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S		2
639 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M		(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
640 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S		6
641 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M		(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
642 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ		(0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
643 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ		(0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
644 #define ICE_AQ_VSI_Q_OPT_RSS_XOR		(0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
645 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH		(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
646 	u8 q_opt_tc;
647 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S		0
648 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M		(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
649 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR		BIT(7)
650 	u8 q_opt_flags;
651 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN		BIT(0)
652 	u8 q_opt_reserved[3];
653 	/* outer up section */
654 	__le32 outer_up_table; /* same structure and defines as ingress tbl */
655 	/* section 10 */
656 	__le16 sect_10_reserved;
657 	/* flow director section */
658 	__le16 fd_options;
659 #define ICE_AQ_VSI_FD_ENABLE			BIT(0)
660 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE		BIT(1)
661 #define ICE_AQ_VSI_FD_PROG_ENABLE		BIT(3)
662 	__le16 max_fd_fltr_dedicated;
663 	__le16 max_fd_fltr_shared;
664 	__le16 fd_def_q;
665 #define ICE_AQ_VSI_FD_DEF_Q_S			0
666 #define ICE_AQ_VSI_FD_DEF_Q_M			(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
667 #define ICE_AQ_VSI_FD_DEF_GRP_S			12
668 #define ICE_AQ_VSI_FD_DEF_GRP_M			(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
669 	__le16 fd_report_opt;
670 #define ICE_AQ_VSI_FD_REPORT_Q_S		0
671 #define ICE_AQ_VSI_FD_REPORT_Q_M		(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
672 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S		12
673 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M		(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
674 #define ICE_AQ_VSI_FD_DEF_DROP			BIT(15)
675 	/* PASID section */
676 	__le32 pasid_id;
677 #define ICE_AQ_VSI_PASID_ID_S			0
678 #define ICE_AQ_VSI_PASID_ID_M			(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
679 #define ICE_AQ_VSI_PASID_ID_VALID		BIT(31)
680 	u8 reserved[24];
681 };
682 
683 /* Add/update mirror rule - direct (0x0260) */
684 #define ICE_AQC_RULE_ID_VALID_S		7
685 #define ICE_AQC_RULE_ID_VALID_M		(0x1 << ICE_AQC_RULE_ID_VALID_S)
686 #define ICE_AQC_RULE_ID_S		0
687 #define ICE_AQC_RULE_ID_M		(0x3F << ICE_AQC_RULE_ID_S)
688 
689 /* Following defines to be used while processing caller specified mirror list
690  * of VSI indexes.
691  */
692 /* Action: Byte.bit (1.7)
693  *	0 = Remove VSI from mirror rule
694  *	1 = Add VSI to mirror rule
695  */
696 #define ICE_AQC_RULE_ACT_S	15
697 #define ICE_AQC_RULE_ACT_M	(0x1 << ICE_AQC_RULE_ACT_S)
698 /* Action: 1.2:0.0 = Mirrored VSI */
699 #define ICE_AQC_RULE_MIRRORED_VSI_S	0
700 #define ICE_AQC_RULE_MIRRORED_VSI_M	(0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S)
701 
702 /* This is to be used by add/update mirror rule Admin Queue command.
703  * In case of add mirror rule - if rule ID is specified as
704  * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool.
705  * If specified rule_id is valid, then it is used. If specified rule_id
706  * is in use then new mirroring rule is added.
707  */
708 #define ICE_INVAL_MIRROR_RULE_ID	0xFFFF
709 
710 struct ice_aqc_add_update_mir_rule {
711 	__le16 rule_id;
712 
713 	__le16 rule_type;
714 #define ICE_AQC_RULE_TYPE_S		0
715 #define ICE_AQC_RULE_TYPE_M		(0x7 << ICE_AQC_RULE_TYPE_S)
716 	/* VPORT ingress/egress */
717 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS	0x1
718 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS	0x2
719 	/* Physical port ingress mirroring.
720 	 * All traffic received by this port
721 	 */
722 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS	0x6
723 	/* Physical port egress mirroring. All traffic sent by this port */
724 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS	0x7
725 
726 	/* Number of mirrored entries.
727 	 * The values are in the command buffer
728 	 */
729 	__le16 num_entries;
730 
731 	/* Destination VSI */
732 	__le16 dest;
733 	__le32 addr_high;
734 	__le32 addr_low;
735 };
736 
737 /* Delete mirror rule - direct(0x0261) */
738 struct ice_aqc_delete_mir_rule {
739 	__le16 rule_id;
740 	__le16 rsvd;
741 
742 	/* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of
743 	 * the PF allocated resources, otherwise it is returned to the
744 	 * shared pool
745 	 */
746 #define ICE_AQC_FLAG_KEEP_ALLOCD_S	0
747 #define ICE_AQC_FLAG_KEEP_ALLOCD_M	(0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S)
748 	__le16 flags;
749 
750 	u8 reserved[10];
751 };
752 
753 /* Set/Get storm config - (direct 0x0280, 0x0281) */
754 /* This structure holds get storm configuration response and same structure
755  * is used to perform set_storm_cfg
756  */
757 struct ice_aqc_storm_cfg {
758 	__le32 bcast_thresh_size;
759 	__le32 mcast_thresh_size;
760 	/* Bit 18:0 - Traffic upper threshold size
761 	 * Bit 31:19 - Reserved
762 	 */
763 #define ICE_AQ_THRESHOLD_S	0
764 #define ICE_AQ_THRESHOLD_M	(0x7FFFF << ICE_AQ_THRESHOLD_S)
765 
766 	__le32 storm_ctrl_ctrl;
767 	/* Bit 0: MDIPW - Drop Multicast packets in previous window
768 	 * Bit 1: MDICW - Drop multicast packets in current window
769 	 * Bit 2: BDIPW - Drop broadcast packets in previous window
770 	 * Bit 3: BDICW - Drop broadcast packets in current window
771 	 */
772 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST	BIT(0)
773 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST	BIT(1)
774 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST	BIT(2)
775 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST	BIT(3)
776 	/* Bit 7:5 : Reserved */
777 	/* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The
778 	 * interval size for applying ingress broadcast or multicast storm
779 	 * control.
780 	 */
781 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S	8
782 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M	\
783 			(0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S)
784 	__le32 reserved;
785 };
786 
787 #define ICE_MAX_NUM_RECIPES 64
788 
789 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
790  */
791 struct ice_aqc_sw_rules {
792 	/* ops: add switch rules, referring the number of rules.
793 	 * ops: update switch rules, referring the number of filters
794 	 * ops: remove switch rules, referring the entry index.
795 	 * ops: get switch rules, referring to the number of filters.
796 	 */
797 	__le16 num_rules_fltr_entry_index;
798 	u8 reserved[6];
799 	__le32 addr_high;
800 	__le32 addr_low;
801 };
802 
803 /* Add switch rule response:
804  * Content of return buffer is same as the input buffer. The status field and
805  * LUT index are updated as part of the response
806  */
807 struct ice_aqc_sw_rules_elem_hdr {
808 	__le16 type; /* Switch rule type, one of T_... */
809 #define ICE_AQC_SW_RULES_T_LKUP_RX		0x0
810 #define ICE_AQC_SW_RULES_T_LKUP_TX		0x1
811 #define ICE_AQC_SW_RULES_T_LG_ACT		0x2
812 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET		0x3
813 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR	0x4
814 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET	0x5
815 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR	0x6
816 	__le16 status;
817 };
818 
819 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
820  * This structures describes the lookup rules and associated actions. "index"
821  * is returned as part of a response to a successful Add command, and can be
822  * used to identify the rule for Update/Get/Remove commands.
823  */
824 struct ice_sw_rule_lkup_rx_tx {
825 	struct ice_aqc_sw_rules_elem_hdr hdr;
826 
827 	__le16 recipe_id;
828 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD		10
829 	/* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
830 	__le16 src;
831 	__le32 act;
832 
833 	/* Bit 0:1 - Action type */
834 #define ICE_SINGLE_ACT_TYPE_S	0x00
835 #define ICE_SINGLE_ACT_TYPE_M	(0x3 << ICE_SINGLE_ACT_TYPE_S)
836 
837 	/* Bit 2 - Loop back enable
838 	 * Bit 3 - LAN enable
839 	 */
840 #define ICE_SINGLE_ACT_LB_ENABLE	BIT(2)
841 #define ICE_SINGLE_ACT_LAN_ENABLE	BIT(3)
842 
843 	/* Action type = 0 - Forward to VSI or VSI list */
844 #define ICE_SINGLE_ACT_VSI_FORWARDING	0x0
845 
846 #define ICE_SINGLE_ACT_VSI_ID_S		4
847 #define ICE_SINGLE_ACT_VSI_ID_M		(0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
848 #define ICE_SINGLE_ACT_VSI_LIST_ID_S	4
849 #define ICE_SINGLE_ACT_VSI_LIST_ID_M	(0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
850 	/* This bit needs to be set if action is forward to VSI list */
851 #define ICE_SINGLE_ACT_VSI_LIST		BIT(14)
852 #define ICE_SINGLE_ACT_VALID_BIT	BIT(17)
853 #define ICE_SINGLE_ACT_DROP		BIT(18)
854 
855 	/* Action type = 1 - Forward to Queue of Queue group */
856 #define ICE_SINGLE_ACT_TO_Q		0x1
857 #define ICE_SINGLE_ACT_Q_INDEX_S	4
858 #define ICE_SINGLE_ACT_Q_INDEX_M	(0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
859 #define ICE_SINGLE_ACT_Q_REGION_S	15
860 #define ICE_SINGLE_ACT_Q_REGION_M	(0x7 << ICE_SINGLE_ACT_Q_REGION_S)
861 #define ICE_SINGLE_ACT_Q_PRIORITY	BIT(18)
862 
863 	/* Action type = 2 - Prune */
864 #define ICE_SINGLE_ACT_PRUNE		0x2
865 #define ICE_SINGLE_ACT_EGRESS		BIT(15)
866 #define ICE_SINGLE_ACT_INGRESS		BIT(16)
867 #define ICE_SINGLE_ACT_PRUNET		BIT(17)
868 	/* Bit 18 should be set to 0 for this action */
869 
870 	/* Action type = 2 - Pointer */
871 #define ICE_SINGLE_ACT_PTR		0x2
872 #define ICE_SINGLE_ACT_PTR_VAL_S	4
873 #define ICE_SINGLE_ACT_PTR_VAL_M	(0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
874 	/* Bit 17 should be set if pointed action includes a FWD cmd */
875 #define ICE_SINGLE_ACT_PTR_HAS_FWD	BIT(17)
876 	/* Bit 18 should be set to 1 */
877 #define ICE_SINGLE_ACT_PTR_BIT		BIT(18)
878 
879 	/* Action type = 3 - Other actions. Last two bits
880 	 * are other action identifier
881 	 */
882 #define ICE_SINGLE_ACT_OTHER_ACTS		0x3
883 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S	17
884 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M	\
885 				(0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
886 
887 	/* Bit 17:18 - Defines other actions */
888 	/* Other action = 0 - Mirror VSI */
889 #define ICE_SINGLE_OTHER_ACT_MIRROR		0
890 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S	4
891 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M	\
892 				(0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
893 
894 	/* Other action = 3 - Set Stat count */
895 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT		3
896 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S	4
897 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M	\
898 				(0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
899 
900 	__le16 index; /* The index of the rule in the lookup table */
901 	/* Length and values of the header to be matched per recipe or
902 	 * lookup-type
903 	 */
904 	__le16 hdr_len;
905 	u8 hdr_data[STRUCT_HACK_VAR_LEN];
906 };
907 
908 #pragma pack(1)
909 /* Add/Update/Remove large action command/response entry
910  * "index" is returned as part of a response to a successful Add command, and
911  * can be used to identify the action for Update/Get/Remove commands.
912  */
913 struct ice_sw_rule_lg_act {
914 	struct ice_aqc_sw_rules_elem_hdr hdr;
915 
916 	__le16 index; /* Index in large action table */
917 	__le16 size;
918 	/* Max number of large actions */
919 #define ICE_MAX_LG_ACT	4
920 	/* Bit 0:1 - Action type */
921 #define ICE_LG_ACT_TYPE_S	0
922 #define ICE_LG_ACT_TYPE_M	(0x7 << ICE_LG_ACT_TYPE_S)
923 
924 	/* Action type = 0 - Forward to VSI or VSI list */
925 #define ICE_LG_ACT_VSI_FORWARDING	0
926 #define ICE_LG_ACT_VSI_ID_S		3
927 #define ICE_LG_ACT_VSI_ID_M		(0x3FF << ICE_LG_ACT_VSI_ID_S)
928 #define ICE_LG_ACT_VSI_LIST_ID_S	3
929 #define ICE_LG_ACT_VSI_LIST_ID_M	(0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
930 	/* This bit needs to be set if action is forward to VSI list */
931 #define ICE_LG_ACT_VSI_LIST		BIT(13)
932 
933 #define ICE_LG_ACT_VALID_BIT		BIT(16)
934 
935 	/* Action type = 1 - Forward to Queue of Queue group */
936 #define ICE_LG_ACT_TO_Q			0x1
937 #define ICE_LG_ACT_Q_INDEX_S		3
938 #define ICE_LG_ACT_Q_INDEX_M		(0x7FF << ICE_LG_ACT_Q_INDEX_S)
939 #define ICE_LG_ACT_Q_REGION_S		14
940 #define ICE_LG_ACT_Q_REGION_M		(0x7 << ICE_LG_ACT_Q_REGION_S)
941 #define ICE_LG_ACT_Q_PRIORITY_SET	BIT(17)
942 
943 	/* Action type = 2 - Prune */
944 #define ICE_LG_ACT_PRUNE		0x2
945 #define ICE_LG_ACT_EGRESS		BIT(14)
946 #define ICE_LG_ACT_INGRESS		BIT(15)
947 #define ICE_LG_ACT_PRUNET		BIT(16)
948 
949 	/* Action type = 3 - Mirror VSI */
950 #define ICE_LG_OTHER_ACT_MIRROR		0x3
951 #define ICE_LG_ACT_MIRROR_VSI_ID_S	3
952 #define ICE_LG_ACT_MIRROR_VSI_ID_M	(0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
953 
954 	/* Action type = 5 - Generic Value */
955 #define ICE_LG_ACT_GENERIC		0x5
956 #define ICE_LG_ACT_GENERIC_VALUE_S	3
957 #define ICE_LG_ACT_GENERIC_VALUE_M	(0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
958 #define ICE_LG_ACT_GENERIC_OFFSET_S	19
959 #define ICE_LG_ACT_GENERIC_OFFSET_M	(0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
960 #define ICE_LG_ACT_GENERIC_PRIORITY_S	22
961 #define ICE_LG_ACT_GENERIC_PRIORITY_M	(0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
962 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX	7
963 
964 	/* Action = 7 - Set Stat count */
965 #define ICE_LG_ACT_STAT_COUNT		0x7
966 #define ICE_LG_ACT_STAT_COUNT_S		3
967 #define ICE_LG_ACT_STAT_COUNT_M		(0x7F << ICE_LG_ACT_STAT_COUNT_S)
968 	__le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */
969 };
970 #pragma pack()
971 
972 #pragma pack(1)
973 /* Add/Update/Remove VSI list command/response entry
974  * "index" is returned as part of a response to a successful Add command, and
975  * can be used to identify the VSI list for Update/Get/Remove commands.
976  */
977 struct ice_sw_rule_vsi_list {
978 	struct ice_aqc_sw_rules_elem_hdr hdr;
979 
980 	__le16 index; /* Index of VSI/Prune list */
981 	__le16 number_vsi;
982 	__le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */
983 };
984 #pragma pack()
985 
986 #pragma pack(1)
987 /* Query VSI list command/response entry */
988 struct ice_sw_rule_vsi_list_query {
989 	__le16 index;
990 	u8 vsi_list[DIVIDE_AND_ROUND_UP(ICE_MAX_VSI, BITS_PER_BYTE)];
991 };
992 #pragma pack()
993 
994 /* PFC Ignore (direct 0x0301)
995  * The command and response use the same descriptor structure
996  */
997 struct ice_aqc_pfc_ignore {
998 	u8	tc_bitmap;
999 	u8	cmd_flags; /* unused in response */
1000 #define ICE_AQC_PFC_IGNORE_SET		BIT(7)
1001 #define ICE_AQC_PFC_IGNORE_CLEAR	0
1002 	u8	reserved[14];
1003 };
1004 
1005 /* Query PFC Mode (direct 0x0302)
1006  * Set PFC Mode (direct 0x0303)
1007  */
1008 struct ice_aqc_set_query_pfc_mode {
1009 	u8	pfc_mode;
1010 /* For Set Command response, reserved in all other cases */
1011 #define ICE_AQC_PFC_NOT_CONFIGURED	0
1012 /* For Query Command response, reserved in all other cases */
1013 #define ICE_AQC_DCB_DIS		0
1014 #define ICE_AQC_PFC_VLAN_BASED_PFC	1
1015 #define ICE_AQC_PFC_DSCP_BASED_PFC	2
1016 	u8	rsvd[15];
1017 };
1018 
1019 /* Set DCB Parameters (direct 0x0306) */
1020 struct ice_aqc_set_dcb_params {
1021 	u8 cmd_flags; /* unused in response */
1022 #define ICE_AQC_LINK_UP_DCB_CFG    BIT(0)
1023 #define ICE_AQC_PERSIST_DCB_CFG    BIT(1)
1024 	u8 valid_flags; /* unused in response */
1025 #define ICE_AQC_LINK_UP_DCB_CFG_VALID    BIT(0)
1026 #define ICE_AQC_PERSIST_DCB_CFG_VALID    BIT(1)
1027 	u8 rsvd[14];
1028 };
1029 
1030 /* Get Default Topology (indirect 0x0400) */
1031 struct ice_aqc_get_topo {
1032 	u8 port_num;
1033 	u8 num_branches;
1034 	__le16 reserved1;
1035 	__le32 reserved2;
1036 	__le32 addr_high;
1037 	__le32 addr_low;
1038 };
1039 
1040 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */
1041 struct ice_aqc_get_set_tx_topo {
1042 	u8 set_flags;
1043 #define ICE_AQC_TX_TOPO_FLAGS_CORRER		BIT(0)
1044 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM		BIT(1)
1045 #define ICE_AQC_TX_TOPO_FLAGS_SET_PSM		BIT(2)
1046 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW		BIT(4)
1047 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED		BIT(5)
1048 	u8 get_flags;
1049 #define ICE_AQC_TX_TOPO_GET_NO_UPDATE		0
1050 #define ICE_AQC_TX_TOPO_GET_PSM			1
1051 #define ICE_AQC_TX_TOPO_GET_RAM			2
1052 	__le16 reserved1;
1053 	__le32 reserved2;
1054 	__le32 addr_high;
1055 	__le32 addr_low;
1056 };
1057 
1058 /* Update TSE (indirect 0x0403)
1059  * Get TSE (indirect 0x0404)
1060  * Add TSE (indirect 0x0401)
1061  * Delete TSE (indirect 0x040F)
1062  * Move TSE (indirect 0x0408)
1063  * Suspend Nodes (indirect 0x0409)
1064  * Resume Nodes (indirect 0x040A)
1065  */
1066 struct ice_aqc_sched_elem_cmd {
1067 	__le16 num_elem_req;	/* Used by commands */
1068 	__le16 num_elem_resp;	/* Used by responses */
1069 	__le32 reserved;
1070 	__le32 addr_high;
1071 	__le32 addr_low;
1072 };
1073 
1074 struct ice_aqc_txsched_move_grp_info_hdr {
1075 	__le32 src_parent_teid;
1076 	__le32 dest_parent_teid;
1077 	__le16 num_elems;
1078 	u8 flags;
1079 	u8 reserved;
1080 };
1081 
1082 struct ice_aqc_move_elem {
1083 	struct ice_aqc_txsched_move_grp_info_hdr hdr;
1084 	__le32 teid[STRUCT_HACK_VAR_LEN];
1085 };
1086 
1087 struct ice_aqc_elem_info_bw {
1088 	__le16 bw_profile_idx;
1089 	__le16 bw_alloc;
1090 };
1091 
1092 struct ice_aqc_txsched_elem {
1093 	u8 elem_type; /* Special field, reserved for some aq calls */
1094 #define ICE_AQC_ELEM_TYPE_UNDEFINED		0x0
1095 #define ICE_AQC_ELEM_TYPE_ROOT_PORT		0x1
1096 #define ICE_AQC_ELEM_TYPE_TC			0x2
1097 #define ICE_AQC_ELEM_TYPE_SE_GENERIC		0x3
1098 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT		0x4
1099 #define ICE_AQC_ELEM_TYPE_LEAF			0x5
1100 #define ICE_AQC_ELEM_TYPE_SE_PADDED		0x6
1101 	u8 valid_sections;
1102 #define ICE_AQC_ELEM_VALID_GENERIC		BIT(0)
1103 #define ICE_AQC_ELEM_VALID_CIR			BIT(1)
1104 #define ICE_AQC_ELEM_VALID_EIR			BIT(2)
1105 #define ICE_AQC_ELEM_VALID_SHARED		BIT(3)
1106 	u8 generic;
1107 #define ICE_AQC_ELEM_GENERIC_MODE_M		0x1
1108 #define ICE_AQC_ELEM_GENERIC_PRIO_S		0x1
1109 #define ICE_AQC_ELEM_GENERIC_PRIO_M		(0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
1110 #define ICE_AQC_ELEM_GENERIC_SP_S		0x4
1111 #define ICE_AQC_ELEM_GENERIC_SP_M		(0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
1112 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S	0x5
1113 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M	\
1114 	(0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
1115 	u8 flags; /* Special field, reserved for some aq calls */
1116 #define ICE_AQC_ELEM_FLAG_SUSPEND_M		0x1
1117 	struct ice_aqc_elem_info_bw cir_bw;
1118 	struct ice_aqc_elem_info_bw eir_bw;
1119 	__le16 srl_id;
1120 	__le16 reserved2;
1121 };
1122 
1123 struct ice_aqc_txsched_elem_data {
1124 	__le32 parent_teid;
1125 	__le32 node_teid;
1126 	struct ice_aqc_txsched_elem data;
1127 };
1128 
1129 struct ice_aqc_txsched_topo_grp_info_hdr {
1130 	__le32 parent_teid;
1131 	__le16 num_elems;
1132 	__le16 reserved2;
1133 };
1134 
1135 struct ice_aqc_add_elem {
1136 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1137 	struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN];
1138 };
1139 
1140 struct ice_aqc_get_topo_elem {
1141 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1142 	struct ice_aqc_txsched_elem_data
1143 		generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1144 };
1145 
1146 struct ice_aqc_delete_elem {
1147 	struct ice_aqc_txsched_topo_grp_info_hdr hdr;
1148 	__le32 teid[STRUCT_HACK_VAR_LEN];
1149 };
1150 
1151 /* Query Port ETS (indirect 0x040E)
1152  *
1153  * This indirect command is used to query port TC node configuration.
1154  */
1155 struct ice_aqc_query_port_ets {
1156 	__le32 port_teid;
1157 	__le32 reserved;
1158 	__le32 addr_high;
1159 	__le32 addr_low;
1160 };
1161 
1162 struct ice_aqc_port_ets_elem {
1163 	u8 tc_valid_bits;
1164 	u8 reserved[3];
1165 	/* 3 bits for UP per TC 0-7, 4th byte reserved */
1166 	__le32 up2tc;
1167 	u8 tc_bw_share[8];
1168 	__le32 port_eir_prof_id;
1169 	__le32 port_cir_prof_id;
1170 	/* 3 bits per Node priority to TC 0-7, 4th byte reserved */
1171 	__le32 tc_node_prio;
1172 #define ICE_TC_NODE_PRIO_S	0x4
1173 	u8 reserved1[4];
1174 	__le32 tc_node_teid[8]; /* Used for response, reserved in command */
1175 };
1176 
1177 /* Rate limiting profile for
1178  * Add RL profile (indirect 0x0410)
1179  * Query RL profile (indirect 0x0411)
1180  * Remove RL profile (indirect 0x0415)
1181  * These indirect commands acts on single or multiple
1182  * RL profiles with specified data.
1183  */
1184 struct ice_aqc_rl_profile {
1185 	__le16 num_profiles;
1186 	__le16 num_processed; /* Only for response. Reserved in Command. */
1187 	u8 reserved[4];
1188 	__le32 addr_high;
1189 	__le32 addr_low;
1190 };
1191 
1192 struct ice_aqc_rl_profile_elem {
1193 	u8 level;
1194 	u8 flags;
1195 #define ICE_AQC_RL_PROFILE_TYPE_S	0x0
1196 #define ICE_AQC_RL_PROFILE_TYPE_M	(0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
1197 #define ICE_AQC_RL_PROFILE_TYPE_CIR	0
1198 #define ICE_AQC_RL_PROFILE_TYPE_EIR	1
1199 #define ICE_AQC_RL_PROFILE_TYPE_SRL	2
1200 /* The following flag is used for Query RL Profile Data */
1201 #define ICE_AQC_RL_PROFILE_INVAL_S	0x7
1202 #define ICE_AQC_RL_PROFILE_INVAL_M	(0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
1203 
1204 	__le16 profile_id;
1205 	__le16 max_burst_size;
1206 	__le16 rl_multiply;
1207 	__le16 wake_up_calc;
1208 	__le16 rl_encode;
1209 };
1210 
1211 /* Config Node Attributes (indirect 0x0419)
1212  * Query Node Attributes (indirect 0x041A)
1213  */
1214 struct ice_aqc_node_attr {
1215 	__le16 num_entries; /* Number of attributes structures in the buffer */
1216 	u8 reserved[6];
1217 	__le32 addr_high;
1218 	__le32 addr_low;
1219 };
1220 
1221 struct ice_aqc_node_attr_elem {
1222 	__le32 node_teid;
1223 	__le16 max_children;
1224 	__le16 children_level;
1225 };
1226 
1227 /* Configure L2 Node CGD (indirect 0x0414)
1228  * This indirect command allows configuring a congestion domain for given L2
1229  * node TEIDs in the scheduler topology.
1230  */
1231 struct ice_aqc_cfg_l2_node_cgd {
1232 	__le16 num_l2_nodes;
1233 	u8 reserved[6];
1234 	__le32 addr_high;
1235 	__le32 addr_low;
1236 };
1237 
1238 struct ice_aqc_cfg_l2_node_cgd_elem {
1239 	__le32 node_teid;
1240 	u8 cgd;
1241 	u8 reserved[3];
1242 };
1243 
1244 /* Query Scheduler Resource Allocation (indirect 0x0412)
1245  * This indirect command retrieves the scheduler resources allocated by
1246  * EMP Firmware to the given PF.
1247  */
1248 struct ice_aqc_query_txsched_res {
1249 	u8 reserved[8];
1250 	__le32 addr_high;
1251 	__le32 addr_low;
1252 };
1253 
1254 struct ice_aqc_generic_sched_props {
1255 	__le16 phys_levels;
1256 	__le16 logical_levels;
1257 	u8 flattening_bitmap;
1258 	u8 max_device_cgds;
1259 	u8 max_pf_cgds;
1260 	u8 rsvd0;
1261 	__le16 rdma_qsets;
1262 	u8 rsvd1[22];
1263 };
1264 
1265 struct ice_aqc_layer_props {
1266 	u8 logical_layer;
1267 	u8 chunk_size;
1268 	__le16 max_device_nodes;
1269 	__le16 max_pf_nodes;
1270 	u8 rsvd0[4];
1271 	__le16 max_sibl_grp_sz;
1272 	__le16 max_cir_rl_profiles;
1273 	__le16 max_eir_rl_profiles;
1274 	__le16 max_srl_profiles;
1275 	u8 rsvd1[14];
1276 };
1277 
1278 struct ice_aqc_query_txsched_res_resp {
1279 	struct ice_aqc_generic_sched_props sched_props;
1280 	struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
1281 };
1282 
1283 /* Query Node to Root Topology (indirect 0x0413)
1284  * This command uses ice_aqc_get_elem as its data buffer.
1285  */
1286 struct ice_aqc_query_node_to_root {
1287 	__le32 teid;
1288 	__le32 num_nodes; /* Response only */
1289 	__le32 addr_high;
1290 	__le32 addr_low;
1291 };
1292 
1293 /* Get PHY capabilities (indirect 0x0600) */
1294 struct ice_aqc_get_phy_caps {
1295 	u8 lport_num;
1296 	u8 reserved;
1297 	__le16 param0;
1298 	/* 18.0 - Report qualified modules */
1299 #define ICE_AQC_GET_PHY_RQM		BIT(0)
1300 	/* 18.1 - 18.3 : Report mode
1301 	 * 000b - Report topology capabilities, without media
1302 	 * 001b - Report topology capabilities, with media
1303 	 * 010b - Report Active configuration
1304 	 * 011b - Report PHY Type and FEC mode capabilities
1305 	 * 100b - Report Default capabilities
1306 	 */
1307 #define ICE_AQC_REPORT_MODE_S			1
1308 #define ICE_AQC_REPORT_MODE_M			(7 << ICE_AQC_REPORT_MODE_S)
1309 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA	0
1310 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA		BIT(1)
1311 #define ICE_AQC_REPORT_ACTIVE_CFG		BIT(2)
1312 #define ICE_AQC_REPORT_DFLT_CFG			BIT(3)
1313 	__le32 reserved1;
1314 	__le32 addr_high;
1315 	__le32 addr_low;
1316 };
1317 
1318 /* This is #define of PHY type (Extended):
1319  * The first set of defines is for phy_type_low.
1320  */
1321 #define ICE_PHY_TYPE_LOW_100BASE_TX		BIT_ULL(0)
1322 #define ICE_PHY_TYPE_LOW_100M_SGMII		BIT_ULL(1)
1323 #define ICE_PHY_TYPE_LOW_1000BASE_T		BIT_ULL(2)
1324 #define ICE_PHY_TYPE_LOW_1000BASE_SX		BIT_ULL(3)
1325 #define ICE_PHY_TYPE_LOW_1000BASE_LX		BIT_ULL(4)
1326 #define ICE_PHY_TYPE_LOW_1000BASE_KX		BIT_ULL(5)
1327 #define ICE_PHY_TYPE_LOW_1G_SGMII		BIT_ULL(6)
1328 #define ICE_PHY_TYPE_LOW_2500BASE_T		BIT_ULL(7)
1329 #define ICE_PHY_TYPE_LOW_2500BASE_X		BIT_ULL(8)
1330 #define ICE_PHY_TYPE_LOW_2500BASE_KX		BIT_ULL(9)
1331 #define ICE_PHY_TYPE_LOW_5GBASE_T		BIT_ULL(10)
1332 #define ICE_PHY_TYPE_LOW_5GBASE_KR		BIT_ULL(11)
1333 #define ICE_PHY_TYPE_LOW_10GBASE_T		BIT_ULL(12)
1334 #define ICE_PHY_TYPE_LOW_10G_SFI_DA		BIT_ULL(13)
1335 #define ICE_PHY_TYPE_LOW_10GBASE_SR		BIT_ULL(14)
1336 #define ICE_PHY_TYPE_LOW_10GBASE_LR		BIT_ULL(15)
1337 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1		BIT_ULL(16)
1338 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC	BIT_ULL(17)
1339 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C		BIT_ULL(18)
1340 #define ICE_PHY_TYPE_LOW_25GBASE_T		BIT_ULL(19)
1341 #define ICE_PHY_TYPE_LOW_25GBASE_CR		BIT_ULL(20)
1342 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S		BIT_ULL(21)
1343 #define ICE_PHY_TYPE_LOW_25GBASE_CR1		BIT_ULL(22)
1344 #define ICE_PHY_TYPE_LOW_25GBASE_SR		BIT_ULL(23)
1345 #define ICE_PHY_TYPE_LOW_25GBASE_LR		BIT_ULL(24)
1346 #define ICE_PHY_TYPE_LOW_25GBASE_KR		BIT_ULL(25)
1347 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S		BIT_ULL(26)
1348 #define ICE_PHY_TYPE_LOW_25GBASE_KR1		BIT_ULL(27)
1349 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC	BIT_ULL(28)
1350 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C		BIT_ULL(29)
1351 #define ICE_PHY_TYPE_LOW_40GBASE_CR4		BIT_ULL(30)
1352 #define ICE_PHY_TYPE_LOW_40GBASE_SR4		BIT_ULL(31)
1353 #define ICE_PHY_TYPE_LOW_40GBASE_LR4		BIT_ULL(32)
1354 #define ICE_PHY_TYPE_LOW_40GBASE_KR4		BIT_ULL(33)
1355 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC	BIT_ULL(34)
1356 #define ICE_PHY_TYPE_LOW_40G_XLAUI		BIT_ULL(35)
1357 #define ICE_PHY_TYPE_LOW_50GBASE_CR2		BIT_ULL(36)
1358 #define ICE_PHY_TYPE_LOW_50GBASE_SR2		BIT_ULL(37)
1359 #define ICE_PHY_TYPE_LOW_50GBASE_LR2		BIT_ULL(38)
1360 #define ICE_PHY_TYPE_LOW_50GBASE_KR2		BIT_ULL(39)
1361 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC	BIT_ULL(40)
1362 #define ICE_PHY_TYPE_LOW_50G_LAUI2		BIT_ULL(41)
1363 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC	BIT_ULL(42)
1364 #define ICE_PHY_TYPE_LOW_50G_AUI2		BIT_ULL(43)
1365 #define ICE_PHY_TYPE_LOW_50GBASE_CP		BIT_ULL(44)
1366 #define ICE_PHY_TYPE_LOW_50GBASE_SR		BIT_ULL(45)
1367 #define ICE_PHY_TYPE_LOW_50GBASE_FR		BIT_ULL(46)
1368 #define ICE_PHY_TYPE_LOW_50GBASE_LR		BIT_ULL(47)
1369 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4	BIT_ULL(48)
1370 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC	BIT_ULL(49)
1371 #define ICE_PHY_TYPE_LOW_50G_AUI1		BIT_ULL(50)
1372 #define ICE_PHY_TYPE_LOW_100GBASE_CR4		BIT_ULL(51)
1373 #define ICE_PHY_TYPE_LOW_100GBASE_SR4		BIT_ULL(52)
1374 #define ICE_PHY_TYPE_LOW_100GBASE_LR4		BIT_ULL(53)
1375 #define ICE_PHY_TYPE_LOW_100GBASE_KR4		BIT_ULL(54)
1376 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC	BIT_ULL(55)
1377 #define ICE_PHY_TYPE_LOW_100G_CAUI4		BIT_ULL(56)
1378 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC	BIT_ULL(57)
1379 #define ICE_PHY_TYPE_LOW_100G_AUI4		BIT_ULL(58)
1380 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4	BIT_ULL(59)
1381 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4	BIT_ULL(60)
1382 #define ICE_PHY_TYPE_LOW_100GBASE_CP2		BIT_ULL(61)
1383 #define ICE_PHY_TYPE_LOW_100GBASE_SR2		BIT_ULL(62)
1384 #define ICE_PHY_TYPE_LOW_100GBASE_DR		BIT_ULL(63)
1385 #define ICE_PHY_TYPE_LOW_MAX_INDEX		63
1386 /* The second set of defines is for phy_type_high. */
1387 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4	BIT_ULL(0)
1388 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC	BIT_ULL(1)
1389 #define ICE_PHY_TYPE_HIGH_100G_CAUI2		BIT_ULL(2)
1390 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC	BIT_ULL(3)
1391 #define ICE_PHY_TYPE_HIGH_100G_AUI2		BIT_ULL(4)
1392 #define ICE_PHY_TYPE_HIGH_MAX_INDEX		4
1393 
1394 struct ice_aqc_get_phy_caps_data {
1395 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1396 	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1397 	u8 caps;
1398 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE			BIT(0)
1399 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE			BIT(1)
1400 #define ICE_AQC_PHY_LOW_POWER_MODE			BIT(2)
1401 #define ICE_AQC_PHY_EN_LINK				BIT(3)
1402 #define ICE_AQC_PHY_AN_MODE				BIT(4)
1403 #define ICE_AQC_PHY_EN_MOD_QUAL				BIT(5)
1404 #define ICE_AQC_PHY_EN_LESM				BIT(6)
1405 #define ICE_AQC_PHY_EN_AUTO_FEC				BIT(7)
1406 #define ICE_AQC_PHY_CAPS_MASK				MAKEMASK(0xff, 0)
1407 	u8 low_power_ctrl_an;
1408 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG		BIT(0)
1409 #define ICE_AQC_PHY_AN_EN_CLAUSE28			BIT(1)
1410 #define ICE_AQC_PHY_AN_EN_CLAUSE73			BIT(2)
1411 #define ICE_AQC_PHY_AN_EN_CLAUSE37			BIT(3)
1412 	__le16 eee_cap;
1413 #define ICE_AQC_PHY_EEE_EN_100BASE_TX			BIT(0)
1414 #define ICE_AQC_PHY_EEE_EN_1000BASE_T			BIT(1)
1415 #define ICE_AQC_PHY_EEE_EN_10GBASE_T			BIT(2)
1416 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX			BIT(3)
1417 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR			BIT(4)
1418 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR			BIT(5)
1419 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4			BIT(6)
1420 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2			BIT(7)
1421 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4		BIT(8)
1422 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4			BIT(9)
1423 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4		BIT(10)
1424 	__le16 eeer_value;
1425 	u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1426 	u8 phy_fw_ver[8];
1427 	u8 link_fec_options;
1428 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN		BIT(0)
1429 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ		BIT(1)
1430 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ			BIT(2)
1431 #define ICE_AQC_PHY_FEC_25G_KR_REQ			BIT(3)
1432 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ			BIT(4)
1433 #define ICE_AQC_PHY_FEC_DIS				BIT(5)
1434 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN		BIT(6)
1435 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN		BIT(7)
1436 #define ICE_AQC_PHY_FEC_MASK				MAKEMASK(0xdf, 0)
1437 	u8 module_compliance_enforcement;
1438 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE			BIT(0)
1439 	u8 extended_compliance_code;
1440 #define ICE_MODULE_TYPE_TOTAL_BYTE			3
1441 	u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1442 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS			0xA0
1443 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS		0x80
1444 #define ICE_AQC_MOD_TYPE_IDENT				1
1445 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE	BIT(0)
1446 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE	BIT(1)
1447 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR		BIT(4)
1448 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR		BIT(5)
1449 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM		BIT(6)
1450 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER		BIT(7)
1451 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS			0xA0
1452 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS		0x86
1453 	u8 qualified_module_count;
1454 	u8 rsvd2[7];	/* Bytes 47:41 reserved */
1455 #define ICE_AQC_QUAL_MOD_COUNT_MAX			16
1456 	struct {
1457 		u8 v_oui[3];
1458 		u8 rsvd3;
1459 		u8 v_part[16];
1460 		__le32 v_rev;
1461 		__le64 rsvd4;
1462 	} qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1463 };
1464 
1465 /* Set PHY capabilities (direct 0x0601)
1466  * NOTE: This command must be followed by setup link and restart auto-neg
1467  */
1468 struct ice_aqc_set_phy_cfg {
1469 	u8 lport_num;
1470 	u8 reserved[7];
1471 	__le32 addr_high;
1472 	__le32 addr_low;
1473 };
1474 
1475 /* Set PHY config command data structure */
1476 struct ice_aqc_set_phy_cfg_data {
1477 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1478 	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1479 	u8 caps;
1480 #define ICE_AQ_PHY_ENA_VALID_MASK	MAKEMASK(0xef, 0)
1481 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY	BIT(0)
1482 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY	BIT(1)
1483 #define ICE_AQ_PHY_ENA_LOW_POWER	BIT(2)
1484 #define ICE_AQ_PHY_ENA_LINK		BIT(3)
1485 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT	BIT(5)
1486 #define ICE_AQ_PHY_ENA_LESM		BIT(6)
1487 #define ICE_AQ_PHY_ENA_AUTO_FEC		BIT(7)
1488 	u8 low_power_ctrl_an;
1489 	__le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1490 	__le16 eeer_value;
1491 	u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1492 	u8 module_compliance_enforcement;
1493 };
1494 
1495 /* Set MAC Config command data structure (direct 0x0603) */
1496 struct ice_aqc_set_mac_cfg {
1497 	__le16 max_frame_size;
1498 	u8 params;
1499 #define ICE_AQ_SET_MAC_PACE_S		3
1500 #define ICE_AQ_SET_MAC_PACE_M		(0xF << ICE_AQ_SET_MAC_PACE_S)
1501 #define ICE_AQ_SET_MAC_PACE_TYPE_M	BIT(7)
1502 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE	0
1503 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED	ICE_AQ_SET_MAC_PACE_TYPE_M
1504 	u8 tx_tmr_priority;
1505 	__le16 tx_tmr_value;
1506 	__le16 fc_refresh_threshold;
1507 	u8 drop_opts;
1508 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK		BIT(0)
1509 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE		0
1510 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS	BIT(0)
1511 	u8 reserved[7];
1512 };
1513 
1514 /* Restart AN command data structure (direct 0x0605)
1515  * Also used for response, with only the lport_num field present.
1516  */
1517 struct ice_aqc_restart_an {
1518 	u8 lport_num;
1519 	u8 reserved;
1520 	u8 cmd_flags;
1521 #define ICE_AQC_RESTART_AN_LINK_RESTART	BIT(1)
1522 #define ICE_AQC_RESTART_AN_LINK_ENABLE	BIT(2)
1523 	u8 reserved2[13];
1524 };
1525 
1526 /* Get link status (indirect 0x0607), also used for Link Status Event */
1527 struct ice_aqc_get_link_status {
1528 	u8 lport_num;
1529 	u8 reserved;
1530 	__le16 cmd_flags;
1531 #define ICE_AQ_LSE_M			0x3
1532 #define ICE_AQ_LSE_NOP			0x0
1533 #define ICE_AQ_LSE_DIS			0x2
1534 #define ICE_AQ_LSE_ENA			0x3
1535 	/* only response uses this flag */
1536 #define ICE_AQ_LSE_IS_ENABLED		0x1
1537 	__le32 reserved2;
1538 	__le32 addr_high;
1539 	__le32 addr_low;
1540 };
1541 
1542 enum ice_get_link_status_data_version {
1543 	ICE_GET_LINK_STATUS_DATA_V1 = 1,
1544 };
1545 
1546 #define ICE_GET_LINK_STATUS_DATALEN_V1		32
1547 
1548 /* Get link status response data structure, also used for Link Status Event */
1549 struct ice_aqc_get_link_status_data {
1550 	u8 topo_media_conflict;
1551 #define ICE_AQ_LINK_TOPO_CONFLICT	BIT(0)
1552 #define ICE_AQ_LINK_MEDIA_CONFLICT	BIT(1)
1553 #define ICE_AQ_LINK_TOPO_CORRUPT	BIT(2)
1554 #define ICE_AQ_LINK_TOPO_UNREACH_PRT	BIT(4)
1555 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT	BIT(5)
1556 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA	BIT(6)
1557 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA	BIT(7)
1558 	u8 link_cfg_err;
1559 #define ICE_AQ_LINK_CFG_ERR			BIT(0)
1560 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL		BIT(2)
1561 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL	BIT(3)
1562 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR	BIT(4)
1563 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED	BIT(5)
1564 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE	BIT(6)
1565 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT	BIT(7)
1566 	u8 link_info;
1567 #define ICE_AQ_LINK_UP			BIT(0)	/* Link Status */
1568 #define ICE_AQ_LINK_FAULT		BIT(1)
1569 #define ICE_AQ_LINK_FAULT_TX		BIT(2)
1570 #define ICE_AQ_LINK_FAULT_RX		BIT(3)
1571 #define ICE_AQ_LINK_FAULT_REMOTE	BIT(4)
1572 #define ICE_AQ_LINK_UP_PORT		BIT(5)	/* External Port Link Status */
1573 #define ICE_AQ_MEDIA_AVAILABLE		BIT(6)
1574 #define ICE_AQ_SIGNAL_DETECT		BIT(7)
1575 	u8 an_info;
1576 #define ICE_AQ_AN_COMPLETED		BIT(0)
1577 #define ICE_AQ_LP_AN_ABILITY		BIT(1)
1578 #define ICE_AQ_PD_FAULT			BIT(2)	/* Parallel Detection Fault */
1579 #define ICE_AQ_FEC_EN			BIT(3)
1580 #define ICE_AQ_PHY_LOW_POWER		BIT(4)	/* Low Power State */
1581 #define ICE_AQ_LINK_PAUSE_TX		BIT(5)
1582 #define ICE_AQ_LINK_PAUSE_RX		BIT(6)
1583 #define ICE_AQ_QUALIFIED_MODULE		BIT(7)
1584 	u8 ext_info;
1585 #define ICE_AQ_LINK_PHY_TEMP_ALARM	BIT(0)
1586 #define ICE_AQ_LINK_EXCESSIVE_ERRORS	BIT(1)	/* Excessive Link Errors */
1587 	/* Port Tx Suspended */
1588 #define ICE_AQ_LINK_TX_S		2
1589 #define ICE_AQ_LINK_TX_M		(0x03 << ICE_AQ_LINK_TX_S)
1590 #define ICE_AQ_LINK_TX_ACTIVE		0
1591 #define ICE_AQ_LINK_TX_DRAINED		1
1592 #define ICE_AQ_LINK_TX_FLUSHED		3
1593 	u8 lb_status;
1594 #define ICE_AQ_LINK_LB_PHY_LCL		BIT(0)
1595 #define ICE_AQ_LINK_LB_PHY_RMT		BIT(1)
1596 #define ICE_AQ_LINK_LB_MAC_LCL		BIT(2)
1597 #define ICE_AQ_LINK_LB_PHY_IDX_S	3
1598 #define ICE_AQ_LINK_LB_PHY_IDX_M	(0x7 << ICE_AQ_LB_PHY_IDX_S)
1599 	__le16 max_frame_size;
1600 	u8 cfg;
1601 #define ICE_AQ_LINK_25G_KR_FEC_EN	BIT(0)
1602 #define ICE_AQ_LINK_25G_RS_528_FEC_EN	BIT(1)
1603 #define ICE_AQ_LINK_25G_RS_544_FEC_EN	BIT(2)
1604 #define ICE_AQ_FEC_MASK			MAKEMASK(0x7, 0)
1605 	/* Pacing Config */
1606 #define ICE_AQ_CFG_PACING_S		3
1607 #define ICE_AQ_CFG_PACING_M		(0xF << ICE_AQ_CFG_PACING_S)
1608 #define ICE_AQ_CFG_PACING_TYPE_M	BIT(7)
1609 #define ICE_AQ_CFG_PACING_TYPE_AVG	0
1610 #define ICE_AQ_CFG_PACING_TYPE_FIXED	ICE_AQ_CFG_PACING_TYPE_M
1611 	/* External Device Power Ability */
1612 	u8 power_desc;
1613 #define ICE_AQ_PWR_CLASS_M		0x3F
1614 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH	0
1615 #define ICE_AQ_LINK_PWR_BASET_HIGH	1
1616 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1	0
1617 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2	1
1618 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3	2
1619 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4	3
1620 	__le16 link_speed;
1621 #define ICE_AQ_LINK_SPEED_M		0x7FF
1622 #define ICE_AQ_LINK_SPEED_10MB		BIT(0)
1623 #define ICE_AQ_LINK_SPEED_100MB		BIT(1)
1624 #define ICE_AQ_LINK_SPEED_1000MB	BIT(2)
1625 #define ICE_AQ_LINK_SPEED_2500MB	BIT(3)
1626 #define ICE_AQ_LINK_SPEED_5GB		BIT(4)
1627 #define ICE_AQ_LINK_SPEED_10GB		BIT(5)
1628 #define ICE_AQ_LINK_SPEED_20GB		BIT(6)
1629 #define ICE_AQ_LINK_SPEED_25GB		BIT(7)
1630 #define ICE_AQ_LINK_SPEED_40GB		BIT(8)
1631 #define ICE_AQ_LINK_SPEED_50GB		BIT(9)
1632 #define ICE_AQ_LINK_SPEED_100GB		BIT(10)
1633 #define ICE_AQ_LINK_SPEED_UNKNOWN	BIT(15)
1634 	__le32 reserved3; /* Aligns next field to 8-byte boundary */
1635 	__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1636 	__le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1637 };
1638 
1639 /* Set event mask command (direct 0x0613) */
1640 struct ice_aqc_set_event_mask {
1641 	u8	lport_num;
1642 	u8	reserved[7];
1643 	__le16	event_mask;
1644 #define ICE_AQ_LINK_EVENT_UPDOWN		BIT(1)
1645 #define ICE_AQ_LINK_EVENT_MEDIA_NA		BIT(2)
1646 #define ICE_AQ_LINK_EVENT_LINK_FAULT		BIT(3)
1647 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM	BIT(4)
1648 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS	BIT(5)
1649 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT		BIT(6)
1650 #define ICE_AQ_LINK_EVENT_AN_COMPLETED		BIT(7)
1651 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL	BIT(8)
1652 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED	BIT(9)
1653 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT		BIT(10)
1654 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT	BIT(11)
1655 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL	BIT(12)
1656 	u8	reserved1[6];
1657 };
1658 
1659 /* Set PHY Loopback command (direct 0x0619) */
1660 struct ice_aqc_set_phy_lb {
1661 	u8 lport_num;
1662 	u8 lport_num_valid;
1663 #define ICE_AQ_PHY_LB_PORT_NUM_VALID	BIT(0)
1664 	u8 phy_index;
1665 	u8 lb_mode;
1666 #define ICE_AQ_PHY_LB_EN		BIT(0)
1667 #define ICE_AQ_PHY_LB_TYPE_M		BIT(1)
1668 #define ICE_AQ_PHY_LB_TYPE_LOCAL	0
1669 #define ICE_AQ_PHY_LB_TYPE_REMOTE	ICE_AQ_PHY_LB_TYPE_M
1670 #define ICE_AQ_PHY_LB_LEVEL_M		BIT(2)
1671 #define ICE_AQ_PHY_LB_LEVEL_PMD		0
1672 #define ICE_AQ_PHY_LB_LEVEL_PCS		ICE_AQ_PHY_LB_LEVEL_M
1673 	u8 reserved2[12];
1674 };
1675 
1676 /* Set MAC Loopback command (direct 0x0620) */
1677 struct ice_aqc_set_mac_lb {
1678 	u8 lb_mode;
1679 #define ICE_AQ_MAC_LB_EN		BIT(0)
1680 #define ICE_AQ_MAC_LB_OSC_CLK		BIT(1)
1681 	u8 reserved[15];
1682 };
1683 
1684 /* Get sensor reading (direct 0x0632) */
1685 struct ice_aqc_get_sensor_reading {
1686 	u8 sensor;
1687 #define ICE_AQC_INT_TEMP_SENSOR		0x0
1688 	u8 format;
1689 #define ICE_AQC_INT_TEMP_FORMAT		0x0
1690 	u8 reserved[6];
1691 	__le32 addr_high;
1692 	__le32 addr_low;
1693 };
1694 
1695 /* Get sensor reading response (direct 0x0632) */
1696 struct ice_aqc_get_sensor_reading_resp {
1697 	union {
1698 		u8 raw[8];
1699 		/* Output data for sensor 0x00, format 0x00 */
1700 		struct {
1701 			s8 temp;
1702 			u8 temp_warning_threshold;
1703 			u8 temp_critical_threshold;
1704 			u8 temp_fatal_threshold;
1705 			u8 reserved[4];
1706 		} s0f0;
1707 	} data;
1708 };
1709 
1710 /* DNL Get Status command (indirect 0x0680)
1711  * Structure used for the response, the command uses the generic
1712  * ice_aqc_generic struct to pass a buffer address to the FW.
1713  */
1714 struct ice_aqc_dnl_get_status {
1715 	u8 ctx;
1716 	u8 status;
1717 #define ICE_AQ_DNL_STATUS_IDLE		0x0
1718 #define ICE_AQ_DNL_STATUS_RESERVED	0x1
1719 #define ICE_AQ_DNL_STATUS_STOPPED	0x2
1720 #define ICE_AQ_DNL_STATUS_FATAL		0x3 /* Fatal DNL engine error */
1721 #define ICE_AQ_DNL_SRC_S		3
1722 #define ICE_AQ_DNL_SRC_M		(0x3 << ICE_AQ_DNL_SRC_S)
1723 #define ICE_AQ_DNL_SRC_NVM		(0x0 << ICE_AQ_DNL_SRC_S)
1724 #define ICE_AQ_DNL_SRC_NVM_SCRATCH	(0x1 << ICE_AQ_DNL_SRC_S)
1725 	u8 stack_ptr;
1726 #define ICE_AQ_DNL_ST_PTR_S		0x0
1727 #define ICE_AQ_DNL_ST_PTR_M		(0x7 << ICE_AQ_DNL_ST_PTR_S)
1728 	u8 engine_flags;
1729 #define ICE_AQ_DNL_FLAGS_ERROR		BIT(2)
1730 #define ICE_AQ_DNL_FLAGS_NEGATIVE	BIT(3)
1731 #define ICE_AQ_DNL_FLAGS_OVERFLOW	BIT(4)
1732 #define ICE_AQ_DNL_FLAGS_ZERO		BIT(5)
1733 #define ICE_AQ_DNL_FLAGS_CARRY		BIT(6)
1734 #define ICE_AQ_DNL_FLAGS_JUMP		BIT(7)
1735 	__le16 pc;
1736 	__le16 activity_id;
1737 	__le32 addr_high;
1738 	__le32 addr_low;
1739 };
1740 
1741 struct ice_aqc_dnl_get_status_data {
1742 	__le16 activity_err_code;
1743 	__le16 act_err_code;
1744 #define ICE_AQ_DNL_ACT_ERR_SUCCESS	0x0000 /* no error */
1745 #define ICE_AQ_DNL_ACT_ERR_PARSE	0x8001 /* NVM parse error */
1746 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED	0x8002 /* unsupported action */
1747 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND	0x8003 /* activity not found */
1748 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP	0x8004 /* an illegal jump */
1749 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER	0x8005 /* persistent store overflow */
1750 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW	0x8006 /* stack overflow */
1751 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT	0x8007 /* activity timeout */
1752 #define ICE_AQ_DNL_ACT_ERR_BREAK	0x0008 /* stopped at breakpoint */
1753 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG	0x0101 /* invalid action argument */
1754 	__le32 execution_time; /* in nanoseconds */
1755 	__le16 lib_ver;
1756 	u8 psto_local_sz;
1757 	u8 psto_global_sz;
1758 	u8 stack_sz;
1759 #define ICE_AQ_DNL_STACK_SZ_S		0
1760 #define ICE_AQ_DNL_STACK_SZ_M		(0xF << ICE_AQ_DNL_STACK_SZ_S)
1761 	u8 port_count;
1762 #define ICE_AQ_DNL_PORT_CNT_S		0
1763 #define ICE_AQ_DNL_PORT_CNT_M		(0x1F << ICE_AQ_DNL_PORT_CNT_S)
1764 	__le16 act_cache_cntr;
1765 	u32 i2c_clk_cntr;
1766 	u32 mdio_clk_cntr;
1767 	u32 sb_iosf_clk_cntr;
1768 };
1769 
1770 /* DNL run command (direct 0x0681) */
1771 struct ice_aqc_dnl_run_command {
1772 	u8 reserved0;
1773 	u8 command;
1774 #define ICE_AQ_DNL_CMD_S		0
1775 #define ICE_AQ_DNL_CMD_M		(0x7 << ICE_AQ_DNL_CMD_S)
1776 #define ICE_AQ_DNL_CMD_RESET		0x0
1777 #define ICE_AQ_DNL_CMD_RUN		0x1
1778 #define ICE_AQ_DNL_CMD_STEP		0x3
1779 #define ICE_AQ_DNL_CMD_ABORT		0x4
1780 #define ICE_AQ_DNL_CMD_SET_PC		0x7
1781 #define ICE_AQ_DNL_CMD_SRC_S		3
1782 #define ICE_AQ_DNL_CMD_SRC_M		(0x3 << ICE_AQ_DNL_CMD_SRC_S)
1783 #define ICE_AQ_DNL_CMD_SRC_DNL		0x0
1784 #define ICE_AQ_DNL_CMD_SRC_SCRATCH	0x1
1785 	__le16 new_pc;
1786 	u8 reserved1[12];
1787 };
1788 
1789 /* DNL call command (indirect 0x0682)
1790  * Struct is used for both command and response
1791  */
1792 struct ice_aqc_dnl_call_command {
1793 	u8 ctx; /* Used in command, reserved in response */
1794 	u8 reserved;
1795 	__le16 activity_id;
1796 	__le32 reserved1;
1797 	__le32 addr_high;
1798 	__le32 addr_low;
1799 };
1800 
1801 /* DNL call command/response buffer (indirect 0x0682) */
1802 struct ice_aqc_dnl_call {
1803 	__le32 stores[4];
1804 };
1805 
1806 /* Used for both commands:
1807  * DNL read sto command (indirect 0x0683)
1808  * DNL write sto command (indirect 0x0684)
1809  */
1810 struct ice_aqc_dnl_read_write_command {
1811 	u8 ctx;
1812 	u8 sto_sel; /* STORE select */
1813 #define ICE_AQC_DNL_STORE_SELECT_STORE	0x0
1814 #define ICE_AQC_DNL_STORE_SELECT_PSTO	0x1
1815 #define ICE_AQC_DNL_STORE_SELECT_STACK	0x2
1816 	__le16 offset;
1817 	__le32 data; /* Used for write sto only */
1818 	__le32 addr_high; /* Used for read sto only */
1819 	__le32 addr_low; /* Used for read sto only */
1820 };
1821 
1822 /* Used for both command responses:
1823  * DNL read sto response (indirect 0x0683)
1824  * DNL write sto response (indirect 0x0684)
1825  */
1826 struct ice_aqc_dnl_read_write_response {
1827 	u8 reserved;
1828 	u8 status; /* Reserved for read command */
1829 	__le16 size; /* Reserved for write command */
1830 	__le32 data; /* Reserved for write command */
1831 	__le32 addr_high; /* Reserved for write command */
1832 	__le32 addr_low; /* Reserved for write command */
1833 };
1834 
1835 /* DNL set breakpoints command (indirect 0x0686) */
1836 struct ice_aqc_dnl_set_breakpoints_command {
1837 	__le32 reserved[2];
1838 	__le32 addr_high;
1839 	__le32 addr_low;
1840 };
1841 
1842 /* DNL set breakpoints data buffer structure (indirect 0x0686) */
1843 struct ice_aqc_dnl_set_breakpoints {
1844 	u8 ctx;
1845 	u8 ena; /* 0- disabled, 1- enabled */
1846 	__le16 offset;
1847 	__le16 activity_id;
1848 };
1849 
1850 /* DNL read log data command(indirect 0x0687) */
1851 struct ice_aqc_dnl_read_log_command {
1852 	__le16 reserved0;
1853 	__le16 offset;
1854 	__le32 reserved1;
1855 	__le32 addr_high;
1856 	__le32 addr_low;
1857 
1858 };
1859 
1860 /* DNL read log data response(indirect 0x0687) */
1861 struct ice_aqc_dnl_read_log_response {
1862 	__le16 reserved;
1863 	__le16 size;
1864 	__le32 data;
1865 	__le32 addr_high;
1866 	__le32 addr_low;
1867 
1868 };
1869 
1870 struct ice_aqc_link_topo_params {
1871 	u8 lport_num;
1872 	u8 lport_num_valid;
1873 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID	BIT(0)
1874 	u8 node_type_ctx;
1875 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S		0
1876 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M	(0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1877 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY		0
1878 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL	1
1879 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL	2
1880 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL	3
1881 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED		4
1882 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL	5
1883 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE	6
1884 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ	7
1885 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM	8
1886 #define ICE_AQC_LINK_TOPO_NODE_CTX_S		4
1887 #define ICE_AQC_LINK_TOPO_NODE_CTX_M		\
1888 				(0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1889 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL	0
1890 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD	1
1891 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT		2
1892 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE		3
1893 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED	4
1894 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE	5
1895 	u8 index;
1896 };
1897 
1898 struct ice_aqc_link_topo_addr {
1899 	struct ice_aqc_link_topo_params topo_params;
1900 	__le16 handle;
1901 #define ICE_AQC_LINK_TOPO_HANDLE_S	0
1902 #define ICE_AQC_LINK_TOPO_HANDLE_M	(0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1903 /* Used to decode the handle field */
1904 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M	BIT(9)
1905 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM	BIT(9)
1906 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ	0
1907 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S		0
1908 /* In case of a Mezzanine type */
1909 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M	\
1910 				(0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1911 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S	6
1912 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M	(0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1913 /* In case of a LOM type */
1914 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M	\
1915 				(0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1916 };
1917 
1918 /* Get Link Topology Handle (direct, 0x06E0) */
1919 struct ice_aqc_get_link_topo {
1920 	struct ice_aqc_link_topo_addr addr;
1921 	u8 node_part_num;
1922 #define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575			0x21
1923 	u8 rsvd[9];
1924 };
1925 
1926 /* Read/Write I2C (direct, 0x06E2/0x06E3) */
1927 struct ice_aqc_i2c {
1928 	struct ice_aqc_link_topo_addr topo_addr;
1929 	__le16 i2c_addr;
1930 	u8 i2c_params;
1931 #define ICE_AQC_I2C_DATA_SIZE_S		0
1932 #define ICE_AQC_I2C_DATA_SIZE_M		(0xF << ICE_AQC_I2C_DATA_SIZE_S)
1933 #define ICE_AQC_I2C_ADDR_TYPE_M		BIT(4)
1934 #define ICE_AQC_I2C_ADDR_TYPE_7BIT	0
1935 #define ICE_AQC_I2C_ADDR_TYPE_10BIT	ICE_AQC_I2C_ADDR_TYPE_M
1936 #define ICE_AQC_I2C_DATA_OFFSET_S	5
1937 #define ICE_AQC_I2C_DATA_OFFSET_M	(0x3 << ICE_AQC_I2C_DATA_OFFSET_S)
1938 #define ICE_AQC_I2C_USE_REPEATED_START	BIT(7)
1939 	u8 rsvd;
1940 	__le16 i2c_bus_addr;
1941 #define ICE_AQC_I2C_ADDR_7BIT_MASK	0x7F
1942 #define ICE_AQC_I2C_ADDR_10BIT_MASK	0x3FF
1943 	u8 i2c_data[4]; /* Used only by write command, reserved in read. */
1944 };
1945 
1946 /* Read I2C Response (direct, 0x06E2) */
1947 struct ice_aqc_read_i2c_resp {
1948 	u8 i2c_data[16];
1949 };
1950 
1951 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */
1952 struct ice_aqc_mdio {
1953 	struct ice_aqc_link_topo_addr topo_addr;
1954 	u8 mdio_device_addr;
1955 #define ICE_AQC_MDIO_DEV_S	0
1956 #define ICE_AQC_MDIO_DEV_M	(0x1F << ICE_AQC_MDIO_DEV_S)
1957 #define ICE_AQC_MDIO_CLAUSE_22	BIT(5)
1958 #define ICE_AQC_MDIO_CLAUSE_45	BIT(6)
1959 	u8 mdio_bus_address;
1960 #define ICE_AQC_MDIO_BUS_ADDR_S 0
1961 #define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S)
1962 	__le16 offset;
1963 	__le16 data; /* Input in write cmd, output in read cmd. */
1964 	u8 rsvd1[4];
1965 };
1966 
1967 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */
1968 struct ice_aqc_gpio_by_func {
1969 	struct ice_aqc_link_topo_addr topo_addr;
1970 	u8 io_func_num;
1971 #define ICE_AQC_GPIO_FUNC_S	0
1972 #define ICE_AQC_GPIO_FUNC_M	(0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S)
1973 	u8 io_value; /* Input in write cmd, output in read cmd. */
1974 #define ICE_AQC_GPIO_ON		BIT(0)
1975 #define ICE_AQC_GPIO_OFF	0
1976 	u8 rsvd[8];
1977 };
1978 
1979 /* Set LED (direct, 0x06E8) */
1980 struct ice_aqc_set_led {
1981 	struct ice_aqc_link_topo_addr topo_addr;
1982 	u8 color_and_blink;
1983 #define ICE_AQC_LED_COLOR_S		0
1984 #define ICE_AQC_LED_COLOR_M		(0x7 << ICE_AQC_LED_COLOR_S)
1985 #define ICE_AQC_LED_COLOR_SKIP		0
1986 #define ICE_AQC_LED_COLOR_RED		1
1987 #define ICE_AQC_LED_COLOR_ORANGE	2
1988 #define ICE_AQC_LED_COLOR_YELLOW	3
1989 #define ICE_AQC_LED_COLOR_GREEN		4
1990 #define ICE_AQC_LED_COLOR_BLUE		5
1991 #define ICE_AQC_LED_COLOR_PURPLE	6
1992 #define ICE_AQC_LED_BLINK_S		3
1993 #define ICE_AQC_LED_BLINK_M		(0x7 << ICE_AQC_LED_BLINK_S)
1994 #define ICE_AQC_LED_BLINK_NONE		0
1995 #define ICE_AQC_LED_BLINK_SLOW		1
1996 #define ICE_AQC_LED_BLINK_SLOW_MAC	2
1997 #define ICE_AQC_LED_BLINK_SLOW_FLTR	3
1998 #define ICE_AQC_LED_BLINK_FAST		5
1999 #define ICE_AQC_LED_BLINK_FAST_MAC	6
2000 #define ICE_AQC_LED_BLINK_FAST_FLTR	7
2001 	u8 rsvd[9];
2002 };
2003 
2004 /* Set Port Identification LED (direct, 0x06E9) */
2005 struct ice_aqc_set_port_id_led {
2006 	u8 lport_num;
2007 	u8 lport_num_valid;
2008 #define ICE_AQC_PORT_ID_PORT_NUM_VALID	BIT(0)
2009 	u8 ident_mode;
2010 #define ICE_AQC_PORT_IDENT_LED_BLINK	BIT(0)
2011 #define ICE_AQC_PORT_IDENT_LED_ORIG	0
2012 	u8 rsvd[13];
2013 };
2014 
2015 /* Get Port Options (indirect, 0x06EA) */
2016 struct ice_aqc_get_port_options {
2017 	u8 lport_num;
2018 	u8 lport_num_valid;
2019 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID	BIT(0)
2020 	u8 port_options_count;
2021 #define ICE_AQC_PORT_OPT_COUNT_S	0
2022 #define ICE_AQC_PORT_OPT_COUNT_M	(0xF << ICE_AQC_PORT_OPT_COUNT_S)
2023 #define ICE_AQC_PORT_OPT_MAX		16
2024 	u8 innermost_phy_index;
2025 	u8 port_options;
2026 #define ICE_AQC_PORT_OPT_ACTIVE_S	0
2027 #define ICE_AQC_PORT_OPT_ACTIVE_M	(0xF << ICE_AQC_PORT_OPT_ACTIVE_S)
2028 #define ICE_AQC_PORT_OPT_FORCED		BIT(6)
2029 #define ICE_AQC_PORT_OPT_VALID		BIT(7)
2030 	u8 pending_port_option_status;
2031 #define ICE_AQC_PENDING_PORT_OPT_IDX_S	0
2032 #define ICE_AQC_PENDING_PORT_OPT_IDX_M	(0xF << ICE_AQC_PENDING_PORT_OPT_IDX_S)
2033 #define ICE_AQC_PENDING_PORT_OPT_VALID	BIT(7)
2034 	u8 rsvd[2];
2035 	__le32 addr_high;
2036 	__le32 addr_low;
2037 };
2038 
2039 struct ice_aqc_get_port_options_elem {
2040 	u8 pmd;
2041 #define ICE_AQC_PORT_INV_PORT_OPT	4
2042 #define ICE_AQC_PORT_OPT_PMD_COUNT_S	0
2043 #define ICE_AQC_PORT_OPT_PMD_COUNT_M	(0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S)
2044 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S	4
2045 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M	(0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S)
2046 	u8 max_lane_speed;
2047 #define ICE_AQC_PORT_OPT_MAX_LANE_S	0
2048 #define ICE_AQC_PORT_OPT_MAX_LANE_M	(0xF << ICE_AQC_PORT_OPT_MAX_LANE_S)
2049 #define ICE_AQC_PORT_OPT_MAX_LANE_100M	0
2050 #define ICE_AQC_PORT_OPT_MAX_LANE_1G	1
2051 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M	2
2052 #define ICE_AQC_PORT_OPT_MAX_LANE_5G	3
2053 #define ICE_AQC_PORT_OPT_MAX_LANE_10G	4
2054 #define ICE_AQC_PORT_OPT_MAX_LANE_25G	5
2055 #define ICE_AQC_PORT_OPT_MAX_LANE_50G	6
2056 #define ICE_AQC_PORT_OPT_MAX_LANE_100G	7
2057 	u8 global_scid[2];
2058 	u8 phy_scid[2];
2059 	u8 pf2port_cid[2];
2060 };
2061 
2062 /* Set Port Option (direct, 0x06EB) */
2063 struct ice_aqc_set_port_option {
2064 	u8 lport_num;
2065 	u8 lport_num_valid;
2066 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID	BIT(0)
2067 	u8 selected_port_option;
2068 	u8 rsvd[13];
2069 };
2070 
2071 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */
2072 struct ice_aqc_gpio {
2073 	__le16 gpio_ctrl_handle;
2074 #define ICE_AQC_GPIO_HANDLE_S	0
2075 #define ICE_AQC_GPIO_HANDLE_M	(0x3FF << ICE_AQC_GPIO_HANDLE_S)
2076 	u8 gpio_num;
2077 	u8 gpio_val;
2078 	u8 rsvd[12];
2079 };
2080 
2081 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
2082 struct ice_aqc_sff_eeprom {
2083 	u8 lport_num;
2084 	u8 lport_num_valid;
2085 #define ICE_AQC_SFF_PORT_NUM_VALID	BIT(0)
2086 	__le16 i2c_bus_addr;
2087 #define ICE_AQC_SFF_I2CBUS_7BIT_M	0x7F
2088 #define ICE_AQC_SFF_I2CBUS_10BIT_M	0x3FF
2089 #define ICE_AQC_SFF_I2CBUS_TYPE_M	BIT(10)
2090 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT	0
2091 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT	ICE_AQC_SFF_I2CBUS_TYPE_M
2092 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S	11
2093 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M	(0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
2094 #define ICE_AQC_SFF_NO_PAGE_CHANGE	0
2095 #define ICE_AQC_SFF_SET_23_ON_MISMATCH	1
2096 #define ICE_AQC_SFF_SET_22_ON_MISMATCH	2
2097 #define ICE_AQC_SFF_IS_WRITE		BIT(15)
2098 	__le16 i2c_mem_addr;
2099 	__le16 eeprom_page;
2100 #define  ICE_AQC_SFF_EEPROM_BANK_S 0
2101 #define  ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
2102 #define  ICE_AQC_SFF_EEPROM_PAGE_S 8
2103 #define  ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
2104 	__le32 addr_high;
2105 	__le32 addr_low;
2106 };
2107 
2108 /* SW Set GPIO command (indirect 0x6EF)
2109  * SW Get GPIO command (indirect 0x6F0)
2110  */
2111 struct ice_aqc_sw_gpio {
2112 	__le16 gpio_ctrl_handle;
2113 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S	0
2114 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M	(0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S)
2115 	u8 gpio_num;
2116 #define ICE_AQC_SW_GPIO_NUMBER_S	0
2117 #define ICE_AQC_SW_GPIO_NUMBER_M	(0x1F << ICE_AQC_SW_GPIO_NUMBER_S)
2118 	u8 gpio_params;
2119 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION    BIT(1)
2120 #define ICE_AQC_SW_GPIO_PARAMS_VALUE        BIT(0)
2121 	u8 rsvd[12];
2122 };
2123 
2124 /* Program Topology Device NVM (direct, 0x06F2) */
2125 struct ice_aqc_prog_topo_dev_nvm {
2126 	struct ice_aqc_link_topo_params topo_params;
2127 	u8 rsvd[12];
2128 };
2129 
2130 /* Read Topology Device NVM (direct, 0x06F3) */
2131 struct ice_aqc_read_topo_dev_nvm {
2132 	struct ice_aqc_link_topo_params topo_params;
2133 	__le32 start_address;
2134 #define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8
2135 	u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE];
2136 };
2137 
2138 /* NVM Read command (indirect 0x0701)
2139  * NVM Erase commands (direct 0x0702)
2140  * NVM Write commands (indirect 0x0703)
2141  * NVM Write Activate commands (direct 0x0707)
2142  * NVM Shadow RAM Dump commands (direct 0x0707)
2143  */
2144 struct ice_aqc_nvm {
2145 #define ICE_AQC_NVM_MAX_OFFSET		0xFFFFFF
2146 	__le16 offset_low;
2147 	u8 offset_high; /* For Write Activate offset_high is used as flags2 */
2148 	u8 cmd_flags;
2149 #define ICE_AQC_NVM_LAST_CMD		BIT(0)
2150 #define ICE_AQC_NVM_PCIR_REQ		BIT(0)	/* Used by NVM Write reply */
2151 #define ICE_AQC_NVM_PRESERVATION_S	1 /* Used by NVM Write Activate only */
2152 #define ICE_AQC_NVM_PRESERVATION_M	(3 << ICE_AQC_NVM_PRESERVATION_S)
2153 #define ICE_AQC_NVM_NO_PRESERVATION	(0 << ICE_AQC_NVM_PRESERVATION_S)
2154 #define ICE_AQC_NVM_PRESERVE_ALL	BIT(1)
2155 #define ICE_AQC_NVM_FACTORY_DEFAULT	(2 << ICE_AQC_NVM_PRESERVATION_S)
2156 #define ICE_AQC_NVM_PRESERVE_SELECTED	(3 << ICE_AQC_NVM_PRESERVATION_S)
2157 #define ICE_AQC_NVM_ACTIV_SEL_NVM	BIT(3) /* Write Activate/SR Dump only */
2158 #define ICE_AQC_NVM_ACTIV_SEL_OROM	BIT(4)
2159 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST	BIT(5)
2160 #define ICE_AQC_NVM_SPECIAL_UPDATE	BIT(6)
2161 #define ICE_AQC_NVM_REVERT_LAST_ACTIV	BIT(6) /* Write Activate only */
2162 #define ICE_AQC_NVM_ACTIV_SEL_MASK	MAKEMASK(0x7, 3)
2163 #define ICE_AQC_NVM_FLASH_ONLY		BIT(7)
2164 #define ICE_AQC_NVM_RESET_LVL_M		MAKEMASK(0x3, 0) /* Write reply only */
2165 #define ICE_AQC_NVM_POR_FLAG		0
2166 #define ICE_AQC_NVM_PERST_FLAG		1
2167 #define ICE_AQC_NVM_EMPR_FLAG		2
2168 #define ICE_AQC_NVM_EMPR_ENA		BIT(0) /* Write Activate reply only */
2169 	/* For Write Activate, several flags are sent as part of a separate
2170 	 * flags2 field using a separate byte. For simplicity of the software
2171 	 * interface, we pass the flags as a 16 bit value so these flags are
2172 	 * all offset by 8 bits
2173 	 */
2174 #define ICE_AQC_NVM_ACTIV_REQ_EMPR	BIT(8) /* NVM Write Activate only */
2175 	__le16 module_typeid;
2176 	__le16 length;
2177 #define ICE_AQC_NVM_ERASE_LEN	0xFFFF
2178 	__le32 addr_high;
2179 	__le32 addr_low;
2180 };
2181 
2182 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */
2183 #define ICE_AQC_NVM_SECTOR_UNIT			4096 /* In Bytes */
2184 #define ICE_AQC_NVM_WORD_UNIT			2 /* In Bytes */
2185 
2186 #define ICE_AQC_NVM_START_POINT			0
2187 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET		0x90
2188 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN		2 /* In Bytes */
2189 #define ICE_AQC_NVM_EMP_SR_PTR_M		MAKEMASK(0x7FFF, 0)
2190 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S		15
2191 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M		BIT(15)
2192 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR	1
2193 
2194 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET		0x46
2195 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN		2 /* In Bytes */
2196 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN		2 /* In Bytes */
2197 
2198 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID	0x129
2199 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET	2 /* In Bytes */
2200 #define ICE_AQC_NVM_LLDP_STATUS_M		MAKEMASK(0xF, 0)
2201 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN		4 /* In Bits */
2202 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN		4 /* In Bytes */
2203 
2204 #define ICE_AQC_NVM_MINSREV_MOD_ID		0x130
2205 #define ICE_AQC_NVM_TX_TOPO_MOD_ID		0x14B
2206 #define ICE_AQC_NVM_CMPO_MOD_ID			0x153
2207 
2208 /* Cage Max Power override NVM module */
2209 struct ice_aqc_nvm_cmpo {
2210 	__le16 length;
2211 #define ICE_AQC_NVM_CMPO_ENABLE	BIT(8)
2212 	__le16 cages_cfg[8];
2213 };
2214 
2215 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the
2216  * type field is excluded from the section when reading and writing from
2217  * a module using the module_typeid field with these AQ commands.
2218  */
2219 struct ice_aqc_nvm_minsrev {
2220 	__le16 length;
2221 	__le16 validity;
2222 #define ICE_AQC_NVM_MINSREV_NVM_VALID		BIT(0)
2223 #define ICE_AQC_NVM_MINSREV_OROM_VALID		BIT(1)
2224 	__le16 nvm_minsrev_l;
2225 	__le16 nvm_minsrev_h;
2226 	__le16 orom_minsrev_l;
2227 	__le16 orom_minsrev_h;
2228 };
2229 
2230 struct ice_aqc_nvm_tx_topo_user_sel {
2231 	__le16 length;
2232 	u8 data;
2233 #define ICE_AQC_NVM_TX_TOPO_USER_SEL		BIT(4)
2234 	u8 reserved;
2235 };
2236 
2237 /* Used for 0x0704 as well as for 0x0705 commands */
2238 struct ice_aqc_nvm_cfg {
2239 	u8	cmd_flags;
2240 #define ICE_AQC_ANVM_MULTIPLE_ELEMS	BIT(0)
2241 #define ICE_AQC_ANVM_IMMEDIATE_FIELD	BIT(1)
2242 #define ICE_AQC_ANVM_NEW_CFG		BIT(2)
2243 	u8	reserved;
2244 	__le16 count;
2245 	__le16 id;
2246 	u8 reserved1[2];
2247 	__le32 addr_high;
2248 	__le32 addr_low;
2249 };
2250 
2251 struct ice_aqc_nvm_cfg_data {
2252 	__le16 field_id;
2253 	__le16 field_options;
2254 	__le16 field_value;
2255 };
2256 
2257 /* NVM Checksum Command (direct, 0x0706) */
2258 struct ice_aqc_nvm_checksum {
2259 	u8 flags;
2260 #define ICE_AQC_NVM_CHECKSUM_VERIFY	BIT(0)
2261 #define ICE_AQC_NVM_CHECKSUM_RECALC	BIT(1)
2262 	u8 rsvd;
2263 	__le16 checksum; /* Used only by response */
2264 #define ICE_AQC_NVM_CHECKSUM_CORRECT	0xBABA
2265 	u8 rsvd2[12];
2266 };
2267 
2268 /*
2269  * Send to PF command (indirect 0x0801) ID is only used by PF
2270  *
2271  * Send to VF command (indirect 0x0802) ID is only used by PF
2272  *
2273  */
2274 struct ice_aqc_pf_vf_msg {
2275 	__le32 id;
2276 	u32 reserved;
2277 	__le32 addr_high;
2278 	__le32 addr_low;
2279 };
2280 
2281 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */
2282 struct ice_aqc_read_write_alt_direct {
2283 	__le32 dword0_addr;
2284 	__le32 dword0_value;
2285 	__le32 dword1_addr;
2286 	__le32 dword1_value;
2287 };
2288 
2289 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */
2290 struct ice_aqc_read_write_alt_indirect {
2291 	__le32 base_dword_addr;
2292 	__le32 num_dwords;
2293 	__le32 addr_high;
2294 	__le32 addr_low;
2295 };
2296 
2297 /* Done Alternate Write (direct 0x0904) */
2298 struct ice_aqc_done_alt_write {
2299 	u8 flags;
2300 #define ICE_AQC_CMD_UEFI_BIOS_MODE	BIT(0)
2301 #define ICE_AQC_RESP_RESET_NEEDED	BIT(1)
2302 	u8 reserved[15];
2303 };
2304 
2305 /* Clear Port Alternate Write (direct 0x0906) */
2306 struct ice_aqc_clear_port_alt_write {
2307 	u8 reserved[16];
2308 };
2309 
2310 /* Get LLDP MIB (indirect 0x0A00)
2311  * Note: This is also used by the LLDP MIB Change Event (0x0A01)
2312  * as the format is the same.
2313  */
2314 struct ice_aqc_lldp_get_mib {
2315 	u8 type;
2316 #define ICE_AQ_LLDP_MIB_TYPE_S			0
2317 #define ICE_AQ_LLDP_MIB_TYPE_M			(0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
2318 #define ICE_AQ_LLDP_MIB_LOCAL			0
2319 #define ICE_AQ_LLDP_MIB_REMOTE			1
2320 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE	2
2321 #define ICE_AQ_LLDP_BRID_TYPE_S			2
2322 #define ICE_AQ_LLDP_BRID_TYPE_M			(0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
2323 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID	0
2324 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR		1
2325 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
2326 #define ICE_AQ_LLDP_TX_S			0x4
2327 #define ICE_AQ_LLDP_TX_M			(0x03 << ICE_AQ_LLDP_TX_S)
2328 #define ICE_AQ_LLDP_TX_ACTIVE			0
2329 #define ICE_AQ_LLDP_TX_SUSPENDED		1
2330 #define ICE_AQ_LLDP_TX_FLUSHED			3
2331 /* DCBX mode */
2332 #define ICE_AQ_LLDP_DCBX_S			6
2333 #define ICE_AQ_LLDP_DCBX_M			(0x3 << ICE_AQ_LLDP_DCBX_S)
2334 #define ICE_AQ_LLDP_DCBX_NA			0
2335 #define ICE_AQ_LLDP_DCBX_CEE			1
2336 #define ICE_AQ_LLDP_DCBX_IEEE			2
2337 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
2338  * and in the LLDP MIB Change Event (0x0A01). They are valid for the
2339  * Get LLDP MIB (0x0A00) response only.
2340  */
2341 	u8 state;
2342 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_S		0
2343 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M		\
2344 				(0x1 << ICE_AQ_LLDP_MIB_CHANGE_STATE_S)
2345 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED		0
2346 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING		1
2347 	__le16 local_len;
2348 	__le16 remote_len;
2349 	u8 reserved[2];
2350 	__le32 addr_high;
2351 	__le32 addr_low;
2352 };
2353 
2354 /* Configure LLDP MIB Change Event (direct 0x0A01) */
2355 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
2356 struct ice_aqc_lldp_set_mib_change {
2357 	u8 command;
2358 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE		0x0
2359 #define ICE_AQ_LLDP_MIB_UPDATE_DIS		0x1
2360 #define ICE_AQ_LLDP_MIB_PENDING_S		1
2361 #define ICE_AQ_LLDP_MIB_PENDING_M		\
2362 				(0x1 << ICE_AQ_LLDP_MIB_PENDING_S)
2363 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE		0
2364 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE		1
2365 	u8 reserved[15];
2366 };
2367 
2368 /* Add LLDP TLV (indirect 0x0A02)
2369  * Delete LLDP TLV (indirect 0x0A04)
2370  */
2371 struct ice_aqc_lldp_add_delete_tlv {
2372 	u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2373 	u8 reserved1[1];
2374 	__le16 len;
2375 	u8 reserved2[4];
2376 	__le32 addr_high;
2377 	__le32 addr_low;
2378 };
2379 
2380 /* Update LLDP TLV (indirect 0x0A03) */
2381 struct ice_aqc_lldp_update_tlv {
2382 	u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2383 	u8 reserved;
2384 	__le16 old_len;
2385 	__le16 new_offset;
2386 	__le16 new_len;
2387 	__le32 addr_high;
2388 	__le32 addr_low;
2389 };
2390 
2391 /* Stop LLDP (direct 0x0A05) */
2392 struct ice_aqc_lldp_stop {
2393 	u8 command;
2394 #define ICE_AQ_LLDP_AGENT_STATE_MASK	BIT(0)
2395 #define ICE_AQ_LLDP_AGENT_STOP		0x0
2396 #define ICE_AQ_LLDP_AGENT_SHUTDOWN	ICE_AQ_LLDP_AGENT_STATE_MASK
2397 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS	BIT(1)
2398 	u8 reserved[15];
2399 };
2400 
2401 /* Start LLDP (direct 0x0A06) */
2402 struct ice_aqc_lldp_start {
2403 	u8 command;
2404 #define ICE_AQ_LLDP_AGENT_START		BIT(0)
2405 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA	BIT(1)
2406 	u8 reserved[15];
2407 };
2408 
2409 /* Get CEE DCBX Oper Config (0x0A07)
2410  * The command uses the generic descriptor struct and
2411  * returns the struct below as an indirect response.
2412  */
2413 struct ice_aqc_get_cee_dcb_cfg_resp {
2414 	u8 oper_num_tc;
2415 	u8 oper_prio_tc[4];
2416 	u8 oper_tc_bw[8];
2417 	u8 oper_pfc_en;
2418 	__le16 oper_app_prio;
2419 #define ICE_AQC_CEE_APP_FCOE_S		0
2420 #define ICE_AQC_CEE_APP_FCOE_M		(0x7 << ICE_AQC_CEE_APP_FCOE_S)
2421 #define ICE_AQC_CEE_APP_ISCSI_S		3
2422 #define ICE_AQC_CEE_APP_ISCSI_M		(0x7 << ICE_AQC_CEE_APP_ISCSI_S)
2423 #define ICE_AQC_CEE_APP_FIP_S		8
2424 #define ICE_AQC_CEE_APP_FIP_M		(0x7 << ICE_AQC_CEE_APP_FIP_S)
2425 	__le32 tlv_status;
2426 #define ICE_AQC_CEE_PG_STATUS_S		0
2427 #define ICE_AQC_CEE_PG_STATUS_M		(0x7 << ICE_AQC_CEE_PG_STATUS_S)
2428 #define ICE_AQC_CEE_PFC_STATUS_S	3
2429 #define ICE_AQC_CEE_PFC_STATUS_M	(0x7 << ICE_AQC_CEE_PFC_STATUS_S)
2430 #define ICE_AQC_CEE_FCOE_STATUS_S	8
2431 #define ICE_AQC_CEE_FCOE_STATUS_M	(0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
2432 #define ICE_AQC_CEE_ISCSI_STATUS_S	11
2433 #define ICE_AQC_CEE_ISCSI_STATUS_M	(0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
2434 #define ICE_AQC_CEE_FIP_STATUS_S	16
2435 #define ICE_AQC_CEE_FIP_STATUS_M	(0x7 << ICE_AQC_CEE_FIP_STATUS_S)
2436 	u8 reserved[12];
2437 };
2438 
2439 /* Set Local LLDP MIB (indirect 0x0A08)
2440  * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
2441  */
2442 struct ice_aqc_lldp_set_local_mib {
2443 	u8 type;
2444 #define SET_LOCAL_MIB_TYPE_DCBX_M		BIT(0)
2445 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB		0
2446 #define SET_LOCAL_MIB_TYPE_CEE_M		BIT(1)
2447 #define SET_LOCAL_MIB_TYPE_CEE_WILLING		0
2448 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING	SET_LOCAL_MIB_TYPE_CEE_M
2449 	u8 reserved0;
2450 	__le16 length;
2451 	u8 reserved1[4];
2452 	__le32 addr_high;
2453 	__le32 addr_low;
2454 };
2455 
2456 struct ice_aqc_lldp_set_local_mib_resp {
2457 	u8 status;
2458 #define SET_LOCAL_MIB_RESP_EVENT_M		BIT(0)
2459 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT	0
2460 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT	SET_LOCAL_MIB_RESP_EVENT_M
2461 	u8 reserved[15];
2462 };
2463 
2464 /* Stop/Start LLDP Agent (direct 0x0A09)
2465  * Used for stopping/starting specific LLDP agent. e.g. DCBX.
2466  * The same structure is used for the response, with the command field
2467  * being used as the status field.
2468  */
2469 struct ice_aqc_lldp_stop_start_specific_agent {
2470 	u8 command;
2471 #define ICE_AQC_START_STOP_AGENT_M		BIT(0)
2472 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX	0
2473 #define ICE_AQC_START_STOP_AGENT_START_DCBX	ICE_AQC_START_STOP_AGENT_M
2474 	u8 reserved[15];
2475 };
2476 
2477 /* LLDP Filter Control (direct 0x0A0A) */
2478 struct ice_aqc_lldp_filter_ctrl {
2479 	u8 cmd_flags;
2480 #define ICE_AQC_LLDP_FILTER_ACTION_M		MAKEMASK(3, 0)
2481 #define ICE_AQC_LLDP_FILTER_ACTION_ADD		0x0
2482 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE	0x1
2483 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE	0x2
2484 	u8 reserved1;
2485 	__le16 vsi_num;
2486 	u8 reserved2[12];
2487 };
2488 
2489 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
2490 struct ice_aqc_get_set_rss_key {
2491 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID	BIT(15)
2492 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S	0
2493 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M	(0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
2494 	__le16 vsi_id;
2495 	u8 reserved[6];
2496 	__le32 addr_high;
2497 	__le32 addr_low;
2498 };
2499 
2500 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE	0x28
2501 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE	0xC
2502 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
2503 				(ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
2504 				 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
2505 
2506 /**
2507  * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer
2508  * @standard_rss_key: 40 most significant bytes of hash key
2509  * @extended_hash_key: 12 least significant bytes of hash key
2510  *
2511  * Set/Get 40 byte hash key using standard_rss_key field, and set
2512  * extended_hash_key field to zero. Set/Get 52 byte hash key using
2513  * standard_rss_key field for 40 most significant bytes and the
2514  * extended_hash_key field for the 12 least significant bytes of hash key.
2515  */
2516 struct ice_aqc_get_set_rss_keys {
2517 	u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
2518 	u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
2519 };
2520 
2521 enum ice_lut_type {
2522 	ICE_LUT_VSI = 0,
2523 	ICE_LUT_PF = 1,
2524 	ICE_LUT_GLOBAL = 2,
2525 	ICE_LUT_TYPE_MASK = 3,
2526 	ICE_LUT_PF_SMALL = 5, /* yields ICE_LUT_PF when &= ICE_LUT_TYPE_MASK */
2527 };
2528 
2529 enum ice_lut_size {
2530 	ICE_LUT_VSI_SIZE = 64,
2531 	ICE_LUT_PF_SMALL_SIZE = 128,
2532 	ICE_LUT_GLOBAL_SIZE = 512,
2533 	ICE_LUT_PF_SIZE = 2048,
2534 };
2535 
2536 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
2537 struct ice_aqc_get_set_rss_lut {
2538 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID	BIT(15)
2539 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S	0
2540 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M	(0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
2541 	__le16 vsi_id;
2542 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S	0
2543 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M	\
2544 	(ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
2545 
2546 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S	 2
2547 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M	 \
2548 	(ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
2549 
2550 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
2551 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG	 2
2552 
2553 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S	 4
2554 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M	 \
2555 				(0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
2556 
2557 	__le16 flags;
2558 	__le32 reserved;
2559 	__le32 addr_high;
2560 	__le32 addr_low;
2561 };
2562 
2563 /* Add Tx LAN Queues (indirect 0x0C30) */
2564 struct ice_aqc_add_txqs {
2565 	u8 num_qgrps;
2566 	u8 reserved[3];
2567 	__le32 reserved1;
2568 	__le32 addr_high;
2569 	__le32 addr_low;
2570 };
2571 
2572 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
2573  * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
2574  */
2575 struct ice_aqc_add_txqs_perq {
2576 	__le16 txq_id;
2577 	u8 rsvd[2];
2578 	__le32 q_teid;
2579 	u8 txq_ctx[22];
2580 	u8 rsvd2[2];
2581 	struct ice_aqc_txsched_elem info;
2582 };
2583 
2584 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
2585  * is an array of the following structs. Please note that the length of
2586  * each struct ice_aqc_add_tx_qgrp is variable due
2587  * to the variable number of queues in each group!
2588  */
2589 struct ice_aqc_add_tx_qgrp {
2590 	__le32 parent_teid;
2591 	u8 num_txqs;
2592 	u8 rsvd[3];
2593 	struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN];
2594 };
2595 
2596 /* Disable Tx LAN Queues (indirect 0x0C31) */
2597 struct ice_aqc_dis_txqs {
2598 	u8 cmd_type;
2599 #define ICE_AQC_Q_DIS_CMD_S		0
2600 #define ICE_AQC_Q_DIS_CMD_M		(0x3 << ICE_AQC_Q_DIS_CMD_S)
2601 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET	(0 << ICE_AQC_Q_DIS_CMD_S)
2602 #define ICE_AQC_Q_DIS_CMD_VM_RESET	BIT(ICE_AQC_Q_DIS_CMD_S)
2603 #define ICE_AQC_Q_DIS_CMD_VF_RESET	(2 << ICE_AQC_Q_DIS_CMD_S)
2604 #define ICE_AQC_Q_DIS_CMD_PF_RESET	(3 << ICE_AQC_Q_DIS_CMD_S)
2605 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL	BIT(2)
2606 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE	BIT(3)
2607 	u8 num_entries;
2608 	__le16 vmvf_and_timeout;
2609 #define ICE_AQC_Q_DIS_VMVF_NUM_S	0
2610 #define ICE_AQC_Q_DIS_VMVF_NUM_M	(0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
2611 #define ICE_AQC_Q_DIS_TIMEOUT_S		10
2612 #define ICE_AQC_Q_DIS_TIMEOUT_M		(0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
2613 	__le32 blocked_cgds;
2614 	__le32 addr_high;
2615 	__le32 addr_low;
2616 };
2617 
2618 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
2619  * contains the following structures, arrayed one after the
2620  * other.
2621  * Note: Since the q_id is 16 bits wide, if the
2622  * number of queues is even, then 2 bytes of alignment MUST be
2623  * added before the start of the next group, to allow correct
2624  * alignment of the parent_teid field.
2625  */
2626 #pragma pack(1)
2627 struct ice_aqc_dis_txq_item {
2628 	__le32 parent_teid;
2629 	u8 num_qs;
2630 	u8 rsvd;
2631 	/* The length of the q_id array varies according to num_qs */
2632 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S		15
2633 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q	\
2634 			(0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2635 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET	\
2636 			(1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
2637 	__le16 q_id[STRUCT_HACK_VAR_LEN];
2638 };
2639 #pragma pack()
2640 
2641 /* Tx LAN Queues Cleanup Event (0x0C31) */
2642 struct ice_aqc_txqs_cleanup {
2643 	__le16 caller_opc;
2644 	__le16 cmd_tag;
2645 	u8 reserved[12];
2646 };
2647 
2648 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */
2649 struct ice_aqc_move_txqs {
2650 	u8 cmd_type;
2651 #define ICE_AQC_Q_CMD_TYPE_S		0
2652 #define ICE_AQC_Q_CMD_TYPE_M		(0x3 << ICE_AQC_Q_CMD_TYPE_S)
2653 #define ICE_AQC_Q_CMD_TYPE_MOVE		1
2654 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE	2
2655 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC	3
2656 #define ICE_AQC_Q_CMD_SUBSEQ_CALL	BIT(2)
2657 #define ICE_AQC_Q_CMD_FLUSH_PIPE	BIT(3)
2658 	u8 num_qs;
2659 	u8 rsvd;
2660 	u8 timeout;
2661 #define ICE_AQC_Q_CMD_TIMEOUT_S		2
2662 #define ICE_AQC_Q_CMD_TIMEOUT_M		(0x3F << ICE_AQC_Q_CMD_TIMEOUT_S)
2663 	__le32 blocked_cgds;
2664 	__le32 addr_high;
2665 	__le32 addr_low;
2666 };
2667 
2668 /* Per-queue data buffer for the Move Tx LAN Queues command/response */
2669 struct ice_aqc_move_txqs_elem {
2670 	__le16 txq_id;
2671 	u8 q_cgd;
2672 	u8 rsvd;
2673 	__le32 q_teid;
2674 };
2675 
2676 /* Indirect data buffer for the Move Tx LAN Queues command/response */
2677 struct ice_aqc_move_txqs_data {
2678 	__le32 src_teid;
2679 	__le32 dest_teid;
2680 	struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN];
2681 };
2682 
2683 /* Add Tx RDMA Queue Set (indirect 0x0C33) */
2684 struct ice_aqc_add_rdma_qset {
2685 	u8 num_qset_grps;
2686 	u8 reserved[7];
2687 	__le32 addr_high;
2688 	__le32 addr_low;
2689 };
2690 
2691 /* This is the descriptor of each qset entry for the Add Tx RDMA Queue Set
2692  * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.
2693  */
2694 struct ice_aqc_add_tx_rdma_qset_entry {
2695 	__le16 tx_qset_id;
2696 	u8 rsvd[2];
2697 	__le32 qset_teid;
2698 	struct ice_aqc_txsched_elem info;
2699 };
2700 
2701 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)
2702  * is an array of the following structs. Please note that the length of
2703  * each struct ice_aqc_add_rdma_qset is variable due to the variable
2704  * number of queues in each group!
2705  */
2706 struct ice_aqc_add_rdma_qset_data {
2707 	__le32 parent_teid;
2708 	__le16 num_qsets;
2709 	u8 rsvd[2];
2710 	struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[STRUCT_HACK_VAR_LEN];
2711 };
2712 
2713 /* Move RDMA Queue Set (indirect 0x0C34) */
2714 struct ice_aqc_move_rdma_qset_cmd {
2715 	u8 num_rdma_qset;	/* Used by commands and response */
2716 #define ICE_AQC_PF_MODE_SAME_PF		0x0
2717 #define ICE_AQC_PF_MODE_GIVE_OWNERSHIP	0x1
2718 #define ICE_AQC_PF_MODE_KEEP_OWNERSHIP	0x2
2719 	u8 flags;
2720 	u8 reserved[6];
2721 	__le32 addr_high;
2722 	__le32 addr_low;
2723 };
2724 
2725 /* Buffer */
2726 struct ice_aqc_move_rdma_qset_buffer_desc {
2727 	__le16 tx_qset_id;
2728 	__le16 qset_teid;
2729 };
2730 
2731 struct ice_aqc_move_rdma_qset_buffer {
2732 	__le32 src_parent_teid;
2733 	__le32 dest_parent_teid;
2734 	struct ice_aqc_move_rdma_qset_buffer_desc descs[STRUCT_HACK_VAR_LEN];
2735 };
2736 
2737 /* Download Package (indirect 0x0C40) */
2738 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */
2739 struct ice_aqc_download_pkg {
2740 	u8 flags;
2741 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF	0x01
2742 	u8 reserved[3];
2743 	__le32 reserved1;
2744 	__le32 addr_high;
2745 	__le32 addr_low;
2746 };
2747 
2748 struct ice_aqc_download_pkg_resp {
2749 	__le32 error_offset;
2750 	__le32 error_info;
2751 	__le32 addr_high;
2752 	__le32 addr_low;
2753 };
2754 
2755 /* Get Package Info List (indirect 0x0C43) */
2756 struct ice_aqc_get_pkg_info_list {
2757 	__le32 reserved1;
2758 	__le32 reserved2;
2759 	__le32 addr_high;
2760 	__le32 addr_low;
2761 };
2762 
2763 /* Version format for packages */
2764 struct ice_pkg_ver {
2765 	u8 major;
2766 	u8 minor;
2767 	u8 update;
2768 	u8 draft;
2769 };
2770 
2771 #define ICE_PKG_NAME_SIZE	32
2772 #define ICE_SEG_ID_SIZE		28
2773 #define ICE_SEG_NAME_SIZE	28
2774 
2775 struct ice_aqc_get_pkg_info {
2776 	struct ice_pkg_ver ver;
2777 	char name[ICE_SEG_NAME_SIZE];
2778 	__le32 track_id;
2779 	u8 is_in_nvm;
2780 	u8 is_active;
2781 	u8 is_active_at_boot;
2782 	u8 is_modified;
2783 };
2784 
2785 /* Get Package Info List response buffer format (0x0C43) */
2786 struct ice_aqc_get_pkg_info_resp {
2787 	__le32 count;
2788 	struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN];
2789 };
2790 
2791 /* Driver Shared Parameters (direct, 0x0C90) */
2792 struct ice_aqc_driver_shared_params {
2793 	u8 set_or_get_op;
2794 #define ICE_AQC_DRIVER_PARAM_OP_MASK		BIT(0)
2795 #define ICE_AQC_DRIVER_PARAM_SET		((u8)0)
2796 #define ICE_AQC_DRIVER_PARAM_GET		((u8)1)
2797 	u8 param_indx;
2798 #define ICE_AQC_DRIVER_PARAM_MAX_IDX		15
2799 	u8 rsvd[2];
2800 	__le32 param_val;
2801 	__le32 addr_high;
2802 	__le32 addr_low;
2803 };
2804 
2805 /* Lan Queue Overflow Event (direct, 0x1001) */
2806 struct ice_aqc_event_lan_overflow {
2807 	__le32 prtdcb_ruptq;
2808 	__le32 qtx_ctl;
2809 	u8 reserved[8];
2810 };
2811 
2812 /* Debug Dump Internal Data (indirect 0xFF08) */
2813 struct ice_aqc_debug_dump_internals {
2814 	__le16 cluster_id; /* Expresses next cluster ID in response */
2815 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW			0
2816 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED		2
2817 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES		3
2818 /* EMP_DRAM only dumpable in device debug mode */
2819 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM		4
2820 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK		5
2821 /* AUX_REGS only dumpable in device debug mode */
2822 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS		6
2823 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB			7
2824 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P			8
2825 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG		9
2826 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE	21
2827 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_MNG_TRANSACTIONS	22
2828 	__le16 table_id; /* Used only for non-memory clusters */
2829 	__le32 idx; /* In table entries for tables, in bytes for memory */
2830 	__le32 addr_high;
2831 	__le32 addr_low;
2832 };
2833 
2834 enum ice_aqc_fw_logging_mod {
2835 	ICE_AQC_FW_LOG_ID_GENERAL = 0,
2836 	ICE_AQC_FW_LOG_ID_CTRL,
2837 	ICE_AQC_FW_LOG_ID_LINK,
2838 	ICE_AQC_FW_LOG_ID_LINK_TOPO,
2839 	ICE_AQC_FW_LOG_ID_DNL,
2840 	ICE_AQC_FW_LOG_ID_I2C,
2841 	ICE_AQC_FW_LOG_ID_SDP,
2842 	ICE_AQC_FW_LOG_ID_MDIO,
2843 	ICE_AQC_FW_LOG_ID_ADMINQ,
2844 	ICE_AQC_FW_LOG_ID_HDMA,
2845 	ICE_AQC_FW_LOG_ID_LLDP,
2846 	ICE_AQC_FW_LOG_ID_DCBX,
2847 	ICE_AQC_FW_LOG_ID_DCB,
2848 	ICE_AQC_FW_LOG_ID_XLR,
2849 	ICE_AQC_FW_LOG_ID_NVM,
2850 	ICE_AQC_FW_LOG_ID_AUTH,
2851 	ICE_AQC_FW_LOG_ID_VPD,
2852 	ICE_AQC_FW_LOG_ID_IOSF,
2853 	ICE_AQC_FW_LOG_ID_PARSER,
2854 	ICE_AQC_FW_LOG_ID_SW,
2855 	ICE_AQC_FW_LOG_ID_SCHEDULER,
2856 	ICE_AQC_FW_LOG_ID_TXQ,
2857 	ICE_AQC_FW_LOG_ID_RSVD,
2858 	ICE_AQC_FW_LOG_ID_POST,
2859 	ICE_AQC_FW_LOG_ID_WATCHDOG,
2860 	ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
2861 	ICE_AQC_FW_LOG_ID_MNG,
2862 	ICE_AQC_FW_LOG_ID_SYNCE,
2863 	ICE_AQC_FW_LOG_ID_HEALTH,
2864 	ICE_AQC_FW_LOG_ID_TSDRV,
2865 	ICE_AQC_FW_LOG_ID_PFREG,
2866 	ICE_AQC_FW_LOG_ID_MDLVER,
2867 	ICE_AQC_FW_LOG_ID_MAX,
2868 };
2869 
2870 /* Set Health Status (direct 0xFF20) */
2871 struct ice_aqc_set_health_status_config {
2872 	u8 event_source;
2873 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK	BIT(0)
2874 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK		BIT(1)
2875 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK		BIT(2)
2876 	u8 reserved[15];
2877 };
2878 
2879 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT		0x101
2880 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE			0x102
2881 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL			0x103
2882 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM			0x104
2883 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT			0x105
2884 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT		0x106
2885 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED		0x107
2886 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT		0x108
2887 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE	0x109
2888 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG		0x10B
2889 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS			0x10C
2890 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE		0x10D
2891 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED	0x10F
2892 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT		0x110
2893 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED	0x111
2894 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO			0x112
2895 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST			0x113
2896 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT			0x114
2897 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS		0x115
2898 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME			0x116
2899 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT			0x117
2900 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG			0x120
2901 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD			0x121
2902 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY			0x500
2903 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS			0x501
2904 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH			0x502
2905 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH			0x503
2906 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH			0x504
2907 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT			0x505
2908 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT			0x506
2909 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION		0x507
2910 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION		0x508
2911 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB			0x509
2912 #define ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT			0x50A
2913 #define ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET			0x50B
2914 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL			0x50C
2915 #define ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL		0x50D
2916 #define ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP			0x1000
2917 #define ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL			0x1001
2918 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ			0x1002
2919 
2920 /* Get Health Status codes (indirect 0xFF21) */
2921 struct ice_aqc_get_supported_health_status_codes {
2922 	__le16 health_code_count;
2923 	u8 reserved[6];
2924 	__le32 addr_high;
2925 	__le32 addr_low;
2926 };
2927 
2928 /* Get Health Status (indirect 0xFF22) */
2929 struct ice_aqc_get_health_status {
2930 	__le16 health_status_count;
2931 	u8 reserved[6];
2932 	__le32 addr_high;
2933 	__le32 addr_low;
2934 };
2935 
2936 /* Get Health Status event buffer entry, (0xFF22)
2937  * repeated per reported health status
2938  */
2939 struct ice_aqc_health_status_elem {
2940 	__le16 health_status_code;
2941 	__le16 event_source;
2942 #define ICE_AQC_HEALTH_STATUS_PF			(0x1)
2943 #define ICE_AQC_HEALTH_STATUS_PORT			(0x2)
2944 #define ICE_AQC_HEALTH_STATUS_GLOBAL			(0x3)
2945 	__le32 internal_data1;
2946 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA	(0xDEADBEEF)
2947 	__le32 internal_data2;
2948 };
2949 
2950 /* Clear Health Status (direct 0xFF23) */
2951 struct ice_aqc_clear_health_status {
2952 	__le32 reserved[4];
2953 };
2954 
2955 /* Set FW Logging configuration (indirect 0xFF30)
2956  * Register for FW Logging (indirect 0xFF31)
2957  * Query FW Logging (indirect 0xFF32)
2958  * FW Log Event (indirect 0xFF33)
2959  * Get FW Log (indirect 0xFF34)
2960  * Clear FW Log (indirect 0xFF35)
2961  */
2962 struct ice_aqc_fw_log {
2963 	u8 cmd_flags;
2964 #define ICE_AQC_FW_LOG_CONF_UART_EN	BIT(0)
2965 #define ICE_AQC_FW_LOG_CONF_AQ_EN	BIT(1)
2966 #define ICE_AQC_FW_LOG_QUERY_REGISTERED	BIT(2)
2967 #define ICE_AQC_FW_LOG_CONF_SET_VALID	BIT(3)
2968 #define ICE_AQC_FW_LOG_AQ_REGISTER	BIT(0)
2969 #define ICE_AQC_FW_LOG_AQ_QUERY		BIT(2)
2970 #define ICE_AQC_FW_LOG_PERSISTENT	BIT(0)
2971 	u8 rsp_flag;
2972 #define ICE_AQC_FW_LOG_MORE_DATA	BIT(1)
2973 	__le16 fw_rt_msb;
2974 	union {
2975 		struct {
2976 			__le32 fw_rt_lsb;
2977 		} sync;
2978 		struct {
2979 			__le16 log_resolution;
2980 #define ICE_AQC_FW_LOG_MIN_RESOLUTION		(1)
2981 #define ICE_AQC_FW_LOG_MAX_RESOLUTION		(128)
2982 			__le16 mdl_cnt;
2983 		} cfg;
2984 	} ops;
2985 	__le32 addr_high;
2986 	__le32 addr_low;
2987 };
2988 
2989 /* Response Buffer for:
2990  *    Set Firmware Logging Configuration (0xFF30)
2991  *    Query FW Logging (0xFF32)
2992  */
2993 struct ice_aqc_fw_log_cfg_resp {
2994 	__le16 module_identifier;
2995 	u8 log_level;
2996 	u8 rsvd0;
2997 };
2998 
2999 /**
3000  * struct ice_aq_desc - Admin Queue (AQ) descriptor
3001  * @flags: ICE_AQ_FLAG_* flags
3002  * @opcode: AQ command opcode
3003  * @datalen: length in bytes of indirect/external data buffer
3004  * @retval: return value from firmware
3005  * @cookie_high: opaque data high-half
3006  * @cookie_low: opaque data low-half
3007  * @params: command-specific parameters
3008  *
3009  * Descriptor format for commands the driver posts on the Admin Transmit Queue
3010  * (ATQ). The firmware writes back onto the command descriptor and returns
3011  * the result of the command. Asynchronous events that are not an immediate
3012  * result of the command are written to the Admin Receive Queue (ARQ) using
3013  * the same descriptor format. Descriptors are in little-endian notation with
3014  * 32-bit words.
3015  */
3016 struct ice_aq_desc {
3017 	__le16 flags;
3018 	__le16 opcode;
3019 	__le16 datalen;
3020 	__le16 retval;
3021 	__le32 cookie_high;
3022 	__le32 cookie_low;
3023 	union {
3024 		u8 raw[16];
3025 		struct ice_aqc_generic generic;
3026 		struct ice_aqc_get_ver get_ver;
3027 		struct ice_aqc_driver_ver driver_ver;
3028 		struct ice_aqc_q_shutdown q_shutdown;
3029 		struct ice_aqc_get_exp_err exp_err;
3030 		struct ice_aqc_req_res res_owner;
3031 		struct ice_aqc_manage_mac_read mac_read;
3032 		struct ice_aqc_manage_mac_write mac_write;
3033 		struct ice_aqc_clear_pxe clear_pxe;
3034 		struct ice_aqc_config_no_drop_policy no_drop;
3035 		struct ice_aqc_add_update_mir_rule add_update_rule;
3036 		struct ice_aqc_delete_mir_rule del_rule;
3037 		struct ice_aqc_list_caps get_cap;
3038 		struct ice_aqc_get_phy_caps get_phy;
3039 		struct ice_aqc_set_phy_cfg set_phy;
3040 		struct ice_aqc_restart_an restart_an;
3041 		struct ice_aqc_get_sensor_reading get_sensor_reading;
3042 		struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp;
3043 		struct ice_aqc_dnl_get_status get_status;
3044 		struct ice_aqc_dnl_run_command dnl_run;
3045 		struct ice_aqc_dnl_call_command dnl_call;
3046 		struct ice_aqc_dnl_read_write_command dnl_read_write;
3047 		struct ice_aqc_dnl_read_write_response dnl_read_write_resp;
3048 		struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk;
3049 		struct ice_aqc_dnl_read_log_command dnl_read_log;
3050 		struct ice_aqc_dnl_read_log_response dnl_read_log_resp;
3051 		struct ice_aqc_i2c read_write_i2c;
3052 		struct ice_aqc_read_i2c_resp read_i2c_resp;
3053 		struct ice_aqc_mdio read_write_mdio;
3054 		struct ice_aqc_gpio_by_func read_write_gpio_by_func;
3055 		struct ice_aqc_gpio read_write_gpio;
3056 		struct ice_aqc_sw_gpio sw_read_write_gpio;
3057 		struct ice_aqc_set_led set_led;
3058 		struct ice_aqc_mdio read_mdio;
3059 		struct ice_aqc_mdio write_mdio;
3060 		struct ice_aqc_sff_eeprom read_write_sff_param;
3061 		struct ice_aqc_set_port_id_led set_port_id_led;
3062 		struct ice_aqc_get_port_options get_port_options;
3063 		struct ice_aqc_set_port_option set_port_option;
3064 		struct ice_aqc_get_sw_cfg get_sw_conf;
3065 		struct ice_aqc_set_port_params set_port_params;
3066 		struct ice_aqc_sw_rules sw_rules;
3067 		struct ice_aqc_storm_cfg storm_conf;
3068 		struct ice_aqc_get_topo get_topo;
3069 		struct ice_aqc_sched_elem_cmd sched_elem_cmd;
3070 		struct ice_aqc_query_txsched_res query_sched_res;
3071 		struct ice_aqc_query_node_to_root query_node_to_root;
3072 		struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
3073 		struct ice_aqc_query_port_ets port_ets;
3074 		struct ice_aqc_rl_profile rl_profile;
3075 		struct ice_aqc_node_attr node_attr;
3076 		struct ice_aqc_nvm nvm;
3077 		struct ice_aqc_nvm_cfg nvm_cfg;
3078 		struct ice_aqc_nvm_checksum nvm_checksum;
3079 		struct ice_aqc_pf_vf_msg virt;
3080 		struct ice_aqc_read_write_alt_direct read_write_alt_direct;
3081 		struct ice_aqc_read_write_alt_indirect read_write_alt_indirect;
3082 		struct ice_aqc_done_alt_write done_alt_write;
3083 		struct ice_aqc_clear_port_alt_write clear_port_alt_write;
3084 		struct ice_aqc_pfc_ignore pfc_ignore;
3085 		struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
3086 		struct ice_aqc_set_dcb_params set_dcb_params;
3087 		struct ice_aqc_lldp_get_mib lldp_get_mib;
3088 		struct ice_aqc_lldp_set_mib_change lldp_set_event;
3089 		struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv;
3090 		struct ice_aqc_lldp_update_tlv lldp_update_tlv;
3091 		struct ice_aqc_lldp_stop lldp_stop;
3092 		struct ice_aqc_lldp_start lldp_start;
3093 		struct ice_aqc_lldp_set_local_mib lldp_set_mib;
3094 		struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
3095 		struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
3096 		struct ice_aqc_get_set_rss_lut get_set_rss_lut;
3097 		struct ice_aqc_get_set_rss_key get_set_rss_key;
3098 		struct ice_aqc_add_txqs add_txqs;
3099 		struct ice_aqc_dis_txqs dis_txqs;
3100 		struct ice_aqc_move_txqs move_txqs;
3101 		struct ice_aqc_add_rdma_qset add_rdma_qset;
3102 		struct ice_aqc_move_rdma_qset_cmd move_rdma_qset;
3103 		struct ice_aqc_txqs_cleanup txqs_cleanup;
3104 		struct ice_aqc_add_get_update_free_vsi vsi_cmd;
3105 		struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
3106 		struct ice_aqc_get_vsi_resp get_vsi_resp;
3107 		struct ice_aqc_download_pkg download_pkg;
3108 		struct ice_aqc_get_pkg_info_list get_pkg_info_list;
3109 		struct ice_aqc_driver_shared_params drv_shared_params;
3110 		struct ice_aqc_fw_log fw_log;
3111 		struct ice_aqc_debug_dump_internals debug_dump;
3112 		struct ice_aqc_set_mac_lb set_mac_lb;
3113 		struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
3114 		struct ice_aqc_get_res_alloc get_res;
3115 		struct ice_aqc_get_allocd_res_desc get_res_desc;
3116 		struct ice_aqc_set_mac_cfg set_mac_cfg;
3117 		struct ice_aqc_set_event_mask set_event_mask;
3118 		struct ice_aqc_get_link_status get_link_status;
3119 		struct ice_aqc_event_lan_overflow lan_overflow;
3120 		struct ice_aqc_get_link_topo get_link_topo;
3121 		struct ice_aqc_set_health_status_config
3122 			set_health_status_config;
3123 		struct ice_aqc_get_supported_health_status_codes
3124 			get_supported_health_status_codes;
3125 		struct ice_aqc_get_health_status get_health_status;
3126 		struct ice_aqc_clear_health_status clear_health_status;
3127 		struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm;
3128 		struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm;
3129 		struct ice_aqc_get_set_tx_topo get_set_tx_topo;
3130 	} params;
3131 };
3132 
3133 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
3134 #define ICE_AQ_LG_BUF	512
3135 
3136 /* Flags sub-structure
3137  * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
3138  * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
3139  */
3140 
3141 /* command flags and offsets */
3142 #define ICE_AQ_FLAG_DD_S	0
3143 #define ICE_AQ_FLAG_CMP_S	1
3144 #define ICE_AQ_FLAG_ERR_S	2
3145 #define ICE_AQ_FLAG_VFE_S	3
3146 #define ICE_AQ_FLAG_LB_S	9
3147 #define ICE_AQ_FLAG_RD_S	10
3148 #define ICE_AQ_FLAG_VFC_S	11
3149 #define ICE_AQ_FLAG_BUF_S	12
3150 #define ICE_AQ_FLAG_SI_S	13
3151 #define ICE_AQ_FLAG_EI_S	14
3152 #define ICE_AQ_FLAG_FE_S	15
3153 
3154 #define ICE_AQ_FLAG_DD		BIT(ICE_AQ_FLAG_DD_S)  /* 0x1    */
3155 #define ICE_AQ_FLAG_CMP		BIT(ICE_AQ_FLAG_CMP_S) /* 0x2    */
3156 #define ICE_AQ_FLAG_ERR		BIT(ICE_AQ_FLAG_ERR_S) /* 0x4    */
3157 #define ICE_AQ_FLAG_VFE		BIT(ICE_AQ_FLAG_VFE_S) /* 0x8    */
3158 #define ICE_AQ_FLAG_LB		BIT(ICE_AQ_FLAG_LB_S)  /* 0x200  */
3159 #define ICE_AQ_FLAG_RD		BIT(ICE_AQ_FLAG_RD_S)  /* 0x400  */
3160 #define ICE_AQ_FLAG_VFC		BIT(ICE_AQ_FLAG_VFC_S) /* 0x800  */
3161 #define ICE_AQ_FLAG_BUF		BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
3162 #define ICE_AQ_FLAG_SI		BIT(ICE_AQ_FLAG_SI_S)  /* 0x2000 */
3163 #define ICE_AQ_FLAG_EI		BIT(ICE_AQ_FLAG_EI_S)  /* 0x4000 */
3164 #define ICE_AQ_FLAG_FE		BIT(ICE_AQ_FLAG_FE_S)  /* 0x8000 */
3165 
3166 /* error codes */
3167 enum ice_aq_err {
3168 	ICE_AQ_RC_OK		= 0,  /* Success */
3169 	ICE_AQ_RC_EPERM		= 1,  /* Operation not permitted */
3170 	ICE_AQ_RC_ENOENT	= 2,  /* No such element */
3171 	ICE_AQ_RC_ESRCH		= 3,  /* Bad opcode */
3172 	ICE_AQ_RC_EINTR		= 4,  /* Operation interrupted */
3173 	ICE_AQ_RC_EIO		= 5,  /* I/O error */
3174 	ICE_AQ_RC_ENXIO		= 6,  /* No such resource */
3175 	ICE_AQ_RC_E2BIG		= 7,  /* Arg too long */
3176 	ICE_AQ_RC_EAGAIN	= 8,  /* Try again */
3177 	ICE_AQ_RC_ENOMEM	= 9,  /* Out of memory */
3178 	ICE_AQ_RC_EACCES	= 10, /* Permission denied */
3179 	ICE_AQ_RC_EFAULT	= 11, /* Bad address */
3180 	ICE_AQ_RC_EBUSY		= 12, /* Device or resource busy */
3181 	ICE_AQ_RC_EEXIST	= 13, /* Object already exists */
3182 	ICE_AQ_RC_EINVAL	= 14, /* Invalid argument */
3183 	ICE_AQ_RC_ENOTTY	= 15, /* Not a typewriter */
3184 	ICE_AQ_RC_ENOSPC	= 16, /* No space left or allocation failure */
3185 	ICE_AQ_RC_ENOSYS	= 17, /* Function not implemented */
3186 	ICE_AQ_RC_ERANGE	= 18, /* Parameter out of range */
3187 	ICE_AQ_RC_EFLUSHED	= 19, /* Cmd flushed due to prev cmd error */
3188 	ICE_AQ_RC_BAD_ADDR	= 20, /* Descriptor contains a bad pointer */
3189 	ICE_AQ_RC_EMODE		= 21, /* Op not allowed in current dev mode */
3190 	ICE_AQ_RC_EFBIG		= 22, /* File too big */
3191 	ICE_AQ_RC_ESBCOMP	= 23, /* SB-IOSF completion unsuccessful */
3192 	ICE_AQ_RC_ENOSEC	= 24, /* Missing security manifest */
3193 	ICE_AQ_RC_EBADSIG	= 25, /* Bad RSA signature */
3194 	ICE_AQ_RC_ESVN		= 26, /* SVN number prohibits this package */
3195 	ICE_AQ_RC_EBADMAN	= 27, /* Manifest hash mismatch */
3196 	ICE_AQ_RC_EBADBUF	= 28, /* Buffer hash mismatches manifest */
3197 	ICE_AQ_RC_EACCES_BMCU	= 29, /* BMC Update in progress */
3198 };
3199 
3200 /* Admin Queue command opcodes */
3201 enum ice_adminq_opc {
3202 	/* AQ commands */
3203 	ice_aqc_opc_get_ver				= 0x0001,
3204 	ice_aqc_opc_driver_ver				= 0x0002,
3205 	ice_aqc_opc_q_shutdown				= 0x0003,
3206 	ice_aqc_opc_get_exp_err				= 0x0005,
3207 
3208 	/* resource ownership */
3209 	ice_aqc_opc_req_res				= 0x0008,
3210 	ice_aqc_opc_release_res				= 0x0009,
3211 
3212 	/* device/function capabilities */
3213 	ice_aqc_opc_list_func_caps			= 0x000A,
3214 	ice_aqc_opc_list_dev_caps			= 0x000B,
3215 
3216 	/* manage MAC address */
3217 	ice_aqc_opc_manage_mac_read			= 0x0107,
3218 	ice_aqc_opc_manage_mac_write			= 0x0108,
3219 
3220 	/* PXE */
3221 	ice_aqc_opc_clear_pxe_mode			= 0x0110,
3222 
3223 	ice_aqc_opc_config_no_drop_policy		= 0x0112,
3224 
3225 	/* internal switch commands */
3226 	ice_aqc_opc_get_sw_cfg				= 0x0200,
3227 	ice_aqc_opc_set_port_params			= 0x0203,
3228 
3229 	/* Alloc/Free/Get Resources */
3230 	ice_aqc_opc_get_res_alloc			= 0x0204,
3231 	ice_aqc_opc_alloc_res				= 0x0208,
3232 	ice_aqc_opc_free_res				= 0x0209,
3233 	ice_aqc_opc_get_allocd_res_desc			= 0x020A,
3234 	ice_aqc_opc_set_vlan_mode_parameters		= 0x020C,
3235 	ice_aqc_opc_get_vlan_mode_parameters		= 0x020D,
3236 
3237 	/* VSI commands */
3238 	ice_aqc_opc_add_vsi				= 0x0210,
3239 	ice_aqc_opc_update_vsi				= 0x0211,
3240 	ice_aqc_opc_get_vsi_params			= 0x0212,
3241 	ice_aqc_opc_free_vsi				= 0x0213,
3242 
3243 	/* Mirroring rules - add/update, delete */
3244 	ice_aqc_opc_add_update_mir_rule			= 0x0260,
3245 	ice_aqc_opc_del_mir_rule			= 0x0261,
3246 
3247 	/* storm configuration */
3248 	ice_aqc_opc_set_storm_cfg			= 0x0280,
3249 	ice_aqc_opc_get_storm_cfg			= 0x0281,
3250 
3251 	/* switch rules population commands */
3252 	ice_aqc_opc_add_sw_rules			= 0x02A0,
3253 	ice_aqc_opc_update_sw_rules			= 0x02A1,
3254 	ice_aqc_opc_remove_sw_rules			= 0x02A2,
3255 	ice_aqc_opc_get_sw_rules			= 0x02A3,
3256 	ice_aqc_opc_clear_pf_cfg			= 0x02A4,
3257 
3258 	/* DCB commands */
3259 	ice_aqc_opc_pfc_ignore				= 0x0301,
3260 	ice_aqc_opc_query_pfc_mode			= 0x0302,
3261 	ice_aqc_opc_set_pfc_mode			= 0x0303,
3262 	ice_aqc_opc_set_dcb_params			= 0x0306,
3263 
3264 	/* transmit scheduler commands */
3265 	ice_aqc_opc_get_dflt_topo			= 0x0400,
3266 	ice_aqc_opc_add_sched_elems			= 0x0401,
3267 	ice_aqc_opc_cfg_sched_elems			= 0x0403,
3268 	ice_aqc_opc_get_sched_elems			= 0x0404,
3269 	ice_aqc_opc_move_sched_elems			= 0x0408,
3270 	ice_aqc_opc_suspend_sched_elems			= 0x0409,
3271 	ice_aqc_opc_resume_sched_elems			= 0x040A,
3272 	ice_aqc_opc_query_port_ets			= 0x040E,
3273 	ice_aqc_opc_delete_sched_elems			= 0x040F,
3274 	ice_aqc_opc_add_rl_profiles			= 0x0410,
3275 	ice_aqc_opc_query_rl_profiles			= 0x0411,
3276 	ice_aqc_opc_query_sched_res			= 0x0412,
3277 	ice_aqc_opc_query_node_to_root			= 0x0413,
3278 	ice_aqc_opc_cfg_l2_node_cgd			= 0x0414,
3279 	ice_aqc_opc_remove_rl_profiles			= 0x0415,
3280 	ice_aqc_opc_set_tx_topo				= 0x0417,
3281 	ice_aqc_opc_get_tx_topo				= 0x0418,
3282 	ice_aqc_opc_cfg_node_attr			= 0x0419,
3283 	ice_aqc_opc_query_node_attr			= 0x041A,
3284 
3285 	/* PHY commands */
3286 	ice_aqc_opc_get_phy_caps			= 0x0600,
3287 	ice_aqc_opc_set_phy_cfg				= 0x0601,
3288 	ice_aqc_opc_set_mac_cfg				= 0x0603,
3289 	ice_aqc_opc_restart_an				= 0x0605,
3290 	ice_aqc_opc_get_link_status			= 0x0607,
3291 	ice_aqc_opc_set_event_mask			= 0x0613,
3292 	ice_aqc_opc_set_mac_lb				= 0x0620,
3293 	ice_aqc_opc_get_sensor_reading			= 0x0632,
3294 	ice_aqc_opc_dnl_get_status			= 0x0680,
3295 	ice_aqc_opc_dnl_run				= 0x0681,
3296 	ice_aqc_opc_dnl_call				= 0x0682,
3297 	ice_aqc_opc_dnl_read_sto			= 0x0683,
3298 	ice_aqc_opc_dnl_write_sto			= 0x0684,
3299 	ice_aqc_opc_dnl_set_breakpoints			= 0x0686,
3300 	ice_aqc_opc_dnl_read_log			= 0x0687,
3301 	ice_aqc_opc_get_link_topo			= 0x06E0,
3302 	ice_aqc_opc_read_i2c				= 0x06E2,
3303 	ice_aqc_opc_write_i2c				= 0x06E3,
3304 	ice_aqc_opc_read_mdio				= 0x06E4,
3305 	ice_aqc_opc_write_mdio				= 0x06E5,
3306 	ice_aqc_opc_set_gpio_by_func			= 0x06E6,
3307 	ice_aqc_opc_get_gpio_by_func			= 0x06E7,
3308 	ice_aqc_opc_set_led				= 0x06E8,
3309 	ice_aqc_opc_set_port_id_led			= 0x06E9,
3310 	ice_aqc_opc_get_port_options			= 0x06EA,
3311 	ice_aqc_opc_set_port_option			= 0x06EB,
3312 	ice_aqc_opc_set_gpio				= 0x06EC,
3313 	ice_aqc_opc_get_gpio				= 0x06ED,
3314 	ice_aqc_opc_sff_eeprom				= 0x06EE,
3315 	ice_aqc_opc_sw_set_gpio				= 0x06EF,
3316 	ice_aqc_opc_sw_get_gpio				= 0x06F0,
3317 	ice_aqc_opc_prog_topo_dev_nvm			= 0x06F2,
3318 	ice_aqc_opc_read_topo_dev_nvm			= 0x06F3,
3319 
3320 	/* NVM commands */
3321 	ice_aqc_opc_nvm_read				= 0x0701,
3322 	ice_aqc_opc_nvm_erase				= 0x0702,
3323 	ice_aqc_opc_nvm_write				= 0x0703,
3324 	ice_aqc_opc_nvm_cfg_read			= 0x0704,
3325 	ice_aqc_opc_nvm_cfg_write			= 0x0705,
3326 	ice_aqc_opc_nvm_checksum			= 0x0706,
3327 	ice_aqc_opc_nvm_write_activate			= 0x0707,
3328 	ice_aqc_opc_nvm_sr_dump				= 0x0707,
3329 	ice_aqc_opc_nvm_save_factory_settings		= 0x0708,
3330 	ice_aqc_opc_nvm_update_empr			= 0x0709,
3331 	ice_aqc_opc_nvm_pkg_data			= 0x070A,
3332 	ice_aqc_opc_nvm_pass_component_tbl		= 0x070B,
3333 
3334 	/* PF/VF mailbox commands */
3335 	ice_mbx_opc_send_msg_to_pf			= 0x0801,
3336 	ice_mbx_opc_send_msg_to_vf			= 0x0802,
3337 	/* Alternate Structure Commands */
3338 	ice_aqc_opc_write_alt_direct			= 0x0900,
3339 	ice_aqc_opc_write_alt_indirect			= 0x0901,
3340 	ice_aqc_opc_read_alt_direct			= 0x0902,
3341 	ice_aqc_opc_read_alt_indirect			= 0x0903,
3342 	ice_aqc_opc_done_alt_write			= 0x0904,
3343 	ice_aqc_opc_clear_port_alt_write		= 0x0906,
3344 	/* LLDP commands */
3345 	ice_aqc_opc_lldp_get_mib			= 0x0A00,
3346 	ice_aqc_opc_lldp_set_mib_change			= 0x0A01,
3347 	ice_aqc_opc_lldp_add_tlv			= 0x0A02,
3348 	ice_aqc_opc_lldp_update_tlv			= 0x0A03,
3349 	ice_aqc_opc_lldp_delete_tlv			= 0x0A04,
3350 	ice_aqc_opc_lldp_stop				= 0x0A05,
3351 	ice_aqc_opc_lldp_start				= 0x0A06,
3352 	ice_aqc_opc_get_cee_dcb_cfg			= 0x0A07,
3353 	ice_aqc_opc_lldp_set_local_mib			= 0x0A08,
3354 	ice_aqc_opc_lldp_stop_start_specific_agent	= 0x0A09,
3355 	ice_aqc_opc_lldp_filter_ctrl			= 0x0A0A,
3356 	ice_execute_pending_lldp_mib			= 0x0A0B,
3357 
3358 	/* RSS commands */
3359 	ice_aqc_opc_set_rss_key				= 0x0B02,
3360 	ice_aqc_opc_set_rss_lut				= 0x0B03,
3361 	ice_aqc_opc_get_rss_key				= 0x0B04,
3362 	ice_aqc_opc_get_rss_lut				= 0x0B05,
3363 
3364 	/* Tx queue handling commands/events */
3365 	ice_aqc_opc_add_txqs				= 0x0C30,
3366 	ice_aqc_opc_dis_txqs				= 0x0C31,
3367 	ice_aqc_opc_txqs_cleanup			= 0x0C31,
3368 	ice_aqc_opc_move_recfg_txqs			= 0x0C32,
3369 	ice_aqc_opc_add_rdma_qset			= 0x0C33,
3370 	ice_aqc_opc_move_rdma_qset			= 0x0C34,
3371 
3372 	/* package commands */
3373 	ice_aqc_opc_download_pkg			= 0x0C40,
3374 	ice_aqc_opc_upload_section			= 0x0C41,
3375 	ice_aqc_opc_update_pkg				= 0x0C42,
3376 	ice_aqc_opc_get_pkg_info_list			= 0x0C43,
3377 
3378 	ice_aqc_opc_driver_shared_params		= 0x0C90,
3379 
3380 	/* Standalone Commands/Events */
3381 	ice_aqc_opc_event_lan_overflow			= 0x1001,
3382 
3383 	/* debug commands */
3384 	ice_aqc_opc_debug_dump_internals		= 0xFF08,
3385 
3386 	/* SystemDiagnostic commands */
3387 	ice_aqc_opc_set_health_status_config		= 0xFF20,
3388 	ice_aqc_opc_get_supported_health_status_codes	= 0xFF21,
3389 	ice_aqc_opc_get_health_status			= 0xFF22,
3390 	ice_aqc_opc_clear_health_status			= 0xFF23,
3391 
3392 	/* FW Logging Commands */
3393 	ice_aqc_opc_fw_logs_config			= 0xFF30,
3394 	ice_aqc_opc_fw_logs_register			= 0xFF31,
3395 	ice_aqc_opc_fw_logs_query			= 0xFF32,
3396 	ice_aqc_opc_fw_logs_event			= 0xFF33,
3397 	ice_aqc_opc_fw_logs_get				= 0xFF34,
3398 	ice_aqc_opc_fw_logs_clear			= 0xFF35
3399 };
3400 
3401 #endif /* _ICE_ADMINQ_CMD_H_ */
3402