1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2024, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ICE_ADMINQ_CMD_H_ 33 #define _ICE_ADMINQ_CMD_H_ 34 35 /* This header file defines the Admin Queue commands, error codes and 36 * descriptor format. It is shared between Firmware and Software. 37 */ 38 39 #include "ice_osdep.h" 40 #include "ice_defs.h" 41 #include "ice_bitops.h" 42 43 #define ICE_MAX_VSI 768 44 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 45 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 46 47 enum ice_aq_res_access_type { 48 ICE_RES_READ = 1, 49 ICE_RES_WRITE 50 }; 51 52 struct ice_aqc_generic { 53 __le32 param0; 54 __le32 param1; 55 __le32 addr_high; 56 __le32 addr_low; 57 }; 58 59 /* Get version (direct 0x0001) */ 60 struct ice_aqc_get_ver { 61 __le32 rom_ver; 62 __le32 fw_build; 63 u8 fw_branch; 64 u8 fw_major; 65 u8 fw_minor; 66 u8 fw_patch; 67 u8 api_branch; 68 u8 api_major; 69 u8 api_minor; 70 u8 api_patch; 71 }; 72 73 /* Send driver version (indirect 0x0002) */ 74 struct ice_aqc_driver_ver { 75 u8 major_ver; 76 u8 minor_ver; 77 u8 build_ver; 78 u8 subbuild_ver; 79 u8 reserved[4]; 80 __le32 addr_high; 81 __le32 addr_low; 82 }; 83 84 /* Queue Shutdown (direct 0x0003) */ 85 struct ice_aqc_q_shutdown { 86 u8 driver_unloading; 87 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 88 u8 reserved[15]; 89 }; 90 91 /* Get Expanded Error Code (0x0005, direct) */ 92 struct ice_aqc_get_exp_err { 93 __le32 reason; 94 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 95 __le32 identifier; 96 u8 rsvd[8]; 97 }; 98 99 /* Request resource ownership (direct 0x0008) 100 * Release resource ownership (direct 0x0009) 101 */ 102 struct ice_aqc_req_res { 103 __le16 res_id; 104 #define ICE_AQC_RES_ID_NVM 1 105 #define ICE_AQC_RES_ID_SDP 2 106 #define ICE_AQC_RES_ID_CHNG_LOCK 3 107 #define ICE_AQC_RES_ID_GLBL_LOCK 4 108 __le16 access_type; 109 #define ICE_AQC_RES_ACCESS_READ 1 110 #define ICE_AQC_RES_ACCESS_WRITE 2 111 112 /* Upon successful completion, FW writes this value and driver is 113 * expected to release resource before timeout. This value is provided 114 * in milliseconds. 115 */ 116 __le32 timeout; 117 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 118 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 119 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 120 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 121 /* For SDP: pin ID of the SDP */ 122 __le32 res_number; 123 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 124 __le16 status; 125 #define ICE_AQ_RES_GLBL_SUCCESS 0 126 #define ICE_AQ_RES_GLBL_IN_PROG 1 127 #define ICE_AQ_RES_GLBL_DONE 2 128 u8 reserved[2]; 129 }; 130 131 /* Get function capabilities (indirect 0x000A) 132 * Get device capabilities (indirect 0x000B) 133 */ 134 struct ice_aqc_list_caps { 135 u8 cmd_flags; 136 u8 pf_index; 137 u8 reserved[2]; 138 __le32 count; 139 __le32 addr_high; 140 __le32 addr_low; 141 }; 142 143 /* Device/Function buffer entry, repeated per reported capability */ 144 struct ice_aqc_list_caps_elem { 145 __le16 cap; 146 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001 147 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002 148 #define ICE_AQC_CAPS_OS2BMC 0x0004 149 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 150 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 151 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006 152 #define ICE_AQC_CAPS_WOL_PROXY 0x0008 153 #define ICE_AQC_CAPS_SRIOV 0x0012 154 #define ICE_AQC_CAPS_VF 0x0013 155 #define ICE_AQC_CAPS_VMDQ 0x0014 156 #define ICE_AQC_CAPS_802_1QBG 0x0015 157 #define ICE_AQC_CAPS_802_1BR 0x0016 158 #define ICE_AQC_CAPS_VSI 0x0017 159 #define ICE_AQC_CAPS_DCB 0x0018 160 #define ICE_AQC_CAPS_RSVD 0x0021 161 #define ICE_AQC_CAPS_ISCSI 0x0022 162 #define ICE_AQC_CAPS_RSS 0x0040 163 #define ICE_AQC_CAPS_RXQS 0x0041 164 #define ICE_AQC_CAPS_TXQS 0x0042 165 #define ICE_AQC_CAPS_MSIX 0x0043 166 #define ICE_AQC_CAPS_MAX_MTU 0x0047 167 #define ICE_AQC_CAPS_CEM 0x00F2 168 #define ICE_AQC_CAPS_IWARP 0x0051 169 #define ICE_AQC_CAPS_LED 0x0061 170 #define ICE_AQC_CAPS_SDP 0x0062 171 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 172 #define ICE_AQC_CAPS_SENSOR_READING 0x0067 173 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 174 #define ICE_AQC_CAPS_SKU 0x0074 175 #define ICE_AQC_CAPS_PORT_MAP 0x0075 176 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 177 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 178 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 179 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081 180 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082 181 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083 182 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084 183 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085 184 #define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087 185 #define ICE_AQC_CAPS_DYN_FLATTENING 0x008A 186 #define ICE_AQC_CAPS_OROM_RECOVERY_UPDATE 0x0090 187 #define ICE_AQC_CAPS_ROCEV2_LAG 0x0092 188 #define ICE_AQC_BIT_ROCEV2_LAG 0x01 189 #define ICE_AQC_BIT_SRIOV_LAG 0x02 190 #define ICE_AQC_CAPS_NEXT_CLUSTER_ID 0x0096 191 u8 major_ver; 192 u8 minor_ver; 193 /* Number of resources described by this capability */ 194 __le32 number; 195 /* Only meaningful for some types of resources */ 196 __le32 logical_id; 197 /* Only meaningful for some types of resources */ 198 __le32 phys_id; 199 __le64 rsvd1; 200 __le64 rsvd2; 201 }; 202 203 /* Manage MAC address, read command - indirect (0x0107) 204 * This struct is also used for the response 205 */ 206 struct ice_aqc_manage_mac_read { 207 __le16 flags; /* Zeroed by device driver */ 208 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 209 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 210 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 211 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 212 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 213 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 214 #define ICE_AQC_MAN_MAC_READ_S 4 215 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 216 u8 rsvd[2]; 217 u8 num_addr; /* Used in response */ 218 u8 rsvd1[3]; 219 __le32 addr_high; 220 __le32 addr_low; 221 }; 222 223 /* Response buffer format for manage MAC read command */ 224 struct ice_aqc_manage_mac_read_resp { 225 u8 lport_num; 226 u8 addr_type; 227 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 228 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 229 u8 mac_addr[ETH_ALEN]; 230 }; 231 232 /* Manage MAC address, write command - direct (0x0108) */ 233 struct ice_aqc_manage_mac_write { 234 u8 rsvd; 235 u8 flags; 236 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 237 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 238 #define ICE_AQC_MAN_MAC_WR_S 6 239 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 240 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 241 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 242 /* byte stream in network order */ 243 u8 mac_addr[ETH_ALEN]; 244 __le32 addr_high; 245 __le32 addr_low; 246 }; 247 248 /* Clear PXE Command and response (direct 0x0110) */ 249 struct ice_aqc_clear_pxe { 250 u8 rx_cnt; 251 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 252 u8 reserved[15]; 253 }; 254 255 /* Configure No-Drop Policy Command (direct 0x0112) */ 256 struct ice_aqc_config_no_drop_policy { 257 u8 opts; 258 #define ICE_AQC_FORCE_NO_DROP BIT(0) 259 u8 rsvd[15]; 260 }; 261 262 /* Get switch configuration (0x0200) */ 263 struct ice_aqc_get_sw_cfg { 264 /* Reserved for command and copy of request flags for response */ 265 __le16 flags; 266 /* First desc in case of command and next_elem in case of response 267 * In case of response, if it is not zero, means all the configuration 268 * was not returned and new command shall be sent with this value in 269 * the 'first desc' field 270 */ 271 __le16 element; 272 /* Reserved for command, only used for response */ 273 __le16 num_elems; 274 __le16 rsvd; 275 __le32 addr_high; 276 __le32 addr_low; 277 }; 278 279 /* Each entry in the response buffer is of the following type: */ 280 struct ice_aqc_get_sw_cfg_resp_elem { 281 /* VSI/Port Number */ 282 __le16 vsi_port_num; 283 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 284 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 285 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 286 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 287 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 288 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 289 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 290 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 291 292 /* SWID VSI/Port belongs to */ 293 __le16 swid; 294 295 /* Bit 14..0 : PF/VF number VSI belongs to 296 * Bit 15 : VF indication bit 297 */ 298 __le16 pf_vf_num; 299 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 300 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 301 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 302 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 303 }; 304 305 /* Set Port parameters, (direct, 0x0203) */ 306 struct ice_aqc_set_port_params { 307 __le16 cmd_flags; 308 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 309 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 310 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 311 __le16 bad_frame_vsi; 312 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 313 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 314 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 315 __le16 swid; 316 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 317 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 318 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 319 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 320 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 321 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 322 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 323 u8 lb_mode; 324 #define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_VALID BIT(2) 325 #define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_NORMAL 0x00 326 #define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_NO 0x01 327 #define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_HIGH 0x02 328 u8 reserved[9]; 329 }; 330 331 /* These resource type defines are used for all switch resource 332 * commands where a resource type is required, such as: 333 * Get Resource Allocation command (indirect 0x0204) 334 * Allocate Resources command (indirect 0x0208) 335 * Free Resources command (indirect 0x0209) 336 * Get Allocated Resource Descriptors Command (indirect 0x020A) 337 */ 338 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 339 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 340 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 341 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 342 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 343 #define ICE_AQC_RES_TYPE_RECIPE 0x05 344 #define ICE_AQC_RES_TYPE_PROFILE 0x06 345 #define ICE_AQC_RES_TYPE_SWID 0x07 346 #define ICE_AQC_RES_TYPE_VSI 0x08 347 #define ICE_AQC_RES_TYPE_FLU 0x09 348 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 349 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 350 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 351 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 352 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 353 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 354 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 355 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 356 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 357 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 358 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 359 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 360 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 361 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 362 /* Resource types 0x62-67 are reserved for Hash profile builder */ 363 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 364 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 365 366 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 367 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 368 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 369 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_SHARED BIT(14) 370 #define ICE_AQC_RES_TYPE_FLAG_SUBSCRIBE_CTL BIT(15) 371 372 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 373 374 #define ICE_AQC_RES_TYPE_S 0 375 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 376 377 /* Get Resource Allocation command (indirect 0x0204) */ 378 struct ice_aqc_get_res_alloc { 379 __le16 resp_elem_num; /* Used in response, reserved in command */ 380 u8 reserved[6]; 381 __le32 addr_high; 382 __le32 addr_low; 383 }; 384 385 /* Get Resource Allocation Response Buffer per response */ 386 struct ice_aqc_get_res_resp_elem { 387 __le16 res_type; /* Types defined above cmd 0x0204 */ 388 __le16 total_capacity; /* Resources available to all PF's */ 389 __le16 total_function; /* Resources allocated for a PF */ 390 __le16 total_shared; /* Resources allocated as shared */ 391 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 392 }; 393 394 /* Allocate Resources command (indirect 0x0208) 395 * Free Resources command (indirect 0x0209) 396 */ 397 struct ice_aqc_alloc_free_res_cmd { 398 __le16 num_entries; /* Number of Resource entries */ 399 u8 reserved[6]; 400 __le32 addr_high; 401 __le32 addr_low; 402 }; 403 404 /* Resource descriptor */ 405 struct ice_aqc_res_elem { 406 union { 407 __le16 sw_resp; 408 __le16 flu_resp; 409 } e; 410 }; 411 412 /* Buffer for Allocate/Free Resources commands */ 413 struct ice_aqc_alloc_free_res_elem { 414 __le16 res_type; /* Types defined above cmd 0x0204 */ 415 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 416 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 417 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 418 __le16 num_elems; 419 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 420 }; 421 422 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 423 struct ice_aqc_get_allocd_res_desc { 424 union { 425 struct { 426 __le16 res; /* Types defined above cmd 0x0204 */ 427 __le16 first_desc; 428 __le32 reserved; 429 } cmd; 430 struct { 431 __le16 res; 432 __le16 next_desc; 433 __le16 num_desc; 434 __le16 reserved; 435 } resp; 436 } ops; 437 __le32 addr_high; 438 __le32 addr_low; 439 }; 440 441 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 442 struct ice_aqc_set_vlan_mode { 443 u8 reserved; 444 u8 l2tag_prio_tagging; 445 #define ICE_AQ_VLAN_PRIO_TAG_S 0 446 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 447 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 448 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 449 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 450 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 451 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 452 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 453 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 454 u8 l2tag_reserved[64]; 455 u8 rdma_packet; 456 #define ICE_AQ_VLAN_RDMA_TAG_S 0 457 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 458 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 459 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 460 u8 rdma_reserved[2]; 461 u8 mng_vlan_prot_id; 462 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 463 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 464 u8 prot_id_reserved[30]; 465 }; 466 467 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 468 struct ice_aqc_get_vlan_mode { 469 u8 vlan_mode; 470 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 471 u8 l2tag_prio_tagging; 472 u8 reserved[98]; 473 }; 474 475 /* Add VSI (indirect 0x0210) 476 * Update VSI (indirect 0x0211) 477 * Get VSI (indirect 0x0212) 478 * Free VSI (indirect 0x0213) 479 */ 480 struct ice_aqc_add_get_update_free_vsi { 481 __le16 vsi_num; 482 #define ICE_AQ_VSI_NUM_S 0 483 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 484 #define ICE_AQ_VSI_IS_VALID BIT(15) 485 __le16 cmd_flags; 486 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 487 u8 vf_id; 488 u8 reserved; 489 __le16 vsi_flags; 490 #define ICE_AQ_VSI_TYPE_S 0 491 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 492 #define ICE_AQ_VSI_TYPE_VF 0x0 493 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 494 #define ICE_AQ_VSI_TYPE_PF 0x2 495 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 496 __le32 addr_high; 497 __le32 addr_low; 498 }; 499 500 /* Response descriptor for: 501 * Add VSI (indirect 0x0210) 502 * Update VSI (indirect 0x0211) 503 * Free VSI (indirect 0x0213) 504 */ 505 struct ice_aqc_add_update_free_vsi_resp { 506 __le16 vsi_num; 507 __le16 ext_status; 508 __le16 vsi_used; 509 __le16 vsi_free; 510 __le32 addr_high; 511 __le32 addr_low; 512 }; 513 514 struct ice_aqc_get_vsi_resp { 515 __le16 vsi_num; 516 u8 vf_id; 517 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 518 * These are found above in struct ice_aqc_add_get_update_free_vsi. 519 */ 520 u8 vsi_flags; 521 __le16 vsi_used; 522 __le16 vsi_free; 523 __le32 addr_high; 524 __le32 addr_low; 525 }; 526 527 struct ice_aqc_vsi_props { 528 __le16 valid_sections; 529 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 530 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 531 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 532 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 533 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 534 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 535 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 536 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 537 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 538 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 539 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 540 /* switch section */ 541 u8 sw_id; 542 u8 sw_flags; 543 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 544 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 545 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 546 u8 sw_flags2; 547 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 548 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 549 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 550 #define ICE_AQ_VSI_SW_FLAG_RX_PASS_PRUNE_ENA BIT(3) 551 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 552 u8 veb_stat_id; 553 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 554 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 555 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 556 /* security section */ 557 u8 sec_flags; 558 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 559 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 560 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 561 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 562 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 563 u8 sec_reserved; 564 /* VLAN section */ 565 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 566 u8 inner_vlan_reserved[2]; 567 u8 inner_vlan_flags; 568 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 569 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 570 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 571 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 572 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 573 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 574 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 575 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 576 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 577 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 578 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 579 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 580 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) 581 u8 inner_vlan_reserved2[3]; 582 /* ingress egress up sections */ 583 __le32 ingress_table; /* bitmap, 3 bits per up */ 584 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 585 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 586 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 587 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 588 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 589 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 590 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 591 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 592 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 593 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 594 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 595 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 596 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 597 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 598 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 599 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 600 __le32 egress_table; /* same defines as for ingress table */ 601 /* outer tags section */ 602 __le16 port_based_outer_vlan; 603 u8 outer_vlan_flags; 604 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 605 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 606 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 607 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 608 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 609 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 610 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 611 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 612 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 613 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 614 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 615 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 616 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 617 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 618 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 619 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 620 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 621 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 622 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 623 u8 outer_vlan_reserved; 624 /* queue mapping section */ 625 __le16 mapping_flags; 626 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 627 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 628 __le16 q_mapping[16]; 629 #define ICE_AQ_VSI_Q_S 0 630 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 631 __le16 tc_mapping[8]; 632 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 633 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 634 #define ICE_AQ_VSI_TC_Q_NUM_S 11 635 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 636 /* queueing option section */ 637 u8 q_opt_rss; 638 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 639 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 640 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 641 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 642 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 643 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 644 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 645 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 646 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 647 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 648 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 649 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 650 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 651 u8 q_opt_tc; 652 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 653 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 654 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 655 u8 q_opt_flags; 656 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 657 u8 q_opt_reserved[3]; 658 /* outer up section */ 659 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 660 /* section 10 */ 661 __le16 sect_10_reserved; 662 /* flow director section */ 663 __le16 fd_options; 664 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 665 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 666 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 667 __le16 max_fd_fltr_dedicated; 668 __le16 max_fd_fltr_shared; 669 __le16 fd_def_q; 670 #define ICE_AQ_VSI_FD_DEF_Q_S 0 671 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 672 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 673 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 674 __le16 fd_report_opt; 675 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 676 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 677 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 678 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 679 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 680 /* PASID section */ 681 __le32 pasid_id; 682 #define ICE_AQ_VSI_PASID_ID_S 0 683 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 684 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 685 u8 reserved[24]; 686 }; 687 688 /* Add/update mirror rule - direct (0x0260) */ 689 #define ICE_AQC_RULE_ID_VALID_S 7 690 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 691 #define ICE_AQC_RULE_ID_S 0 692 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 693 694 /* Following defines to be used while processing caller specified mirror list 695 * of VSI indexes. 696 */ 697 /* Action: Byte.bit (1.7) 698 * 0 = Remove VSI from mirror rule 699 * 1 = Add VSI to mirror rule 700 */ 701 #define ICE_AQC_RULE_ACT_S 15 702 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 703 /* Action: 1.2:0.0 = Mirrored VSI */ 704 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 705 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 706 707 /* This is to be used by add/update mirror rule Admin Queue command. 708 * In case of add mirror rule - if rule ID is specified as 709 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 710 * If specified rule_id is valid, then it is used. If specified rule_id 711 * is in use then new mirroring rule is added. 712 */ 713 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 714 715 struct ice_aqc_add_update_mir_rule { 716 __le16 rule_id; 717 718 __le16 rule_type; 719 #define ICE_AQC_RULE_TYPE_S 0 720 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 721 /* VPORT ingress/egress */ 722 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 723 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 724 /* Physical port ingress mirroring. 725 * All traffic received by this port 726 */ 727 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 728 /* Physical port egress mirroring. All traffic sent by this port */ 729 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 730 731 /* Number of mirrored entries. 732 * The values are in the command buffer 733 */ 734 __le16 num_entries; 735 736 /* Destination VSI */ 737 __le16 dest; 738 __le32 addr_high; 739 __le32 addr_low; 740 }; 741 742 /* Delete mirror rule - direct(0x0261) */ 743 struct ice_aqc_delete_mir_rule { 744 __le16 rule_id; 745 __le16 rsvd; 746 747 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 748 * the PF allocated resources, otherwise it is returned to the 749 * shared pool 750 */ 751 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 752 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 753 __le16 flags; 754 755 u8 reserved[10]; 756 }; 757 758 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 759 /* This structure holds get storm configuration response and same structure 760 * is used to perform set_storm_cfg 761 */ 762 struct ice_aqc_storm_cfg { 763 __le32 bcast_thresh_size; 764 __le32 mcast_thresh_size; 765 /* Bit 18:0 - Traffic upper threshold size 766 * Bit 31:19 - Reserved 767 */ 768 #define ICE_AQ_THRESHOLD_S 0 769 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 770 771 __le32 storm_ctrl_ctrl; 772 /* Bit 0: MDIPW - Drop Multicast packets in previous window 773 * Bit 1: MDICW - Drop multicast packets in current window 774 * Bit 2: BDIPW - Drop broadcast packets in previous window 775 * Bit 3: BDICW - Drop broadcast packets in current window 776 */ 777 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 778 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 779 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 780 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 781 /* Bit 7:5 : Reserved */ 782 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 783 * interval size for applying ingress broadcast or multicast storm 784 * control. 785 */ 786 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 787 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 788 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 789 __le32 reserved; 790 }; 791 792 #define ICE_MAX_NUM_RECIPES 64 793 794 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 795 */ 796 struct ice_aqc_sw_rules { 797 /* ops: add switch rules, referring the number of rules. 798 * ops: update switch rules, referring the number of filters 799 * ops: remove switch rules, referring the entry index. 800 * ops: get switch rules, referring to the number of filters. 801 */ 802 __le16 num_rules_fltr_entry_index; 803 u8 reserved[6]; 804 __le32 addr_high; 805 __le32 addr_low; 806 }; 807 808 /* Add switch rule response: 809 * Content of return buffer is same as the input buffer. The status field and 810 * LUT index are updated as part of the response 811 */ 812 struct ice_aqc_sw_rules_elem_hdr { 813 __le16 type; /* Switch rule type, one of T_... */ 814 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 815 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 816 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 817 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 818 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 819 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 820 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 821 __le16 status; 822 }; 823 824 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 825 * This structures describes the lookup rules and associated actions. "index" 826 * is returned as part of a response to a successful Add command, and can be 827 * used to identify the rule for Update/Get/Remove commands. 828 */ 829 struct ice_sw_rule_lkup_rx_tx { 830 struct ice_aqc_sw_rules_elem_hdr hdr; 831 832 __le16 recipe_id; 833 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 834 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 835 __le16 src; 836 __le32 act; 837 838 /* Bit 0:1 - Action type */ 839 #define ICE_SINGLE_ACT_TYPE_S 0x00 840 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 841 842 /* Bit 2 - Loop back enable 843 * Bit 3 - LAN enable 844 */ 845 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 846 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 847 848 /* Action type = 0 - Forward to VSI or VSI list */ 849 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 850 851 #define ICE_SINGLE_ACT_VSI_ID_S 4 852 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 853 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 854 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 855 /* This bit needs to be set if action is forward to VSI list */ 856 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 857 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 858 #define ICE_SINGLE_ACT_DROP BIT(18) 859 860 /* Action type = 1 - Forward to Queue of Queue group */ 861 #define ICE_SINGLE_ACT_TO_Q 0x1 862 #define ICE_SINGLE_ACT_Q_INDEX_S 4 863 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 864 #define ICE_SINGLE_ACT_Q_REGION_S 15 865 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 866 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 867 868 /* Action type = 2 - Prune */ 869 #define ICE_SINGLE_ACT_PRUNE 0x2 870 #define ICE_SINGLE_ACT_EGRESS BIT(15) 871 #define ICE_SINGLE_ACT_INGRESS BIT(16) 872 #define ICE_SINGLE_ACT_PRUNET BIT(17) 873 /* Bit 18 should be set to 0 for this action */ 874 875 /* Action type = 2 - Pointer */ 876 #define ICE_SINGLE_ACT_PTR 0x2 877 #define ICE_SINGLE_ACT_PTR_VAL_S 4 878 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 879 /* Bit 17 should be set if pointed action includes a FWD cmd */ 880 #define ICE_SINGLE_ACT_PTR_HAS_FWD BIT(17) 881 /* Bit 18 should be set to 1 */ 882 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 883 884 /* Action type = 3 - Other actions. Last two bits 885 * are other action identifier 886 */ 887 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 888 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 889 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 890 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 891 892 /* Bit 17:18 - Defines other actions */ 893 /* Other action = 0 - Mirror VSI */ 894 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 895 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 896 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 897 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 898 899 /* Other action = 3 - Set Stat count */ 900 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 901 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 902 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 903 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 904 905 __le16 index; /* The index of the rule in the lookup table */ 906 /* Length and values of the header to be matched per recipe or 907 * lookup-type 908 */ 909 __le16 hdr_len; 910 u8 hdr_data[STRUCT_HACK_VAR_LEN]; 911 }; 912 913 #pragma pack(1) 914 /* Add/Update/Remove large action command/response entry 915 * "index" is returned as part of a response to a successful Add command, and 916 * can be used to identify the action for Update/Get/Remove commands. 917 */ 918 struct ice_sw_rule_lg_act { 919 struct ice_aqc_sw_rules_elem_hdr hdr; 920 921 __le16 index; /* Index in large action table */ 922 __le16 size; 923 /* Max number of large actions */ 924 #define ICE_MAX_LG_ACT 4 925 /* Bit 0:1 - Action type */ 926 #define ICE_LG_ACT_TYPE_S 0 927 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 928 929 /* Action type = 0 - Forward to VSI or VSI list */ 930 #define ICE_LG_ACT_VSI_FORWARDING 0 931 #define ICE_LG_ACT_VSI_ID_S 3 932 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 933 #define ICE_LG_ACT_VSI_LIST_ID_S 3 934 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 935 /* This bit needs to be set if action is forward to VSI list */ 936 #define ICE_LG_ACT_VSI_LIST BIT(13) 937 938 #define ICE_LG_ACT_VALID_BIT BIT(16) 939 940 /* Action type = 1 - Forward to Queue of Queue group */ 941 #define ICE_LG_ACT_TO_Q 0x1 942 #define ICE_LG_ACT_Q_INDEX_S 3 943 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 944 #define ICE_LG_ACT_Q_REGION_S 14 945 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 946 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 947 948 /* Action type = 2 - Prune */ 949 #define ICE_LG_ACT_PRUNE 0x2 950 #define ICE_LG_ACT_EGRESS BIT(14) 951 #define ICE_LG_ACT_INGRESS BIT(15) 952 #define ICE_LG_ACT_PRUNET BIT(16) 953 954 /* Action type = 3 - Mirror VSI */ 955 #define ICE_LG_OTHER_ACT_MIRROR 0x3 956 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 957 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 958 959 /* Action type = 5 - Generic Value */ 960 #define ICE_LG_ACT_GENERIC 0x5 961 #define ICE_LG_ACT_GENERIC_VALUE_S 3 962 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 963 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 964 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 965 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 966 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 967 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 968 969 /* Action = 7 - Set Stat count */ 970 #define ICE_LG_ACT_STAT_COUNT 0x7 971 #define ICE_LG_ACT_STAT_COUNT_S 3 972 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 973 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 974 }; 975 #pragma pack() 976 977 #pragma pack(1) 978 /* Add/Update/Remove VSI list command/response entry 979 * "index" is returned as part of a response to a successful Add command, and 980 * can be used to identify the VSI list for Update/Get/Remove commands. 981 */ 982 struct ice_sw_rule_vsi_list { 983 struct ice_aqc_sw_rules_elem_hdr hdr; 984 985 __le16 index; /* Index of VSI/Prune list */ 986 __le16 number_vsi; 987 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 988 }; 989 #pragma pack() 990 991 #pragma pack(1) 992 /* Query VSI list command/response entry */ 993 struct ice_sw_rule_vsi_list_query { 994 __le16 index; 995 u8 vsi_list[DIVIDE_AND_ROUND_UP(ICE_MAX_VSI, BITS_PER_BYTE)]; 996 }; 997 #pragma pack() 998 999 /* PFC Ignore (direct 0x0301) 1000 * The command and response use the same descriptor structure 1001 */ 1002 struct ice_aqc_pfc_ignore { 1003 u8 tc_bitmap; 1004 u8 cmd_flags; /* unused in response */ 1005 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 1006 #define ICE_AQC_PFC_IGNORE_CLEAR 0 1007 u8 reserved[14]; 1008 }; 1009 1010 /* Query PFC Mode (direct 0x0302) 1011 * Set PFC Mode (direct 0x0303) 1012 */ 1013 struct ice_aqc_set_query_pfc_mode { 1014 u8 pfc_mode; 1015 /* For Set Command response, reserved in all other cases */ 1016 #define ICE_AQC_PFC_NOT_CONFIGURED 0 1017 /* For Query Command response, reserved in all other cases */ 1018 #define ICE_AQC_DCB_DIS 0 1019 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 1020 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 1021 u8 rsvd[15]; 1022 }; 1023 1024 /* Set DCB Parameters (direct 0x0306) */ 1025 struct ice_aqc_set_dcb_params { 1026 u8 cmd_flags; /* unused in response */ 1027 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 1028 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 1029 u8 valid_flags; /* unused in response */ 1030 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 1031 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 1032 u8 rsvd[14]; 1033 }; 1034 1035 /* Get Default Topology (indirect 0x0400) */ 1036 struct ice_aqc_get_topo { 1037 u8 port_num; 1038 u8 num_branches; 1039 __le16 reserved1; 1040 __le32 reserved2; 1041 __le32 addr_high; 1042 __le32 addr_low; 1043 }; 1044 1045 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */ 1046 struct ice_aqc_get_set_tx_topo { 1047 u8 set_flags; 1048 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0) 1049 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1) 1050 #define ICE_AQC_TX_TOPO_FLAGS_SET_PSM BIT(2) 1051 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4) 1052 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5) 1053 u8 get_flags; 1054 #define ICE_AQC_TX_TOPO_GET_NO_UPDATE 0 1055 #define ICE_AQC_TX_TOPO_GET_PSM 1 1056 #define ICE_AQC_TX_TOPO_GET_RAM 2 1057 __le16 reserved1; 1058 __le32 reserved2; 1059 __le32 addr_high; 1060 __le32 addr_low; 1061 }; 1062 1063 /* Update TSE (indirect 0x0403) 1064 * Get TSE (indirect 0x0404) 1065 * Add TSE (indirect 0x0401) 1066 * Delete TSE (indirect 0x040F) 1067 * Move TSE (indirect 0x0408) 1068 * Suspend Nodes (indirect 0x0409) 1069 * Resume Nodes (indirect 0x040A) 1070 */ 1071 struct ice_aqc_sched_elem_cmd { 1072 __le16 num_elem_req; /* Used by commands */ 1073 __le16 num_elem_resp; /* Used by responses */ 1074 __le32 reserved; 1075 __le32 addr_high; 1076 __le32 addr_low; 1077 }; 1078 1079 struct ice_aqc_txsched_move_grp_info_hdr { 1080 __le32 src_parent_teid; 1081 __le32 dest_parent_teid; 1082 __le16 num_elems; 1083 u8 flags; 1084 u8 reserved; 1085 }; 1086 1087 struct ice_aqc_move_elem { 1088 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1089 __le32 teid[STRUCT_HACK_VAR_LEN]; 1090 }; 1091 1092 struct ice_aqc_elem_info_bw { 1093 __le16 bw_profile_idx; 1094 __le16 bw_alloc; 1095 }; 1096 1097 struct ice_aqc_txsched_elem { 1098 u8 elem_type; /* Special field, reserved for some aq calls */ 1099 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1100 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1101 #define ICE_AQC_ELEM_TYPE_TC 0x2 1102 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1103 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1104 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1105 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1106 u8 valid_sections; 1107 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1108 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1109 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1110 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1111 u8 generic; 1112 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1113 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1114 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1115 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1116 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1117 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1118 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1119 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1120 u8 flags; /* Special field, reserved for some aq calls */ 1121 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1122 struct ice_aqc_elem_info_bw cir_bw; 1123 struct ice_aqc_elem_info_bw eir_bw; 1124 __le16 srl_id; 1125 __le16 reserved2; 1126 }; 1127 1128 struct ice_aqc_txsched_elem_data { 1129 __le32 parent_teid; 1130 __le32 node_teid; 1131 struct ice_aqc_txsched_elem data; 1132 }; 1133 1134 struct ice_aqc_txsched_topo_grp_info_hdr { 1135 __le32 parent_teid; 1136 __le16 num_elems; 1137 __le16 reserved2; 1138 }; 1139 1140 struct ice_aqc_add_elem { 1141 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1142 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1143 }; 1144 1145 struct ice_aqc_get_topo_elem { 1146 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1147 struct ice_aqc_txsched_elem_data 1148 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1149 }; 1150 1151 struct ice_aqc_delete_elem { 1152 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1153 __le32 teid[STRUCT_HACK_VAR_LEN]; 1154 }; 1155 1156 /* Query Port ETS (indirect 0x040E) 1157 * 1158 * This indirect command is used to query port TC node configuration. 1159 */ 1160 struct ice_aqc_query_port_ets { 1161 __le32 port_teid; 1162 __le32 reserved; 1163 __le32 addr_high; 1164 __le32 addr_low; 1165 }; 1166 1167 struct ice_aqc_port_ets_elem { 1168 u8 tc_valid_bits; 1169 u8 reserved[3]; 1170 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1171 __le32 up2tc; 1172 u8 tc_bw_share[8]; 1173 __le32 port_eir_prof_id; 1174 __le32 port_cir_prof_id; 1175 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1176 __le32 tc_node_prio; 1177 #define ICE_TC_NODE_PRIO_S 0x4 1178 u8 reserved1[4]; 1179 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1180 }; 1181 1182 /* Rate limiting profile for 1183 * Add RL profile (indirect 0x0410) 1184 * Query RL profile (indirect 0x0411) 1185 * Remove RL profile (indirect 0x0415) 1186 * These indirect commands acts on single or multiple 1187 * RL profiles with specified data. 1188 */ 1189 struct ice_aqc_rl_profile { 1190 __le16 num_profiles; 1191 __le16 num_processed; /* Only for response. Reserved in Command. */ 1192 u8 reserved[4]; 1193 __le32 addr_high; 1194 __le32 addr_low; 1195 }; 1196 1197 struct ice_aqc_rl_profile_elem { 1198 u8 level; 1199 u8 flags; 1200 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1201 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1202 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1203 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1204 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1205 /* The following flag is used for Query RL Profile Data */ 1206 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1207 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1208 1209 __le16 profile_id; 1210 __le16 max_burst_size; 1211 __le16 rl_multiply; 1212 __le16 wake_up_calc; 1213 __le16 rl_encode; 1214 }; 1215 1216 /* Config Node Attributes (indirect 0x0419) 1217 * Query Node Attributes (indirect 0x041A) 1218 */ 1219 struct ice_aqc_node_attr { 1220 __le16 num_entries; /* Number of attributes structures in the buffer */ 1221 u8 reserved[6]; 1222 __le32 addr_high; 1223 __le32 addr_low; 1224 }; 1225 1226 struct ice_aqc_node_attr_elem { 1227 __le32 node_teid; 1228 __le16 max_children; 1229 __le16 children_level; 1230 }; 1231 1232 /* Configure L2 Node CGD (indirect 0x0414) 1233 * This indirect command allows configuring a congestion domain for given L2 1234 * node TEIDs in the scheduler topology. 1235 */ 1236 struct ice_aqc_cfg_l2_node_cgd { 1237 __le16 num_l2_nodes; 1238 u8 reserved[6]; 1239 __le32 addr_high; 1240 __le32 addr_low; 1241 }; 1242 1243 struct ice_aqc_cfg_l2_node_cgd_elem { 1244 __le32 node_teid; 1245 u8 cgd; 1246 u8 reserved[3]; 1247 }; 1248 1249 /* Query Scheduler Resource Allocation (indirect 0x0412) 1250 * This indirect command retrieves the scheduler resources allocated by 1251 * EMP Firmware to the given PF. 1252 */ 1253 struct ice_aqc_query_txsched_res { 1254 u8 reserved[8]; 1255 __le32 addr_high; 1256 __le32 addr_low; 1257 }; 1258 1259 struct ice_aqc_generic_sched_props { 1260 __le16 phys_levels; 1261 __le16 logical_levels; 1262 u8 flattening_bitmap; 1263 u8 max_device_cgds; 1264 u8 max_pf_cgds; 1265 u8 rsvd0; 1266 __le16 rdma_qsets; 1267 u8 rsvd1[22]; 1268 }; 1269 1270 struct ice_aqc_layer_props { 1271 u8 logical_layer; 1272 u8 chunk_size; 1273 __le16 max_device_nodes; 1274 __le16 max_pf_nodes; 1275 u8 rsvd0[4]; 1276 __le16 max_sibl_grp_sz; 1277 __le16 max_cir_rl_profiles; 1278 __le16 max_eir_rl_profiles; 1279 __le16 max_srl_profiles; 1280 u8 rsvd1[14]; 1281 }; 1282 1283 struct ice_aqc_query_txsched_res_resp { 1284 struct ice_aqc_generic_sched_props sched_props; 1285 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1286 }; 1287 1288 /* Query Node to Root Topology (indirect 0x0413) 1289 * This command uses ice_aqc_get_elem as its data buffer. 1290 */ 1291 struct ice_aqc_query_node_to_root { 1292 __le32 teid; 1293 __le32 num_nodes; /* Response only */ 1294 __le32 addr_high; 1295 __le32 addr_low; 1296 }; 1297 1298 /* Get PHY capabilities (indirect 0x0600) */ 1299 struct ice_aqc_get_phy_caps { 1300 u8 lport_num; 1301 u8 reserved; 1302 __le16 param0; 1303 /* 18.0 - Report qualified modules */ 1304 #define ICE_AQC_GET_PHY_RQM BIT(0) 1305 /* 18.1 - 18.3 : Report mode 1306 * 000b - Report topology capabilities, without media 1307 * 001b - Report topology capabilities, with media 1308 * 010b - Report Active configuration 1309 * 011b - Report PHY Type and FEC mode capabilities 1310 * 100b - Report Default capabilities 1311 */ 1312 #define ICE_AQC_REPORT_MODE_S 1 1313 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1314 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1315 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1316 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1317 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1318 __le32 reserved1; 1319 __le32 addr_high; 1320 __le32 addr_low; 1321 }; 1322 1323 /* This is #define of PHY type (Extended): 1324 * The first set of defines is for phy_type_low. 1325 */ 1326 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1327 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1328 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1329 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1330 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1331 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1332 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1333 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1334 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1335 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1336 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1337 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1338 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1339 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1340 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1341 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1342 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1343 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1344 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1345 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1346 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1347 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1348 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1349 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1350 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1351 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1352 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1353 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1354 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1355 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1356 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1357 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1358 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1359 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1360 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1361 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1362 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1363 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1364 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1365 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1366 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1367 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1368 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1369 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1370 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1371 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1372 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1373 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1374 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1375 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1376 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1377 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1378 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1379 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1380 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1381 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1382 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1383 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1384 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1385 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1386 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1387 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1388 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1389 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1390 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1391 /* The second set of defines is for phy_type_high. */ 1392 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1393 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1394 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1395 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1396 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1397 #define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) 1398 #define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) 1399 #define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) 1400 #define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) 1401 #define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) 1402 #define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) 1403 #define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) 1404 #define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) 1405 #define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC BIT_ULL(13) 1406 #define ICE_PHY_TYPE_HIGH_200G_AUI8 BIT_ULL(14) 1407 #define ICE_PHY_TYPE_HIGH_400GBASE_FR8 BIT_ULL(15) 1408 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 15 1409 1410 struct ice_aqc_get_phy_caps_data { 1411 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1412 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1413 u8 caps; 1414 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1415 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1416 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1417 #define ICE_AQC_PHY_EN_LINK BIT(3) 1418 #define ICE_AQC_PHY_AN_MODE BIT(4) 1419 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1420 #define ICE_AQC_PHY_EN_LESM BIT(6) 1421 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1422 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1423 u8 low_power_ctrl_an; 1424 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1425 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1426 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1427 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1428 __le16 eee_cap; 1429 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1430 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1431 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1432 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1433 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1434 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1435 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1436 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1437 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1438 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1439 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1440 __le16 eeer_value; 1441 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1442 u8 phy_fw_ver[8]; 1443 u8 link_fec_options; 1444 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1445 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1446 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1447 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1448 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1449 #define ICE_AQC_PHY_FEC_DIS BIT(5) 1450 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1451 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1452 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1453 u8 module_compliance_enforcement; 1454 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1455 u8 extended_compliance_code; 1456 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1457 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1458 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1459 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1460 #define ICE_AQC_MOD_TYPE_IDENT 1 1461 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1462 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1463 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1464 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1465 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1466 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1467 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1468 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1469 u8 qualified_module_count; 1470 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1471 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1472 struct { 1473 u8 v_oui[3]; 1474 u8 rsvd3; 1475 u8 v_part[16]; 1476 __le32 v_rev; 1477 __le64 rsvd4; 1478 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1479 }; 1480 1481 /* Set PHY capabilities (direct 0x0601) 1482 * NOTE: This command must be followed by setup link and restart auto-neg 1483 */ 1484 struct ice_aqc_set_phy_cfg { 1485 u8 lport_num; 1486 u8 reserved[7]; 1487 __le32 addr_high; 1488 __le32 addr_low; 1489 }; 1490 1491 /* Set PHY config command data structure */ 1492 struct ice_aqc_set_phy_cfg_data { 1493 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1494 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1495 u8 caps; 1496 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1497 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1498 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1499 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1500 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1501 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1502 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1503 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1504 u8 low_power_ctrl_an; 1505 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1506 __le16 eeer_value; 1507 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1508 u8 module_compliance_enforcement; 1509 }; 1510 1511 /* Set MAC Config command data structure (direct 0x0603) */ 1512 struct ice_aqc_set_mac_cfg { 1513 __le16 max_frame_size; 1514 u8 params; 1515 #define ICE_AQ_SET_MAC_PACE_S 3 1516 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1517 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1518 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1519 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1520 u8 tx_tmr_priority; 1521 __le16 tx_tmr_value; 1522 __le16 fc_refresh_threshold; 1523 u8 drop_opts; 1524 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1525 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1526 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1527 u8 reserved[7]; 1528 }; 1529 1530 /* Restart AN command data structure (direct 0x0605) 1531 * Also used for response, with only the lport_num field present. 1532 */ 1533 struct ice_aqc_restart_an { 1534 u8 lport_num; 1535 u8 reserved; 1536 u8 cmd_flags; 1537 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1538 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1539 u8 reserved2[13]; 1540 }; 1541 1542 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1543 struct ice_aqc_get_link_status { 1544 u8 lport_num; 1545 u8 reserved; 1546 __le16 cmd_flags; 1547 #define ICE_AQ_LSE_M 0x3 1548 #define ICE_AQ_LSE_NOP 0x0 1549 #define ICE_AQ_LSE_DIS 0x2 1550 #define ICE_AQ_LSE_ENA 0x3 1551 /* only response uses this flag */ 1552 #define ICE_AQ_LSE_IS_ENABLED 0x1 1553 __le32 reserved2; 1554 __le32 addr_high; 1555 __le32 addr_low; 1556 }; 1557 1558 enum ice_get_link_status_data_version { 1559 ICE_GET_LINK_STATUS_DATA_V1 = 1, 1560 ICE_GET_LINK_STATUS_DATA_V2 = 2, 1561 }; 1562 1563 #define ICE_GET_LINK_STATUS_DATALEN_V1 32 1564 #define ICE_GET_LINK_STATUS_DATALEN_V2 56 1565 1566 /* Get link status response data structure, also used for Link Status Event */ 1567 #pragma pack(1) 1568 struct ice_aqc_get_link_status_data { 1569 u8 topo_media_conflict; 1570 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1571 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1572 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1573 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1574 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1575 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1576 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1577 u8 link_cfg_err; 1578 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1579 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1580 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1581 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1582 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1583 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1584 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1585 u8 link_info; 1586 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1587 #define ICE_AQ_LINK_FAULT BIT(1) 1588 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1589 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1590 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1591 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1592 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1593 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1594 u8 an_info; 1595 #define ICE_AQ_AN_COMPLETED BIT(0) 1596 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1597 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1598 #define ICE_AQ_FEC_EN BIT(3) 1599 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1600 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1601 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1602 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1603 u8 ext_info; 1604 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1605 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1606 /* Port Tx Suspended */ 1607 #define ICE_AQ_LINK_TX_S 2 1608 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1609 #define ICE_AQ_LINK_TX_ACTIVE 0 1610 #define ICE_AQ_LINK_TX_DRAINED 1 1611 #define ICE_AQ_LINK_TX_FLUSHED 3 1612 u8 lb_status; 1613 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1614 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1615 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1616 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1617 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1618 __le16 max_frame_size; 1619 u8 cfg; 1620 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1621 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1622 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1623 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1624 /* Pacing Config */ 1625 #define ICE_AQ_CFG_PACING_S 3 1626 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1627 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1628 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1629 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1630 /* External Device Power Ability */ 1631 u8 power_desc; 1632 #define ICE_AQ_PWR_CLASS_M 0x3F 1633 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1634 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1635 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1636 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1637 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1638 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1639 __le16 link_speed; 1640 #define ICE_AQ_LINK_SPEED_M 0xFFF 1641 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1642 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1643 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1644 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1645 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1646 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1647 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1648 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1649 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1650 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1651 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1652 #define ICE_AQ_LINK_SPEED_200GB BIT(11) 1653 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1654 __le16 reserved3; /* Aligns next field to 8-byte boundary */ 1655 u8 ext_fec_status; 1656 #define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) /* RS 272 FEC enabled */ 1657 u8 reserved4; 1658 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1659 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1660 /* Get link status version 2 link partner data */ 1661 __le64 lp_phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1662 __le64 lp_phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1663 u8 lp_fec_adv; 1664 #define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0) 1665 #define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1) 1666 #define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2) 1667 #define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3) 1668 #define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4) 1669 #define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5) 1670 u8 lp_fec_req; 1671 #define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0) 1672 #define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1) 1673 #define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2) 1674 #define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3) 1675 u8 lp_flowcontrol; 1676 #define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0) 1677 #define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1) 1678 u8 reserved[5]; 1679 }; 1680 1681 #pragma pack() 1682 1683 /* Set event mask command (direct 0x0613) */ 1684 struct ice_aqc_set_event_mask { 1685 u8 lport_num; 1686 u8 reserved[7]; 1687 __le16 event_mask; 1688 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1689 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1690 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1691 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1692 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1693 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1694 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1695 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1696 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1697 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1698 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1699 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1700 u8 reserved1[6]; 1701 }; 1702 1703 /* Set PHY Loopback command (direct 0x0619) */ 1704 struct ice_aqc_set_phy_lb { 1705 u8 lport_num; 1706 u8 lport_num_valid; 1707 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0) 1708 u8 phy_index; 1709 u8 lb_mode; 1710 #define ICE_AQ_PHY_LB_EN BIT(0) 1711 #define ICE_AQ_PHY_LB_TYPE_M BIT(1) 1712 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0 1713 #define ICE_AQ_PHY_LB_TYPE_REMOTE ICE_AQ_PHY_LB_TYPE_M 1714 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2) 1715 #define ICE_AQ_PHY_LB_LEVEL_PMD 0 1716 #define ICE_AQ_PHY_LB_LEVEL_PCS ICE_AQ_PHY_LB_LEVEL_M 1717 u8 reserved2[12]; 1718 }; 1719 1720 /* Set MAC Loopback command (direct 0x0620) */ 1721 struct ice_aqc_set_mac_lb { 1722 u8 lb_mode; 1723 #define ICE_AQ_MAC_LB_EN BIT(0) 1724 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1725 u8 reserved[15]; 1726 }; 1727 1728 /* Get sensor reading (direct 0x0632) */ 1729 struct ice_aqc_get_sensor_reading { 1730 u8 sensor; 1731 #define ICE_AQC_INT_TEMP_SENSOR 0x0 1732 u8 format; 1733 #define ICE_AQC_INT_TEMP_FORMAT 0x0 1734 u8 reserved[6]; 1735 __le32 addr_high; 1736 __le32 addr_low; 1737 }; 1738 1739 /* Get sensor reading response (direct 0x0632) */ 1740 struct ice_aqc_get_sensor_reading_resp { 1741 union { 1742 u8 raw[8]; 1743 /* Output data for sensor 0x00, format 0x00 */ 1744 struct { 1745 s8 temp; 1746 u8 temp_warning_threshold; 1747 u8 temp_critical_threshold; 1748 u8 temp_fatal_threshold; 1749 u8 reserved[4]; 1750 } s0f0; 1751 } data; 1752 }; 1753 1754 /* DNL Get Status command (indirect 0x0680) 1755 * Structure used for the response, the command uses the generic 1756 * ice_aqc_generic struct to pass a buffer address to the FW. 1757 */ 1758 struct ice_aqc_dnl_get_status { 1759 u8 ctx; 1760 u8 status; 1761 #define ICE_AQ_DNL_STATUS_IDLE 0x0 1762 #define ICE_AQ_DNL_STATUS_RESERVED 0x1 1763 #define ICE_AQ_DNL_STATUS_STOPPED 0x2 1764 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */ 1765 #define ICE_AQ_DNL_SRC_S 3 1766 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S) 1767 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S) 1768 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S) 1769 u8 stack_ptr; 1770 #define ICE_AQ_DNL_ST_PTR_S 0x0 1771 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S) 1772 u8 engine_flags; 1773 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2) 1774 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3) 1775 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4) 1776 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5) 1777 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6) 1778 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7) 1779 __le16 pc; 1780 __le16 activity_id; 1781 __le32 addr_high; 1782 __le32 addr_low; 1783 }; 1784 1785 struct ice_aqc_dnl_get_status_data { 1786 __le16 activity_err_code; 1787 __le16 act_err_code; 1788 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */ 1789 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */ 1790 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */ 1791 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */ 1792 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */ 1793 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */ 1794 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */ 1795 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */ 1796 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */ 1797 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */ 1798 __le32 execution_time; /* in nanoseconds */ 1799 __le16 lib_ver; 1800 u8 psto_local_sz; 1801 u8 psto_global_sz; 1802 u8 stack_sz; 1803 #define ICE_AQ_DNL_STACK_SZ_S 0 1804 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S) 1805 u8 port_count; 1806 #define ICE_AQ_DNL_PORT_CNT_S 0 1807 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S) 1808 __le16 act_cache_cntr; 1809 u32 i2c_clk_cntr; 1810 u32 mdio_clk_cntr; 1811 u32 sb_iosf_clk_cntr; 1812 }; 1813 1814 /* DNL run command (direct 0x0681) */ 1815 struct ice_aqc_dnl_run_command { 1816 u8 reserved0; 1817 u8 command; 1818 #define ICE_AQ_DNL_CMD_S 0 1819 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S) 1820 #define ICE_AQ_DNL_CMD_RESET 0x0 1821 #define ICE_AQ_DNL_CMD_RUN 0x1 1822 #define ICE_AQ_DNL_CMD_STEP 0x3 1823 #define ICE_AQ_DNL_CMD_ABORT 0x4 1824 #define ICE_AQ_DNL_CMD_SET_PC 0x7 1825 #define ICE_AQ_DNL_CMD_SRC_S 3 1826 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S) 1827 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0 1828 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1 1829 __le16 new_pc; 1830 u8 reserved1[12]; 1831 }; 1832 1833 /* DNL call command (indirect 0x0682) 1834 * Struct is used for both command and response 1835 */ 1836 struct ice_aqc_dnl_call_command { 1837 u8 ctx; /* Used in command, reserved in response */ 1838 u8 reserved; 1839 __le16 activity_id; 1840 #define ICE_AQC_ACT_ID_DNL 0x1129 1841 __le32 reserved1; 1842 __le32 addr_high; 1843 __le32 addr_low; 1844 }; 1845 1846 struct ice_aqc_dnl_equa_param { 1847 __le16 data_in; 1848 #define ICE_AQC_RX_EQU_SHIFT 8 1849 #define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT) 1850 #define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT) 1851 #define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT) 1852 #define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT) 1853 #define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT) 1854 #define ICE_AQC_RX_EQU_DRATE (0x15 << ICE_AQC_RX_EQU_SHIFT) 1855 #define ICE_AQC_TX_EQU_PRE1 0x0 1856 #define ICE_AQC_TX_EQU_PRE3 0x3 1857 #define ICE_AQC_TX_EQU_ATTEN 0x4 1858 #define ICE_AQC_TX_EQU_POST1 0x8 1859 #define ICE_AQC_TX_EQU_PRE2 0xC 1860 __le16 op_code_serdes_sel; 1861 #define ICE_AQC_OP_CODE_SHIFT 4 1862 #define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT) 1863 #define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT) 1864 __le32 reserved[3]; 1865 }; 1866 1867 struct ice_aqc_dnl_equa_resp { 1868 /* Equalization value can be -ve */ 1869 int val; 1870 __le32 reserved[3]; 1871 }; 1872 1873 /* DNL call command/response buffer (indirect 0x0682) */ 1874 struct ice_aqc_dnl_call { 1875 union { 1876 struct ice_aqc_dnl_equa_param txrx_equa_reqs; 1877 __le32 stores[4]; 1878 struct ice_aqc_dnl_equa_resp txrx_equa_resp; 1879 } sto; 1880 }; 1881 1882 /* Used for both commands: 1883 * DNL read sto command (indirect 0x0683) 1884 * DNL write sto command (indirect 0x0684) 1885 */ 1886 struct ice_aqc_dnl_read_write_command { 1887 u8 ctx; 1888 u8 sto_sel; /* STORE select */ 1889 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0 1890 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1 1891 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2 1892 __le16 offset; 1893 __le32 data; /* Used for write sto only */ 1894 __le32 addr_high; /* Used for read sto only */ 1895 __le32 addr_low; /* Used for read sto only */ 1896 }; 1897 1898 /* Used for both command responses: 1899 * DNL read sto response (indirect 0x0683) 1900 * DNL write sto response (indirect 0x0684) 1901 */ 1902 struct ice_aqc_dnl_read_write_response { 1903 u8 reserved; 1904 u8 status; /* Reserved for read command */ 1905 __le16 size; /* Reserved for write command */ 1906 __le32 data; /* Reserved for write command */ 1907 __le32 addr_high; /* Reserved for write command */ 1908 __le32 addr_low; /* Reserved for write command */ 1909 }; 1910 1911 /* DNL set breakpoints command (indirect 0x0686) */ 1912 struct ice_aqc_dnl_set_breakpoints_command { 1913 __le32 reserved[2]; 1914 __le32 addr_high; 1915 __le32 addr_low; 1916 }; 1917 1918 /* DNL set breakpoints data buffer structure (indirect 0x0686) */ 1919 struct ice_aqc_dnl_set_breakpoints { 1920 u8 ctx; 1921 u8 ena; /* 0- disabled, 1- enabled */ 1922 __le16 offset; 1923 __le16 activity_id; 1924 }; 1925 1926 /* DNL read log data command(indirect 0x0687) */ 1927 struct ice_aqc_dnl_read_log_command { 1928 __le16 reserved0; 1929 __le16 offset; 1930 __le32 reserved1; 1931 __le32 addr_high; 1932 __le32 addr_low; 1933 1934 }; 1935 1936 /* DNL read log data response(indirect 0x0687) */ 1937 struct ice_aqc_dnl_read_log_response { 1938 __le16 reserved; 1939 __le16 size; 1940 __le32 data; 1941 __le32 addr_high; 1942 __le32 addr_low; 1943 1944 }; 1945 1946 struct ice_aqc_link_topo_params { 1947 u8 lport_num; 1948 u8 lport_num_valid; 1949 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1950 u8 node_type_ctx; 1951 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1952 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1953 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1954 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1955 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1956 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1957 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1958 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1959 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1960 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1961 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1962 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1963 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1964 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1965 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1966 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1967 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1968 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1969 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1970 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1971 u8 index; 1972 }; 1973 1974 struct ice_aqc_link_topo_addr { 1975 struct ice_aqc_link_topo_params topo_params; 1976 __le16 handle; 1977 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1978 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1979 /* Used to decode the handle field */ 1980 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1981 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM 0 1982 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ BIT(9) 1983 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1984 /* In case of a Mezzanine type */ 1985 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1986 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1987 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1988 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1989 /* In case of a LOM type */ 1990 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1991 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1992 }; 1993 1994 /* Get Link Topology Handle (direct, 0x06E0) */ 1995 struct ice_aqc_get_link_topo { 1996 struct ice_aqc_link_topo_addr addr; 1997 u8 node_part_num; 1998 #define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1999 u8 rsvd[9]; 2000 }; 2001 2002 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 2003 struct ice_aqc_i2c { 2004 struct ice_aqc_link_topo_addr topo_addr; 2005 __le16 i2c_addr; 2006 u8 i2c_params; 2007 #define ICE_AQC_I2C_DATA_SIZE_S 0 2008 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S) 2009 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4) 2010 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0 2011 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M 2012 #define ICE_AQC_I2C_DATA_OFFSET_S 5 2013 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S) 2014 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 2015 u8 rsvd; 2016 __le16 i2c_bus_addr; 2017 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F 2018 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF 2019 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 2020 }; 2021 2022 /* Read I2C Response (direct, 0x06E2) */ 2023 struct ice_aqc_read_i2c_resp { 2024 u8 i2c_data[16]; 2025 }; 2026 2027 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */ 2028 struct ice_aqc_mdio { 2029 struct ice_aqc_link_topo_addr topo_addr; 2030 u8 mdio_device_addr; 2031 #define ICE_AQC_MDIO_DEV_S 0 2032 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S) 2033 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5) 2034 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6) 2035 u8 mdio_bus_address; 2036 #define ICE_AQC_MDIO_BUS_ADDR_S 0 2037 #define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S) 2038 __le16 offset; 2039 __le16 data; /* Input in write cmd, output in read cmd. */ 2040 u8 rsvd1[4]; 2041 }; 2042 2043 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */ 2044 struct ice_aqc_gpio_by_func { 2045 struct ice_aqc_link_topo_addr topo_addr; 2046 u8 io_func_num; 2047 #define ICE_AQC_GPIO_FUNC_S 0 2048 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S) 2049 u8 io_value; /* Input in write cmd, output in read cmd. */ 2050 #define ICE_AQC_GPIO_ON BIT(0) 2051 #define ICE_AQC_GPIO_OFF 0 2052 u8 rsvd[8]; 2053 }; 2054 2055 /* Set LED (direct, 0x06E8) */ 2056 struct ice_aqc_set_led { 2057 struct ice_aqc_link_topo_addr topo_addr; 2058 u8 color_and_blink; 2059 #define ICE_AQC_LED_COLOR_S 0 2060 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S) 2061 #define ICE_AQC_LED_COLOR_SKIP 0 2062 #define ICE_AQC_LED_COLOR_RED 1 2063 #define ICE_AQC_LED_COLOR_ORANGE 2 2064 #define ICE_AQC_LED_COLOR_YELLOW 3 2065 #define ICE_AQC_LED_COLOR_GREEN 4 2066 #define ICE_AQC_LED_COLOR_BLUE 5 2067 #define ICE_AQC_LED_COLOR_PURPLE 6 2068 #define ICE_AQC_LED_BLINK_S 3 2069 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S) 2070 #define ICE_AQC_LED_BLINK_NONE 0 2071 #define ICE_AQC_LED_BLINK_SLOW 1 2072 #define ICE_AQC_LED_BLINK_SLOW_MAC 2 2073 #define ICE_AQC_LED_BLINK_SLOW_FLTR 3 2074 #define ICE_AQC_LED_BLINK_FAST 5 2075 #define ICE_AQC_LED_BLINK_FAST_MAC 6 2076 #define ICE_AQC_LED_BLINK_FAST_FLTR 7 2077 u8 rsvd[9]; 2078 }; 2079 2080 /* Set Port Identification LED (direct, 0x06E9) */ 2081 struct ice_aqc_set_port_id_led { 2082 u8 lport_num; 2083 u8 lport_num_valid; 2084 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 2085 u8 ident_mode; 2086 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 2087 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 2088 u8 rsvd[13]; 2089 }; 2090 2091 /* Get Port Options (indirect, 0x06EA) */ 2092 struct ice_aqc_get_port_options { 2093 u8 lport_num; 2094 u8 lport_num_valid; 2095 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0) 2096 u8 port_options_count; 2097 #define ICE_AQC_PORT_OPT_COUNT_S 0 2098 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) 2099 #define ICE_AQC_PORT_OPT_MAX 16 2100 u8 innermost_phy_index; 2101 u8 port_options; 2102 #define ICE_AQC_PORT_OPT_ACTIVE_S 0 2103 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) 2104 #define ICE_AQC_PORT_OPT_FORCED BIT(6) 2105 #define ICE_AQC_PORT_OPT_VALID BIT(7) 2106 u8 pending_port_option_status; 2107 #define ICE_AQC_PENDING_PORT_OPT_IDX_S 0 2108 #define ICE_AQC_PENDING_PORT_OPT_IDX_M (0xF << ICE_AQC_PENDING_PORT_OPT_IDX_S) 2109 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 2110 u8 rsvd[2]; 2111 __le32 addr_high; 2112 __le32 addr_low; 2113 }; 2114 2115 struct ice_aqc_get_port_options_elem { 2116 u8 pmd; 2117 #define ICE_AQC_PORT_INV_PORT_OPT 4 2118 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 2119 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) 2120 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 2121 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) 2122 u8 max_lane_speed; 2123 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0 2124 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) 2125 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 2126 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 2127 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 2128 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 2129 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 2130 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 2131 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 2132 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 2133 #define ICE_AQC_PORT_OPT_MAX_LANE_200G 8 2134 u8 global_scid[2]; 2135 u8 phy_scid[2]; 2136 u8 pf2port_cid[2]; 2137 }; 2138 2139 /* Set Port Option (direct, 0x06EB) */ 2140 struct ice_aqc_set_port_option { 2141 u8 lport_num; 2142 u8 lport_num_valid; 2143 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) 2144 u8 selected_port_option; 2145 u8 rsvd[13]; 2146 }; 2147 2148 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 2149 struct ice_aqc_gpio { 2150 __le16 gpio_ctrl_handle; 2151 #define ICE_AQC_GPIO_HANDLE_S 0 2152 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 2153 u8 gpio_num; 2154 u8 gpio_val; 2155 u8 rsvd[12]; 2156 }; 2157 2158 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 2159 struct ice_aqc_sff_eeprom { 2160 u8 lport_num; 2161 u8 lport_num_valid; 2162 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 2163 __le16 i2c_bus_addr; 2164 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 2165 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 2166 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 2167 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 2168 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 2169 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 2170 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 2171 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 2172 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 2173 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 2174 #define ICE_AQC_SFF_IS_WRITE BIT(15) 2175 __le16 i2c_mem_addr; 2176 __le16 eeprom_page; 2177 #define ICE_AQC_SFF_EEPROM_BANK_S 0 2178 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 2179 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 2180 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 2181 __le32 addr_high; 2182 __le32 addr_low; 2183 }; 2184 2185 /* SW Set GPIO command (indirect 0x6EF) 2186 * SW Get GPIO command (indirect 0x6F0) 2187 */ 2188 struct ice_aqc_sw_gpio { 2189 __le16 gpio_ctrl_handle; 2190 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 2191 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 2192 u8 gpio_num; 2193 #define ICE_AQC_SW_GPIO_NUMBER_S 0 2194 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 2195 u8 gpio_params; 2196 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 2197 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 2198 u8 rsvd[12]; 2199 }; 2200 2201 /* Program Topology Device NVM (direct, 0x06F2) */ 2202 struct ice_aqc_prog_topo_dev_nvm { 2203 struct ice_aqc_link_topo_params topo_params; 2204 u8 rsvd[12]; 2205 }; 2206 2207 /* Read Topology Device NVM (direct, 0x06F3) */ 2208 struct ice_aqc_read_topo_dev_nvm { 2209 struct ice_aqc_link_topo_params topo_params; 2210 __le32 start_address; 2211 #define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8 2212 u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE]; 2213 }; 2214 2215 /* NVM Read command (indirect 0x0701) 2216 * NVM Erase commands (direct 0x0702) 2217 * NVM Write commands (indirect 0x0703) 2218 * NVM Write Activate commands (direct 0x0707) 2219 * NVM Shadow RAM Dump commands (direct 0x0707) 2220 */ 2221 struct ice_aqc_nvm { 2222 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 2223 __le16 offset_low; 2224 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 2225 u8 cmd_flags; 2226 #define ICE_AQC_NVM_LAST_CMD BIT(0) 2227 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 2228 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 2229 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 2230 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 2231 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 2232 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 2233 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 2234 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 2235 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 2236 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 2237 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 2238 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 2239 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 2240 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 2241 #define ICE_AQC_NVM_RESET_LVL_M MAKEMASK(0x3, 0) /* Write reply only */ 2242 #define ICE_AQC_NVM_POR_FLAG 0 2243 #define ICE_AQC_NVM_PERST_FLAG 1 2244 #define ICE_AQC_NVM_EMPR_FLAG 2 2245 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 2246 /* For Write Activate, several flags are sent as part of a separate 2247 * flags2 field using a separate byte. For simplicity of the software 2248 * interface, we pass the flags as a 16 bit value so these flags are 2249 * all offset by 8 bits 2250 */ 2251 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 2252 __le16 module_typeid; 2253 __le16 length; 2254 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 2255 __le32 addr_high; 2256 __le32 addr_low; 2257 }; 2258 2259 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 2260 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 2261 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 2262 2263 #define ICE_AQC_NVM_START_POINT 0 2264 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 2265 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 2266 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 2267 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 2268 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 2269 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 2270 2271 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 2272 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 2273 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 2274 2275 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 2276 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 2277 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 2278 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 2279 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 2280 2281 #define ICE_AQC_NVM_SDP_CFG_PTR_OFFSET 0xD8 2282 #define ICE_AQC_NVM_SDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 2283 #define ICE_AQC_NVM_SDP_CFG_PTR_M MAKEMASK(0x7FFF, 0) 2284 #define ICE_AQC_NVM_SDP_CFG_PTR_TYPE_M BIT(15) 2285 #define ICE_AQC_NVM_SDP_CFG_HEADER_LEN 2 /* In Bytes */ 2286 #define ICE_AQC_NVM_SDP_CFG_SEC_LEN_LEN 2 /* In Bytes */ 2287 #define ICE_AQC_NVM_SDP_CFG_DATA_LEN 14 /* In Bytes */ 2288 #define ICE_AQC_NVM_SDP_CFG_MAX_SECTION_SIZE 7 2289 #define ICE_AQC_NVM_SDP_CFG_PIN_SIZE 10 2290 #define ICE_AQC_NVM_SDP_CFG_PIN_OFFSET 6 2291 #define ICE_AQC_NVM_SDP_CFG_PIN_MASK MAKEMASK(0x3FF, \ 2292 ICE_AQC_NVM_SDP_CFG_PIN_OFFSET) 2293 #define ICE_AQC_NVM_SDP_CFG_CHAN_OFFSET 4 2294 #define ICE_AQC_NVM_SDP_CFG_CHAN_MASK MAKEMASK(0x3, \ 2295 ICE_AQC_NVM_SDP_CFG_CHAN_OFFSET) 2296 #define ICE_AQC_NVM_SDP_CFG_DIR_OFFSET 3 2297 #define ICE_AQC_NVM_SDP_CFG_DIR_MASK MAKEMASK(0x1, \ 2298 ICE_AQC_NVM_SDP_CFG_DIR_OFFSET) 2299 #define ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET 0 2300 #define ICE_AQC_NVM_SDP_CFG_SDP_NUM_MASK MAKEMASK(0x7, \ 2301 ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET) 2302 #define ICE_AQC_NVM_SDP_CFG_NA_PIN_MASK MAKEMASK(0x1, 15) 2303 2304 #define ICE_AQC_NVM_MINSREV_MOD_ID 0x130 2305 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B 2306 #define ICE_AQC_NVM_CMPO_MOD_ID 0x153 2307 2308 /* Cage Max Power override NVM module */ 2309 struct ice_aqc_nvm_cmpo { 2310 __le16 length; 2311 #define ICE_AQC_NVM_CMPO_ENABLE BIT(8) 2312 __le16 cages_cfg[8]; 2313 }; 2314 2315 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the 2316 * type field is excluded from the section when reading and writing from 2317 * a module using the module_typeid field with these AQ commands. 2318 */ 2319 struct ice_aqc_nvm_minsrev { 2320 __le16 length; 2321 __le16 validity; 2322 #define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0) 2323 #define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1) 2324 __le16 nvm_minsrev_l; 2325 __le16 nvm_minsrev_h; 2326 __le16 orom_minsrev_l; 2327 __le16 orom_minsrev_h; 2328 }; 2329 2330 struct ice_aqc_nvm_tx_topo_user_sel { 2331 __le16 length; 2332 u8 data; 2333 #define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4) 2334 u8 reserved; 2335 }; 2336 2337 /* Used for 0x0704 as well as for 0x0705 commands */ 2338 struct ice_aqc_nvm_cfg { 2339 u8 cmd_flags; 2340 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 2341 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 2342 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 2343 u8 reserved; 2344 __le16 count; 2345 __le16 id; 2346 u8 reserved1[2]; 2347 __le32 addr_high; 2348 __le32 addr_low; 2349 }; 2350 2351 struct ice_aqc_nvm_cfg_data { 2352 __le16 field_id; 2353 __le16 field_options; 2354 __le16 field_value; 2355 }; 2356 2357 /* NVM Checksum Command (direct, 0x0706) */ 2358 struct ice_aqc_nvm_checksum { 2359 u8 flags; 2360 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 2361 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 2362 u8 rsvd; 2363 __le16 checksum; /* Used only by response */ 2364 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 2365 u8 rsvd2[12]; 2366 }; 2367 2368 /* Used for NVM Sanitization command - 0x070C */ 2369 struct ice_aqc_nvm_sanitization { 2370 u8 cmd_flags; 2371 #define ICE_AQ_NVM_SANITIZE_REQ_READ 0 2372 #define ICE_AQ_NVM_SANITIZE_REQ_OPERATE BIT(0) 2373 2374 #define ICE_AQ_NVM_SANITIZE_READ_SUBJECT_NVM_BITS 0 2375 #define ICE_AQ_NVM_SANITIZE_READ_SUBJECT_NVM_STATE BIT(1) 2376 #define ICE_AQ_NVM_SANITIZE_OPERATE_SUBJECT_CLEAR 0 2377 u8 values; 2378 #define ICE_AQ_NVM_SANITIZE_NVM_BITS_HOST_CLEAN_SUPPORT BIT(0) 2379 #define ICE_AQ_NVM_SANITIZE_NVM_BITS_BMC_CLEAN_SUPPORT BIT(2) 2380 #define ICE_AQ_NVM_SANITIZE_NVM_STATE_HOST_CLEAN_DONE BIT(0) 2381 #define ICE_AQ_NVM_SANITIZE_NVM_STATE_HOST_CLEAN_SUCCESS BIT(1) 2382 #define ICE_AQ_NVM_SANITIZE_NVM_STATE_BMC_CLEAN_DONE BIT(2) 2383 #define ICE_AQ_NVM_SANITIZE_NVM_STATE_BMC_CLEAN_SUCCESS BIT(3) 2384 #define ICE_AQ_NVM_SANITIZE_OPERATE_HOST_CLEAN_DONE BIT(0) 2385 #define ICE_AQ_NVM_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS BIT(1) 2386 #define ICE_AQ_NVM_SANITIZE_OPERATE_BMC_CLEAN_DONE BIT(2) 2387 #define ICE_AQ_NVM_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS BIT(3) 2388 u8 reserved[14]; 2389 }; 2390 2391 /* 2392 * Send to PF command (indirect 0x0801) ID is only used by PF 2393 * 2394 * Send to VF command (indirect 0x0802) ID is only used by PF 2395 * 2396 */ 2397 struct ice_aqc_pf_vf_msg { 2398 __le32 id; 2399 u32 reserved; 2400 __le32 addr_high; 2401 __le32 addr_low; 2402 }; 2403 2404 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */ 2405 struct ice_aqc_read_write_alt_direct { 2406 __le32 dword0_addr; 2407 __le32 dword0_value; 2408 __le32 dword1_addr; 2409 __le32 dword1_value; 2410 }; 2411 2412 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */ 2413 struct ice_aqc_read_write_alt_indirect { 2414 __le32 base_dword_addr; 2415 __le32 num_dwords; 2416 __le32 addr_high; 2417 __le32 addr_low; 2418 }; 2419 2420 /* Done Alternate Write (direct 0x0904) */ 2421 struct ice_aqc_done_alt_write { 2422 u8 flags; 2423 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0) 2424 #define ICE_AQC_RESP_RESET_NEEDED BIT(1) 2425 u8 reserved[15]; 2426 }; 2427 2428 /* Clear Port Alternate Write (direct 0x0906) */ 2429 struct ice_aqc_clear_port_alt_write { 2430 u8 reserved[16]; 2431 }; 2432 2433 /* Get LLDP MIB (indirect 0x0A00) 2434 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 2435 * as the format is the same. 2436 */ 2437 struct ice_aqc_lldp_get_mib { 2438 u8 type; 2439 #define ICE_AQ_LLDP_MIB_TYPE_S 0 2440 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 2441 #define ICE_AQ_LLDP_MIB_LOCAL 0 2442 #define ICE_AQ_LLDP_MIB_REMOTE 1 2443 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 2444 #define ICE_AQ_LLDP_BRID_TYPE_S 2 2445 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 2446 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 2447 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 2448 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 2449 #define ICE_AQ_LLDP_TX_S 0x4 2450 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 2451 #define ICE_AQ_LLDP_TX_ACTIVE 0 2452 #define ICE_AQ_LLDP_TX_SUSPENDED 1 2453 #define ICE_AQ_LLDP_TX_FLUSHED 3 2454 /* DCBX mode */ 2455 #define ICE_AQ_LLDP_DCBX_S 6 2456 #define ICE_AQ_LLDP_DCBX_M (0x3 << ICE_AQ_LLDP_DCBX_S) 2457 #define ICE_AQ_LLDP_DCBX_NA 0 2458 #define ICE_AQ_LLDP_DCBX_CEE 1 2459 #define ICE_AQ_LLDP_DCBX_IEEE 2 2460 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 2461 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 2462 * Get LLDP MIB (0x0A00) response only. 2463 */ 2464 u8 state; 2465 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_S 0 2466 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M \ 2467 (0x1 << ICE_AQ_LLDP_MIB_CHANGE_STATE_S) 2468 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 2469 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 2470 __le16 local_len; 2471 __le16 remote_len; 2472 u8 reserved[2]; 2473 __le32 addr_high; 2474 __le32 addr_low; 2475 }; 2476 2477 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 2478 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 2479 struct ice_aqc_lldp_set_mib_change { 2480 u8 command; 2481 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2482 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 2483 #define ICE_AQ_LLDP_MIB_PENDING_S 1 2484 #define ICE_AQ_LLDP_MIB_PENDING_M \ 2485 (0x1 << ICE_AQ_LLDP_MIB_PENDING_S) 2486 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 2487 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 2488 u8 reserved[15]; 2489 }; 2490 2491 /* Add LLDP TLV (indirect 0x0A02) 2492 * Delete LLDP TLV (indirect 0x0A04) 2493 */ 2494 struct ice_aqc_lldp_add_delete_tlv { 2495 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2496 u8 reserved1[1]; 2497 __le16 len; 2498 u8 reserved2[4]; 2499 __le32 addr_high; 2500 __le32 addr_low; 2501 }; 2502 2503 /* Update LLDP TLV (indirect 0x0A03) */ 2504 struct ice_aqc_lldp_update_tlv { 2505 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2506 u8 reserved; 2507 __le16 old_len; 2508 __le16 new_offset; 2509 __le16 new_len; 2510 __le32 addr_high; 2511 __le32 addr_low; 2512 }; 2513 2514 /* Stop LLDP (direct 0x0A05) */ 2515 struct ice_aqc_lldp_stop { 2516 u8 command; 2517 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 2518 #define ICE_AQ_LLDP_AGENT_STOP 0x0 2519 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 2520 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 2521 u8 reserved[15]; 2522 }; 2523 2524 /* Start LLDP (direct 0x0A06) */ 2525 struct ice_aqc_lldp_start { 2526 u8 command; 2527 #define ICE_AQ_LLDP_AGENT_START BIT(0) 2528 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 2529 u8 reserved[15]; 2530 }; 2531 2532 /* Get CEE DCBX Oper Config (0x0A07) 2533 * The command uses the generic descriptor struct and 2534 * returns the struct below as an indirect response. 2535 */ 2536 struct ice_aqc_get_cee_dcb_cfg_resp { 2537 u8 oper_num_tc; 2538 u8 oper_prio_tc[4]; 2539 u8 oper_tc_bw[8]; 2540 u8 oper_pfc_en; 2541 __le16 oper_app_prio; 2542 #define ICE_AQC_CEE_APP_FCOE_S 0 2543 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 2544 #define ICE_AQC_CEE_APP_ISCSI_S 3 2545 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 2546 #define ICE_AQC_CEE_APP_FIP_S 8 2547 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 2548 __le32 tlv_status; 2549 #define ICE_AQC_CEE_PG_STATUS_S 0 2550 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 2551 #define ICE_AQC_CEE_PFC_STATUS_S 3 2552 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 2553 #define ICE_AQC_CEE_FCOE_STATUS_S 8 2554 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 2555 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 2556 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 2557 #define ICE_AQC_CEE_FIP_STATUS_S 16 2558 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 2559 u8 reserved[12]; 2560 }; 2561 2562 /* Set Local LLDP MIB (indirect 0x0A08) 2563 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 2564 */ 2565 struct ice_aqc_lldp_set_local_mib { 2566 u8 type; 2567 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 2568 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 2569 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 2570 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 2571 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 2572 u8 reserved0; 2573 __le16 length; 2574 u8 reserved1[4]; 2575 __le32 addr_high; 2576 __le32 addr_low; 2577 }; 2578 2579 struct ice_aqc_lldp_set_local_mib_resp { 2580 u8 status; 2581 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 2582 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 2583 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 2584 u8 reserved[15]; 2585 }; 2586 2587 /* Stop/Start LLDP Agent (direct 0x0A09) 2588 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2589 * The same structure is used for the response, with the command field 2590 * being used as the status field. 2591 */ 2592 struct ice_aqc_lldp_stop_start_specific_agent { 2593 u8 command; 2594 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2595 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2596 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2597 u8 reserved[15]; 2598 }; 2599 2600 /* LLDP Filter Control (direct 0x0A0A) */ 2601 struct ice_aqc_lldp_filter_ctrl { 2602 u8 cmd_flags; 2603 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 2604 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 2605 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 2606 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 2607 u8 reserved1; 2608 __le16 vsi_num; 2609 u8 reserved2[12]; 2610 }; 2611 2612 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2613 struct ice_aqc_get_set_rss_key { 2614 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 2615 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 2616 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 2617 __le16 vsi_id; 2618 u8 reserved[6]; 2619 __le32 addr_high; 2620 __le32 addr_low; 2621 }; 2622 2623 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2624 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2625 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2626 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2627 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2628 2629 /** 2630 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2631 * @standard_rss_key: 40 most significant bytes of hash key 2632 * @extended_hash_key: 12 least significant bytes of hash key 2633 * 2634 * Set/Get 40 byte hash key using standard_rss_key field, and set 2635 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2636 * standard_rss_key field for 40 most significant bytes and the 2637 * extended_hash_key field for the 12 least significant bytes of hash key. 2638 */ 2639 struct ice_aqc_get_set_rss_keys { 2640 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2641 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2642 }; 2643 2644 enum ice_lut_type { 2645 ICE_LUT_VSI = 0, 2646 ICE_LUT_PF = 1, 2647 ICE_LUT_GLOBAL = 2, 2648 ICE_LUT_TYPE_MASK = 3, 2649 ICE_LUT_PF_SMALL = 5, /* yields ICE_LUT_PF when &= ICE_LUT_TYPE_MASK */ 2650 }; 2651 2652 enum ice_lut_size { 2653 ICE_LUT_VSI_SIZE = 64, 2654 ICE_LUT_PF_SMALL_SIZE = 128, 2655 ICE_LUT_GLOBAL_SIZE = 512, 2656 ICE_LUT_PF_SIZE = 2048, 2657 }; 2658 2659 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2660 struct ice_aqc_get_set_rss_lut { 2661 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2662 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2663 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2664 __le16 vsi_id; 2665 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2666 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2667 (ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2668 2669 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2670 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2671 (ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2672 2673 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2674 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2675 2676 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2677 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2678 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2679 2680 __le16 flags; 2681 __le32 reserved; 2682 __le32 addr_high; 2683 __le32 addr_low; 2684 }; 2685 2686 /* Sideband Control Interface Commands */ 2687 /* Neighbor Device Request (indirect 0x0C00); also used for the response. */ 2688 struct ice_aqc_neigh_dev_req { 2689 __le16 sb_data_len; 2690 u8 reserved[6]; 2691 __le32 addr_high; 2692 __le32 addr_low; 2693 }; 2694 2695 /* Add Tx LAN Queues (indirect 0x0C30) */ 2696 struct ice_aqc_add_txqs { 2697 u8 num_qgrps; 2698 u8 reserved[3]; 2699 __le32 reserved1; 2700 __le32 addr_high; 2701 __le32 addr_low; 2702 }; 2703 2704 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2705 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2706 */ 2707 struct ice_aqc_add_txqs_perq { 2708 __le16 txq_id; 2709 u8 rsvd[2]; 2710 __le32 q_teid; 2711 u8 txq_ctx[22]; 2712 u8 rsvd2[2]; 2713 struct ice_aqc_txsched_elem info; 2714 }; 2715 2716 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2717 * is an array of the following structs. Please note that the length of 2718 * each struct ice_aqc_add_tx_qgrp is variable due 2719 * to the variable number of queues in each group! 2720 */ 2721 struct ice_aqc_add_tx_qgrp { 2722 __le32 parent_teid; 2723 u8 num_txqs; 2724 u8 rsvd[3]; 2725 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2726 }; 2727 2728 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2729 struct ice_aqc_dis_txqs { 2730 u8 cmd_type; 2731 #define ICE_AQC_Q_DIS_CMD_S 0 2732 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2733 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2734 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2735 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2736 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2737 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2738 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2739 u8 num_entries; 2740 __le16 vmvf_and_timeout; 2741 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2742 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2743 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2744 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2745 __le32 blocked_cgds; 2746 __le32 addr_high; 2747 __le32 addr_low; 2748 }; 2749 2750 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2751 * contains the following structures, arrayed one after the 2752 * other. 2753 * Note: Since the q_id is 16 bits wide, if the 2754 * number of queues is even, then 2 bytes of alignment MUST be 2755 * added before the start of the next group, to allow correct 2756 * alignment of the parent_teid field. 2757 */ 2758 #pragma pack(1) 2759 struct ice_aqc_dis_txq_item { 2760 __le32 parent_teid; 2761 u8 num_qs; 2762 u8 rsvd; 2763 /* The length of the q_id array varies according to num_qs */ 2764 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2765 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2766 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2767 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2768 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2769 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2770 }; 2771 #pragma pack() 2772 2773 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2774 struct ice_aqc_txqs_cleanup { 2775 __le16 caller_opc; 2776 __le16 cmd_tag; 2777 u8 reserved[12]; 2778 }; 2779 2780 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2781 struct ice_aqc_move_txqs { 2782 u8 cmd_type; 2783 #define ICE_AQC_Q_CMD_TYPE_S 0 2784 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2785 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2786 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2787 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2788 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2789 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2790 u8 num_qs; 2791 u8 rsvd; 2792 u8 timeout; 2793 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2794 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2795 __le32 blocked_cgds; 2796 __le32 addr_high; 2797 __le32 addr_low; 2798 }; 2799 2800 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2801 struct ice_aqc_move_txqs_elem { 2802 __le16 txq_id; 2803 u8 q_cgd; 2804 u8 rsvd; 2805 __le32 q_teid; 2806 }; 2807 2808 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2809 struct ice_aqc_move_txqs_data { 2810 __le32 src_teid; 2811 __le32 dest_teid; 2812 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2813 }; 2814 2815 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2816 struct ice_aqc_add_rdma_qset { 2817 u8 num_qset_grps; 2818 u8 reserved[7]; 2819 __le32 addr_high; 2820 __le32 addr_low; 2821 }; 2822 2823 /* This is the descriptor of each qset entry for the Add Tx RDMA Queue Set 2824 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2825 */ 2826 struct ice_aqc_add_tx_rdma_qset_entry { 2827 __le16 tx_qset_id; 2828 u8 rsvd[2]; 2829 __le32 qset_teid; 2830 struct ice_aqc_txsched_elem info; 2831 }; 2832 2833 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2834 * is an array of the following structs. Please note that the length of 2835 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2836 * number of queues in each group! 2837 */ 2838 struct ice_aqc_add_rdma_qset_data { 2839 __le32 parent_teid; 2840 __le16 num_qsets; 2841 u8 rsvd[2]; 2842 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[STRUCT_HACK_VAR_LEN]; 2843 }; 2844 2845 /* Move RDMA Queue Set (indirect 0x0C34) */ 2846 struct ice_aqc_move_rdma_qset_cmd { 2847 u8 num_rdma_qset; /* Used by commands and response */ 2848 #define ICE_AQC_PF_MODE_SAME_PF 0x0 2849 #define ICE_AQC_PF_MODE_GIVE_OWNERSHIP 0x1 2850 #define ICE_AQC_PF_MODE_KEEP_OWNERSHIP 0x2 2851 u8 flags; 2852 u8 reserved[6]; 2853 __le32 addr_high; 2854 __le32 addr_low; 2855 }; 2856 2857 /* Buffer */ 2858 struct ice_aqc_move_rdma_qset_buffer_desc { 2859 __le16 tx_qset_id; 2860 __le16 qset_teid; 2861 }; 2862 2863 struct ice_aqc_move_rdma_qset_buffer { 2864 __le32 src_parent_teid; 2865 __le32 dest_parent_teid; 2866 struct ice_aqc_move_rdma_qset_buffer_desc descs[STRUCT_HACK_VAR_LEN]; 2867 }; 2868 2869 /* Download Package (indirect 0x0C40) */ 2870 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2871 struct ice_aqc_download_pkg { 2872 u8 flags; 2873 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2874 u8 reserved[3]; 2875 __le32 reserved1; 2876 __le32 addr_high; 2877 __le32 addr_low; 2878 }; 2879 2880 struct ice_aqc_download_pkg_resp { 2881 __le32 error_offset; 2882 __le32 error_info; 2883 __le32 addr_high; 2884 __le32 addr_low; 2885 }; 2886 2887 /* Get Package Info List (indirect 0x0C43) */ 2888 struct ice_aqc_get_pkg_info_list { 2889 __le32 reserved1; 2890 __le32 reserved2; 2891 __le32 addr_high; 2892 __le32 addr_low; 2893 }; 2894 2895 /* Version format for packages */ 2896 struct ice_pkg_ver { 2897 u8 major; 2898 u8 minor; 2899 u8 update; 2900 u8 draft; 2901 }; 2902 2903 #define ICE_PKG_NAME_SIZE 32 2904 #define ICE_SEG_ID_SIZE 28 2905 #define ICE_SEG_NAME_SIZE 28 2906 2907 struct ice_aqc_get_pkg_info { 2908 struct ice_pkg_ver ver; 2909 char name[ICE_SEG_NAME_SIZE]; 2910 __le32 track_id; 2911 u8 is_in_nvm; 2912 u8 is_active; 2913 u8 is_active_at_boot; 2914 u8 is_modified; 2915 }; 2916 2917 /* Get Package Info List response buffer format (0x0C43) */ 2918 struct ice_aqc_get_pkg_info_resp { 2919 __le32 count; 2920 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2921 }; 2922 2923 /* Driver Shared Parameters (direct, 0x0C90) */ 2924 struct ice_aqc_driver_shared_params { 2925 u8 set_or_get_op; 2926 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2927 #define ICE_AQC_DRIVER_PARAM_SET ((u8)0) 2928 #define ICE_AQC_DRIVER_PARAM_GET ((u8)1) 2929 u8 param_indx; 2930 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2931 u8 rsvd[2]; 2932 __le32 param_val; 2933 __le32 addr_high; 2934 __le32 addr_low; 2935 }; 2936 2937 /* Lan Queue Overflow Event (direct, 0x1001) */ 2938 struct ice_aqc_event_lan_overflow { 2939 __le32 prtdcb_ruptq; 2940 __le32 qtx_ctl; 2941 u8 reserved[8]; 2942 }; 2943 2944 /* Debug Dump Internal Data (indirect 0xFF08) */ 2945 struct ice_aqc_debug_dump_internals { 2946 __le16 cluster_id; /* Expresses next cluster ID in response */ 2947 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW_E810 0 2948 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL_E810 1 2949 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED_E810 2 2950 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES_E810 3 2951 /* EMP_DRAM only dumpable in device debug mode */ 2952 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM_E810 4 2953 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK_E810 5 2954 /* AUX_REGS only dumpable in device debug mode */ 2955 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS_E810 6 2956 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB_E810 7 2957 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P_E810 8 2958 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG_E810 9 2959 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE_E810 21 2960 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_MNG_TRANSACTIONS_E810 22 2961 2962 /* Start cluster to discover first available cluster */ 2963 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_START_ALL 0 2964 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW_E830 100 2965 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL_E830 101 2966 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED_E830 102 2967 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES_E830 103 2968 /* EMP_DRAM only dumpable in device debug mode */ 2969 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK_E830 105 2970 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB_E830 107 2971 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P_E830 108 2972 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG_E830 109 2973 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE_E830 121 2974 __le16 table_id; /* Used only for non-memory clusters */ 2975 __le32 idx; /* In table entries for tables, in bytes for memory */ 2976 __le32 addr_high; 2977 __le32 addr_low; 2978 }; 2979 2980 enum ice_aqc_fw_logging_mod { 2981 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2982 ICE_AQC_FW_LOG_ID_CTRL, 2983 ICE_AQC_FW_LOG_ID_LINK, 2984 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2985 ICE_AQC_FW_LOG_ID_DNL, 2986 ICE_AQC_FW_LOG_ID_I2C, 2987 ICE_AQC_FW_LOG_ID_SDP, 2988 ICE_AQC_FW_LOG_ID_MDIO, 2989 ICE_AQC_FW_LOG_ID_ADMINQ, 2990 ICE_AQC_FW_LOG_ID_HDMA, 2991 ICE_AQC_FW_LOG_ID_LLDP, 2992 ICE_AQC_FW_LOG_ID_DCBX, 2993 ICE_AQC_FW_LOG_ID_DCB, 2994 ICE_AQC_FW_LOG_ID_XLR, 2995 ICE_AQC_FW_LOG_ID_NVM, 2996 ICE_AQC_FW_LOG_ID_AUTH, 2997 ICE_AQC_FW_LOG_ID_VPD, 2998 ICE_AQC_FW_LOG_ID_IOSF, 2999 ICE_AQC_FW_LOG_ID_PARSER, 3000 ICE_AQC_FW_LOG_ID_SW, 3001 ICE_AQC_FW_LOG_ID_SCHEDULER, 3002 ICE_AQC_FW_LOG_ID_TXQ, 3003 ICE_AQC_FW_LOG_ID_RSVD, 3004 ICE_AQC_FW_LOG_ID_POST, 3005 ICE_AQC_FW_LOG_ID_WATCHDOG, 3006 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 3007 ICE_AQC_FW_LOG_ID_MNG, 3008 ICE_AQC_FW_LOG_ID_SYNCE, 3009 ICE_AQC_FW_LOG_ID_HEALTH, 3010 ICE_AQC_FW_LOG_ID_TSDRV, 3011 ICE_AQC_FW_LOG_ID_PFREG, 3012 ICE_AQC_FW_LOG_ID_MDLVER, 3013 ICE_AQC_FW_LOG_ID_MAX, 3014 }; 3015 3016 /* Set Health Status (direct 0xFF20) */ 3017 struct ice_aqc_set_health_status_config { 3018 u8 event_source; 3019 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 3020 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 3021 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 3022 u8 reserved[15]; 3023 }; 3024 3025 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 3026 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 3027 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 3028 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 3029 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 3030 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 3031 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 3032 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 3033 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE 0x109 3034 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 3035 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 3036 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 3037 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 3038 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 3039 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 3040 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 3041 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 3042 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 3043 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 3044 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 3045 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 3046 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120 3047 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121 3048 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 3049 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 3050 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 3051 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 3052 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 3053 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 3054 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 3055 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION 0x507 3056 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION 0x508 3057 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 3058 #define ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT 0x50A 3059 #define ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET 0x50B 3060 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL 0x50C 3061 #define ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL 0x50D 3062 #define ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP 0x1000 3063 #define ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL 0x1001 3064 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ 0x1002 3065 3066 /* Get Health Status codes (indirect 0xFF21) */ 3067 struct ice_aqc_get_supported_health_status_codes { 3068 __le16 health_code_count; 3069 u8 reserved[6]; 3070 __le32 addr_high; 3071 __le32 addr_low; 3072 }; 3073 3074 /* Get Health Status (indirect 0xFF22) */ 3075 struct ice_aqc_get_health_status { 3076 __le16 health_status_count; 3077 u8 reserved[6]; 3078 __le32 addr_high; 3079 __le32 addr_low; 3080 }; 3081 3082 /* Get Health Status event buffer entry, (0xFF22) 3083 * repeated per reported health status 3084 */ 3085 struct ice_aqc_health_status_elem { 3086 __le16 health_status_code; 3087 __le16 event_source; 3088 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 3089 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 3090 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 3091 __le32 internal_data1; 3092 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 3093 __le32 internal_data2; 3094 }; 3095 3096 /* Clear Health Status (direct 0xFF23) */ 3097 struct ice_aqc_clear_health_status { 3098 __le32 reserved[4]; 3099 }; 3100 3101 /* Set FW Logging configuration (indirect 0xFF30) 3102 * Register for FW Logging (indirect 0xFF31) 3103 * Query FW Logging (indirect 0xFF32) 3104 * FW Log Event (indirect 0xFF33) 3105 * Get FW Log (indirect 0xFF34) 3106 * Clear FW Log (indirect 0xFF35) 3107 */ 3108 struct ice_aqc_fw_log { 3109 u8 cmd_flags; 3110 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 3111 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 3112 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) 3113 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 3114 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 3115 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 3116 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0) 3117 u8 rsp_flag; 3118 #define ICE_AQC_FW_LOG_MORE_DATA BIT(1) 3119 __le16 fw_rt_msb; 3120 union { 3121 struct { 3122 __le32 fw_rt_lsb; 3123 } sync; 3124 struct { 3125 __le16 log_resolution; 3126 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 3127 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 3128 __le16 mdl_cnt; 3129 } cfg; 3130 } ops; 3131 __le32 addr_high; 3132 __le32 addr_low; 3133 }; 3134 3135 /* Response Buffer for: 3136 * Set Firmware Logging Configuration (0xFF30) 3137 * Query FW Logging (0xFF32) 3138 */ 3139 struct ice_aqc_fw_log_cfg_resp { 3140 __le16 module_identifier; 3141 u8 log_level; 3142 u8 rsvd0; 3143 }; 3144 3145 /** 3146 * struct ice_aq_desc - Admin Queue (AQ) descriptor 3147 * @flags: ICE_AQ_FLAG_* flags 3148 * @opcode: AQ command opcode 3149 * @datalen: length in bytes of indirect/external data buffer 3150 * @retval: return value from firmware 3151 * @cookie_high: opaque data high-half 3152 * @cookie_low: opaque data low-half 3153 * @params: command-specific parameters 3154 * 3155 * Descriptor format for commands the driver posts on the Admin Transmit Queue 3156 * (ATQ). The firmware writes back onto the command descriptor and returns 3157 * the result of the command. Asynchronous events that are not an immediate 3158 * result of the command are written to the Admin Receive Queue (ARQ) using 3159 * the same descriptor format. Descriptors are in little-endian notation with 3160 * 32-bit words. 3161 */ 3162 struct ice_aq_desc { 3163 __le16 flags; 3164 __le16 opcode; 3165 __le16 datalen; 3166 __le16 retval; 3167 __le32 cookie_high; 3168 __le32 cookie_low; 3169 union { 3170 u8 raw[16]; 3171 struct ice_aqc_generic generic; 3172 struct ice_aqc_get_ver get_ver; 3173 struct ice_aqc_driver_ver driver_ver; 3174 struct ice_aqc_q_shutdown q_shutdown; 3175 struct ice_aqc_get_exp_err exp_err; 3176 struct ice_aqc_req_res res_owner; 3177 struct ice_aqc_manage_mac_read mac_read; 3178 struct ice_aqc_manage_mac_write mac_write; 3179 struct ice_aqc_clear_pxe clear_pxe; 3180 struct ice_aqc_config_no_drop_policy no_drop; 3181 struct ice_aqc_add_update_mir_rule add_update_rule; 3182 struct ice_aqc_delete_mir_rule del_rule; 3183 struct ice_aqc_list_caps get_cap; 3184 struct ice_aqc_get_phy_caps get_phy; 3185 struct ice_aqc_set_phy_cfg set_phy; 3186 struct ice_aqc_restart_an restart_an; 3187 struct ice_aqc_get_sensor_reading get_sensor_reading; 3188 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; 3189 struct ice_aqc_dnl_get_status get_status; 3190 struct ice_aqc_dnl_run_command dnl_run; 3191 struct ice_aqc_dnl_call_command dnl_call; 3192 struct ice_aqc_dnl_read_write_command dnl_read_write; 3193 struct ice_aqc_dnl_read_write_response dnl_read_write_resp; 3194 struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; 3195 struct ice_aqc_dnl_read_log_command dnl_read_log; 3196 struct ice_aqc_dnl_read_log_response dnl_read_log_resp; 3197 struct ice_aqc_i2c read_write_i2c; 3198 struct ice_aqc_read_i2c_resp read_i2c_resp; 3199 struct ice_aqc_mdio read_write_mdio; 3200 struct ice_aqc_gpio_by_func read_write_gpio_by_func; 3201 struct ice_aqc_gpio read_write_gpio; 3202 struct ice_aqc_sw_gpio sw_read_write_gpio; 3203 struct ice_aqc_set_led set_led; 3204 struct ice_aqc_mdio read_mdio; 3205 struct ice_aqc_mdio write_mdio; 3206 struct ice_aqc_sff_eeprom read_write_sff_param; 3207 struct ice_aqc_set_port_id_led set_port_id_led; 3208 struct ice_aqc_get_port_options get_port_options; 3209 struct ice_aqc_set_port_option set_port_option; 3210 struct ice_aqc_get_sw_cfg get_sw_conf; 3211 struct ice_aqc_set_port_params set_port_params; 3212 struct ice_aqc_sw_rules sw_rules; 3213 struct ice_aqc_storm_cfg storm_conf; 3214 struct ice_aqc_get_topo get_topo; 3215 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 3216 struct ice_aqc_query_txsched_res query_sched_res; 3217 struct ice_aqc_query_node_to_root query_node_to_root; 3218 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 3219 struct ice_aqc_query_port_ets port_ets; 3220 struct ice_aqc_rl_profile rl_profile; 3221 struct ice_aqc_node_attr node_attr; 3222 struct ice_aqc_nvm nvm; 3223 struct ice_aqc_nvm_cfg nvm_cfg; 3224 struct ice_aqc_nvm_checksum nvm_checksum; 3225 struct ice_aqc_nvm_sanitization sanitization; 3226 struct ice_aqc_pf_vf_msg virt; 3227 struct ice_aqc_read_write_alt_direct read_write_alt_direct; 3228 struct ice_aqc_read_write_alt_indirect read_write_alt_indirect; 3229 struct ice_aqc_done_alt_write done_alt_write; 3230 struct ice_aqc_clear_port_alt_write clear_port_alt_write; 3231 struct ice_aqc_pfc_ignore pfc_ignore; 3232 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 3233 struct ice_aqc_set_dcb_params set_dcb_params; 3234 struct ice_aqc_lldp_get_mib lldp_get_mib; 3235 struct ice_aqc_lldp_set_mib_change lldp_set_event; 3236 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 3237 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 3238 struct ice_aqc_lldp_stop lldp_stop; 3239 struct ice_aqc_lldp_start lldp_start; 3240 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 3241 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 3242 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 3243 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 3244 struct ice_aqc_get_set_rss_key get_set_rss_key; 3245 struct ice_aqc_neigh_dev_req neigh_dev; 3246 struct ice_aqc_add_txqs add_txqs; 3247 struct ice_aqc_dis_txqs dis_txqs; 3248 struct ice_aqc_move_txqs move_txqs; 3249 struct ice_aqc_add_rdma_qset add_rdma_qset; 3250 struct ice_aqc_move_rdma_qset_cmd move_rdma_qset; 3251 struct ice_aqc_txqs_cleanup txqs_cleanup; 3252 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 3253 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 3254 struct ice_aqc_get_vsi_resp get_vsi_resp; 3255 struct ice_aqc_download_pkg download_pkg; 3256 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 3257 struct ice_aqc_driver_shared_params drv_shared_params; 3258 struct ice_aqc_fw_log fw_log; 3259 struct ice_aqc_debug_dump_internals debug_dump; 3260 struct ice_aqc_set_mac_lb set_mac_lb; 3261 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 3262 struct ice_aqc_get_res_alloc get_res; 3263 struct ice_aqc_get_allocd_res_desc get_res_desc; 3264 struct ice_aqc_set_mac_cfg set_mac_cfg; 3265 struct ice_aqc_set_event_mask set_event_mask; 3266 struct ice_aqc_get_link_status get_link_status; 3267 struct ice_aqc_event_lan_overflow lan_overflow; 3268 struct ice_aqc_get_link_topo get_link_topo; 3269 struct ice_aqc_set_health_status_config 3270 set_health_status_config; 3271 struct ice_aqc_get_supported_health_status_codes 3272 get_supported_health_status_codes; 3273 struct ice_aqc_get_health_status get_health_status; 3274 struct ice_aqc_clear_health_status clear_health_status; 3275 struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm; 3276 struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm; 3277 struct ice_aqc_get_set_tx_topo get_set_tx_topo; 3278 } params; 3279 }; 3280 3281 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 3282 #define ICE_AQ_LG_BUF 512 3283 3284 /* Flags sub-structure 3285 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 3286 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 3287 */ 3288 3289 /* command flags and offsets */ 3290 #define ICE_AQ_FLAG_DD_S 0 3291 #define ICE_AQ_FLAG_CMP_S 1 3292 #define ICE_AQ_FLAG_ERR_S 2 3293 #define ICE_AQ_FLAG_VFE_S 3 3294 #define ICE_AQ_FLAG_LB_S 9 3295 #define ICE_AQ_FLAG_RD_S 10 3296 #define ICE_AQ_FLAG_VFC_S 11 3297 #define ICE_AQ_FLAG_BUF_S 12 3298 #define ICE_AQ_FLAG_SI_S 13 3299 #define ICE_AQ_FLAG_EI_S 14 3300 #define ICE_AQ_FLAG_FE_S 15 3301 3302 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 3303 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 3304 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 3305 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 3306 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 3307 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 3308 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 3309 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 3310 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 3311 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 3312 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 3313 3314 /* error codes */ 3315 enum ice_aq_err { 3316 ICE_AQ_RC_OK = 0, /* Success */ 3317 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 3318 ICE_AQ_RC_ENOENT = 2, /* No such element */ 3319 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 3320 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 3321 ICE_AQ_RC_EIO = 5, /* I/O error */ 3322 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 3323 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 3324 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 3325 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 3326 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 3327 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 3328 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 3329 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 3330 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 3331 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 3332 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 3333 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 3334 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 3335 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 3336 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 3337 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 3338 ICE_AQ_RC_EFBIG = 22, /* File too big */ 3339 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 3340 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 3341 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 3342 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 3343 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 3344 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 3345 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 3346 }; 3347 3348 /* Admin Queue command opcodes */ 3349 enum ice_adminq_opc { 3350 /* AQ commands */ 3351 ice_aqc_opc_get_ver = 0x0001, 3352 ice_aqc_opc_driver_ver = 0x0002, 3353 ice_aqc_opc_q_shutdown = 0x0003, 3354 ice_aqc_opc_get_exp_err = 0x0005, 3355 3356 /* resource ownership */ 3357 ice_aqc_opc_req_res = 0x0008, 3358 ice_aqc_opc_release_res = 0x0009, 3359 3360 /* device/function capabilities */ 3361 ice_aqc_opc_list_func_caps = 0x000A, 3362 ice_aqc_opc_list_dev_caps = 0x000B, 3363 3364 /* manage MAC address */ 3365 ice_aqc_opc_manage_mac_read = 0x0107, 3366 ice_aqc_opc_manage_mac_write = 0x0108, 3367 3368 /* PXE */ 3369 ice_aqc_opc_clear_pxe_mode = 0x0110, 3370 3371 ice_aqc_opc_config_no_drop_policy = 0x0112, 3372 3373 /* internal switch commands */ 3374 ice_aqc_opc_get_sw_cfg = 0x0200, 3375 ice_aqc_opc_set_port_params = 0x0203, 3376 3377 /* Alloc/Free/Get Resources */ 3378 ice_aqc_opc_get_res_alloc = 0x0204, 3379 ice_aqc_opc_alloc_res = 0x0208, 3380 ice_aqc_opc_free_res = 0x0209, 3381 ice_aqc_opc_get_allocd_res_desc = 0x020A, 3382 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 3383 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 3384 3385 /* VSI commands */ 3386 ice_aqc_opc_add_vsi = 0x0210, 3387 ice_aqc_opc_update_vsi = 0x0211, 3388 ice_aqc_opc_get_vsi_params = 0x0212, 3389 ice_aqc_opc_free_vsi = 0x0213, 3390 3391 /* Mirroring rules - add/update, delete */ 3392 ice_aqc_opc_add_update_mir_rule = 0x0260, 3393 ice_aqc_opc_del_mir_rule = 0x0261, 3394 3395 /* storm configuration */ 3396 ice_aqc_opc_set_storm_cfg = 0x0280, 3397 ice_aqc_opc_get_storm_cfg = 0x0281, 3398 3399 /* switch rules population commands */ 3400 ice_aqc_opc_add_sw_rules = 0x02A0, 3401 ice_aqc_opc_update_sw_rules = 0x02A1, 3402 ice_aqc_opc_remove_sw_rules = 0x02A2, 3403 ice_aqc_opc_get_sw_rules = 0x02A3, 3404 ice_aqc_opc_clear_pf_cfg = 0x02A4, 3405 3406 /* DCB commands */ 3407 ice_aqc_opc_pfc_ignore = 0x0301, 3408 ice_aqc_opc_query_pfc_mode = 0x0302, 3409 ice_aqc_opc_set_pfc_mode = 0x0303, 3410 ice_aqc_opc_set_dcb_params = 0x0306, 3411 3412 /* transmit scheduler commands */ 3413 ice_aqc_opc_get_dflt_topo = 0x0400, 3414 ice_aqc_opc_add_sched_elems = 0x0401, 3415 ice_aqc_opc_cfg_sched_elems = 0x0403, 3416 ice_aqc_opc_get_sched_elems = 0x0404, 3417 ice_aqc_opc_move_sched_elems = 0x0408, 3418 ice_aqc_opc_suspend_sched_elems = 0x0409, 3419 ice_aqc_opc_resume_sched_elems = 0x040A, 3420 ice_aqc_opc_query_port_ets = 0x040E, 3421 ice_aqc_opc_delete_sched_elems = 0x040F, 3422 ice_aqc_opc_add_rl_profiles = 0x0410, 3423 ice_aqc_opc_query_rl_profiles = 0x0411, 3424 ice_aqc_opc_query_sched_res = 0x0412, 3425 ice_aqc_opc_query_node_to_root = 0x0413, 3426 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 3427 ice_aqc_opc_remove_rl_profiles = 0x0415, 3428 ice_aqc_opc_set_tx_topo = 0x0417, 3429 ice_aqc_opc_get_tx_topo = 0x0418, 3430 ice_aqc_opc_cfg_node_attr = 0x0419, 3431 ice_aqc_opc_query_node_attr = 0x041A, 3432 3433 /* PHY commands */ 3434 ice_aqc_opc_get_phy_caps = 0x0600, 3435 ice_aqc_opc_set_phy_cfg = 0x0601, 3436 ice_aqc_opc_set_mac_cfg = 0x0603, 3437 ice_aqc_opc_restart_an = 0x0605, 3438 ice_aqc_opc_get_link_status = 0x0607, 3439 ice_aqc_opc_set_event_mask = 0x0613, 3440 ice_aqc_opc_set_mac_lb = 0x0620, 3441 ice_aqc_opc_get_sensor_reading = 0x0632, 3442 ice_aqc_opc_dnl_get_status = 0x0680, 3443 ice_aqc_opc_dnl_run = 0x0681, 3444 ice_aqc_opc_dnl_call = 0x0682, 3445 ice_aqc_opc_dnl_read_sto = 0x0683, 3446 ice_aqc_opc_dnl_write_sto = 0x0684, 3447 ice_aqc_opc_dnl_set_breakpoints = 0x0686, 3448 ice_aqc_opc_dnl_read_log = 0x0687, 3449 ice_aqc_opc_get_link_topo = 0x06E0, 3450 ice_aqc_opc_read_i2c = 0x06E2, 3451 ice_aqc_opc_write_i2c = 0x06E3, 3452 ice_aqc_opc_read_mdio = 0x06E4, 3453 ice_aqc_opc_write_mdio = 0x06E5, 3454 ice_aqc_opc_set_gpio_by_func = 0x06E6, 3455 ice_aqc_opc_get_gpio_by_func = 0x06E7, 3456 ice_aqc_opc_set_led = 0x06E8, 3457 ice_aqc_opc_set_port_id_led = 0x06E9, 3458 ice_aqc_opc_get_port_options = 0x06EA, 3459 ice_aqc_opc_set_port_option = 0x06EB, 3460 ice_aqc_opc_set_gpio = 0x06EC, 3461 ice_aqc_opc_get_gpio = 0x06ED, 3462 ice_aqc_opc_sff_eeprom = 0x06EE, 3463 ice_aqc_opc_sw_set_gpio = 0x06EF, 3464 ice_aqc_opc_sw_get_gpio = 0x06F0, 3465 ice_aqc_opc_prog_topo_dev_nvm = 0x06F2, 3466 ice_aqc_opc_read_topo_dev_nvm = 0x06F3, 3467 3468 /* NVM commands */ 3469 ice_aqc_opc_nvm_read = 0x0701, 3470 ice_aqc_opc_nvm_erase = 0x0702, 3471 ice_aqc_opc_nvm_write = 0x0703, 3472 ice_aqc_opc_nvm_cfg_read = 0x0704, 3473 ice_aqc_opc_nvm_cfg_write = 0x0705, 3474 ice_aqc_opc_nvm_checksum = 0x0706, 3475 ice_aqc_opc_nvm_write_activate = 0x0707, 3476 ice_aqc_opc_nvm_sr_dump = 0x0707, 3477 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 3478 ice_aqc_opc_nvm_update_empr = 0x0709, 3479 ice_aqc_opc_nvm_pkg_data = 0x070A, 3480 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 3481 ice_aqc_opc_nvm_sanitization = 0x070C, 3482 3483 /* PF/VF mailbox commands */ 3484 ice_mbx_opc_send_msg_to_pf = 0x0801, 3485 ice_mbx_opc_send_msg_to_vf = 0x0802, 3486 /* Alternate Structure Commands */ 3487 ice_aqc_opc_write_alt_direct = 0x0900, 3488 ice_aqc_opc_write_alt_indirect = 0x0901, 3489 ice_aqc_opc_read_alt_direct = 0x0902, 3490 ice_aqc_opc_read_alt_indirect = 0x0903, 3491 ice_aqc_opc_done_alt_write = 0x0904, 3492 ice_aqc_opc_clear_port_alt_write = 0x0906, 3493 /* LLDP commands */ 3494 ice_aqc_opc_lldp_get_mib = 0x0A00, 3495 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 3496 ice_aqc_opc_lldp_add_tlv = 0x0A02, 3497 ice_aqc_opc_lldp_update_tlv = 0x0A03, 3498 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 3499 ice_aqc_opc_lldp_stop = 0x0A05, 3500 ice_aqc_opc_lldp_start = 0x0A06, 3501 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3502 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3503 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3504 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3505 ice_execute_pending_lldp_mib = 0x0A0B, 3506 3507 /* RSS commands */ 3508 ice_aqc_opc_set_rss_key = 0x0B02, 3509 ice_aqc_opc_set_rss_lut = 0x0B03, 3510 ice_aqc_opc_get_rss_key = 0x0B04, 3511 ice_aqc_opc_get_rss_lut = 0x0B05, 3512 /* Sideband Control Interface commands */ 3513 ice_aqc_opc_neighbour_device_request = 0x0C00, 3514 3515 /* Tx queue handling commands/events */ 3516 ice_aqc_opc_add_txqs = 0x0C30, 3517 ice_aqc_opc_dis_txqs = 0x0C31, 3518 ice_aqc_opc_txqs_cleanup = 0x0C31, 3519 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3520 ice_aqc_opc_add_rdma_qset = 0x0C33, 3521 ice_aqc_opc_move_rdma_qset = 0x0C34, 3522 3523 /* package commands */ 3524 ice_aqc_opc_download_pkg = 0x0C40, 3525 ice_aqc_opc_upload_section = 0x0C41, 3526 ice_aqc_opc_update_pkg = 0x0C42, 3527 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3528 3529 ice_aqc_opc_driver_shared_params = 0x0C90, 3530 3531 /* Standalone Commands/Events */ 3532 ice_aqc_opc_event_lan_overflow = 0x1001, 3533 3534 /* debug commands */ 3535 ice_aqc_opc_debug_dump_internals = 0xFF08, 3536 3537 /* SystemDiagnostic commands */ 3538 ice_aqc_opc_set_health_status_config = 0xFF20, 3539 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3540 ice_aqc_opc_get_health_status = 0xFF22, 3541 ice_aqc_opc_clear_health_status = 0xFF23, 3542 3543 /* FW Logging Commands */ 3544 ice_aqc_opc_fw_logs_config = 0xFF30, 3545 ice_aqc_opc_fw_logs_register = 0xFF31, 3546 ice_aqc_opc_fw_logs_query = 0xFF32, 3547 ice_aqc_opc_fw_logs_event = 0xFF33, 3548 ice_aqc_opc_fw_logs_get = 0xFF34, 3549 ice_aqc_opc_fw_logs_clear = 0xFF35 3550 }; 3551 3552 #endif /* _ICE_ADMINQ_CMD_H_ */ 3553