1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2023, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ICE_ADMINQ_CMD_H_ 33 #define _ICE_ADMINQ_CMD_H_ 34 35 /* This header file defines the Admin Queue commands, error codes and 36 * descriptor format. It is shared between Firmware and Software. 37 */ 38 39 #include "ice_osdep.h" 40 #include "ice_defs.h" 41 #include "ice_bitops.h" 42 43 #define ICE_MAX_VSI 768 44 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 45 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 46 47 enum ice_aq_res_access_type { 48 ICE_RES_READ = 1, 49 ICE_RES_WRITE 50 }; 51 52 struct ice_aqc_generic { 53 __le32 param0; 54 __le32 param1; 55 __le32 addr_high; 56 __le32 addr_low; 57 }; 58 59 /* Get version (direct 0x0001) */ 60 struct ice_aqc_get_ver { 61 __le32 rom_ver; 62 __le32 fw_build; 63 u8 fw_branch; 64 u8 fw_major; 65 u8 fw_minor; 66 u8 fw_patch; 67 u8 api_branch; 68 u8 api_major; 69 u8 api_minor; 70 u8 api_patch; 71 }; 72 73 /* Send driver version (indirect 0x0002) */ 74 struct ice_aqc_driver_ver { 75 u8 major_ver; 76 u8 minor_ver; 77 u8 build_ver; 78 u8 subbuild_ver; 79 u8 reserved[4]; 80 __le32 addr_high; 81 __le32 addr_low; 82 }; 83 84 /* Queue Shutdown (direct 0x0003) */ 85 struct ice_aqc_q_shutdown { 86 u8 driver_unloading; 87 #define ICE_AQC_DRIVER_UNLOADING BIT(0) 88 u8 reserved[15]; 89 }; 90 91 /* Get Expanded Error Code (0x0005, direct) */ 92 struct ice_aqc_get_exp_err { 93 __le32 reason; 94 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF 95 __le32 identifier; 96 u8 rsvd[8]; 97 }; 98 99 /* Request resource ownership (direct 0x0008) 100 * Release resource ownership (direct 0x0009) 101 */ 102 struct ice_aqc_req_res { 103 __le16 res_id; 104 #define ICE_AQC_RES_ID_NVM 1 105 #define ICE_AQC_RES_ID_SDP 2 106 #define ICE_AQC_RES_ID_CHNG_LOCK 3 107 #define ICE_AQC_RES_ID_GLBL_LOCK 4 108 __le16 access_type; 109 #define ICE_AQC_RES_ACCESS_READ 1 110 #define ICE_AQC_RES_ACCESS_WRITE 2 111 112 /* Upon successful completion, FW writes this value and driver is 113 * expected to release resource before timeout. This value is provided 114 * in milliseconds. 115 */ 116 __le32 timeout; 117 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 118 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 119 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 120 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 121 /* For SDP: pin ID of the SDP */ 122 __le32 res_number; 123 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ 124 __le16 status; 125 #define ICE_AQ_RES_GLBL_SUCCESS 0 126 #define ICE_AQ_RES_GLBL_IN_PROG 1 127 #define ICE_AQ_RES_GLBL_DONE 2 128 u8 reserved[2]; 129 }; 130 131 /* Get function capabilities (indirect 0x000A) 132 * Get device capabilities (indirect 0x000B) 133 */ 134 struct ice_aqc_list_caps { 135 u8 cmd_flags; 136 u8 pf_index; 137 u8 reserved[2]; 138 __le32 count; 139 __le32 addr_high; 140 __le32 addr_low; 141 }; 142 143 /* Device/Function buffer entry, repeated per reported capability */ 144 struct ice_aqc_list_caps_elem { 145 __le16 cap; 146 #define ICE_AQC_CAPS_SWITCHING_MODE 0x0001 147 #define ICE_AQC_CAPS_MANAGEABILITY_MODE 0x0002 148 #define ICE_AQC_CAPS_OS2BMC 0x0004 149 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005 150 #define ICE_AQC_MAX_VALID_FUNCTIONS 0x8 151 #define ICE_AQC_CAPS_ALTERNATE_RAM 0x0006 152 #define ICE_AQC_CAPS_WOL_PROXY 0x0008 153 #define ICE_AQC_CAPS_SRIOV 0x0012 154 #define ICE_AQC_CAPS_VF 0x0013 155 #define ICE_AQC_CAPS_802_1QBG 0x0015 156 #define ICE_AQC_CAPS_802_1BR 0x0016 157 #define ICE_AQC_CAPS_VSI 0x0017 158 #define ICE_AQC_CAPS_DCB 0x0018 159 #define ICE_AQC_CAPS_RSVD 0x0021 160 #define ICE_AQC_CAPS_ISCSI 0x0022 161 #define ICE_AQC_CAPS_RSS 0x0040 162 #define ICE_AQC_CAPS_RXQS 0x0041 163 #define ICE_AQC_CAPS_TXQS 0x0042 164 #define ICE_AQC_CAPS_MSIX 0x0043 165 #define ICE_AQC_CAPS_MAX_MTU 0x0047 166 #define ICE_AQC_CAPS_CEM 0x00F2 167 #define ICE_AQC_CAPS_IWARP 0x0051 168 #define ICE_AQC_CAPS_LED 0x0061 169 #define ICE_AQC_CAPS_SDP 0x0062 170 #define ICE_AQC_CAPS_WR_CSR_PROT 0x0064 171 #define ICE_AQC_CAPS_SENSOR_READING 0x0067 172 #define ICE_AQC_CAPS_LOGI_TO_PHYSI_PORT_MAP 0x0073 173 #define ICE_AQC_CAPS_SKU 0x0074 174 #define ICE_AQC_CAPS_PORT_MAP 0x0075 175 #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 176 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 177 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 178 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081 179 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082 180 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083 181 #define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084 182 #define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085 183 #define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087 184 #define ICE_AQC_CAPS_DYN_FLATTENING 0x008A 185 #define ICE_AQC_CAPS_OROM_RECOVERY_UPDATE 0x0090 186 #define ICE_AQC_CAPS_ROCEV2_LAG 0x0092 187 188 u8 major_ver; 189 u8 minor_ver; 190 /* Number of resources described by this capability */ 191 __le32 number; 192 /* Only meaningful for some types of resources */ 193 __le32 logical_id; 194 /* Only meaningful for some types of resources */ 195 __le32 phys_id; 196 __le64 rsvd1; 197 __le64 rsvd2; 198 }; 199 200 /* Manage MAC address, read command - indirect (0x0107) 201 * This struct is also used for the response 202 */ 203 struct ice_aqc_manage_mac_read { 204 __le16 flags; /* Zeroed by device driver */ 205 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) 206 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) 207 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) 208 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) 209 #define ICE_AQC_MAN_MAC_MC_MAG_EN BIT(8) 210 #define ICE_AQC_MAN_MAC_WOL_PRESERVE_ON_PFR BIT(9) 211 #define ICE_AQC_MAN_MAC_READ_S 4 212 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) 213 u8 rsvd[2]; 214 u8 num_addr; /* Used in response */ 215 u8 rsvd1[3]; 216 __le32 addr_high; 217 __le32 addr_low; 218 }; 219 220 /* Response buffer format for manage MAC read command */ 221 struct ice_aqc_manage_mac_read_resp { 222 u8 lport_num; 223 u8 addr_type; 224 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 225 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 226 u8 mac_addr[ETH_ALEN]; 227 }; 228 229 /* Manage MAC address, write command - direct (0x0108) */ 230 struct ice_aqc_manage_mac_write { 231 u8 rsvd; 232 u8 flags; 233 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0) 234 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1) 235 #define ICE_AQC_MAN_MAC_WR_S 6 236 #define ICE_AQC_MAN_MAC_WR_M MAKEMASK(3, ICE_AQC_MAN_MAC_WR_S) 237 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0 238 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S) 239 /* byte stream in network order */ 240 u8 mac_addr[ETH_ALEN]; 241 __le32 addr_high; 242 __le32 addr_low; 243 }; 244 245 /* Clear PXE Command and response (direct 0x0110) */ 246 struct ice_aqc_clear_pxe { 247 u8 rx_cnt; 248 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 249 u8 reserved[15]; 250 }; 251 252 /* Configure No-Drop Policy Command (direct 0x0112) */ 253 struct ice_aqc_config_no_drop_policy { 254 u8 opts; 255 #define ICE_AQC_FORCE_NO_DROP BIT(0) 256 u8 rsvd[15]; 257 }; 258 259 /* Get switch configuration (0x0200) */ 260 struct ice_aqc_get_sw_cfg { 261 /* Reserved for command and copy of request flags for response */ 262 __le16 flags; 263 /* First desc in case of command and next_elem in case of response 264 * In case of response, if it is not zero, means all the configuration 265 * was not returned and new command shall be sent with this value in 266 * the 'first desc' field 267 */ 268 __le16 element; 269 /* Reserved for command, only used for response */ 270 __le16 num_elems; 271 __le16 rsvd; 272 __le32 addr_high; 273 __le32 addr_low; 274 }; 275 276 /* Each entry in the response buffer is of the following type: */ 277 struct ice_aqc_get_sw_cfg_resp_elem { 278 /* VSI/Port Number */ 279 __le16 vsi_port_num; 280 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 281 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ 282 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) 283 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 284 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) 285 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 286 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 287 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 288 289 /* SWID VSI/Port belongs to */ 290 __le16 swid; 291 292 /* Bit 14..0 : PF/VF number VSI belongs to 293 * Bit 15 : VF indication bit 294 */ 295 __le16 pf_vf_num; 296 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 297 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ 298 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) 299 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) 300 }; 301 302 /* Set Port parameters, (direct, 0x0203) */ 303 struct ice_aqc_set_port_params { 304 __le16 cmd_flags; 305 #define ICE_AQC_SET_P_PARAMS_SAVE_BAD_PACKETS BIT(0) 306 #define ICE_AQC_SET_P_PARAMS_PAD_SHORT_PACKETS BIT(1) 307 #define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2) 308 __le16 bad_frame_vsi; 309 #define ICE_AQC_SET_P_PARAMS_VSI_S 0 310 #define ICE_AQC_SET_P_PARAMS_VSI_M (0x3FF << ICE_AQC_SET_P_PARAMS_VSI_S) 311 #define ICE_AQC_SET_P_PARAMS_VSI_VALID BIT(15) 312 __le16 swid; 313 #define ICE_AQC_SET_P_PARAMS_SWID_S 0 314 #define ICE_AQC_SET_P_PARAMS_SWID_M (0xFF << ICE_AQC_SET_P_PARAMS_SWID_S) 315 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S 8 316 #define ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_M \ 317 (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) 318 #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) 319 #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) 320 u8 reserved[10]; 321 }; 322 323 /* These resource type defines are used for all switch resource 324 * commands where a resource type is required, such as: 325 * Get Resource Allocation command (indirect 0x0204) 326 * Allocate Resources command (indirect 0x0208) 327 * Free Resources command (indirect 0x0209) 328 * Get Allocated Resource Descriptors Command (indirect 0x020A) 329 */ 330 #define ICE_AQC_RES_TYPE_VEB_COUNTER 0x00 331 #define ICE_AQC_RES_TYPE_VLAN_COUNTER 0x01 332 #define ICE_AQC_RES_TYPE_MIRROR_RULE 0x02 333 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 334 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 335 #define ICE_AQC_RES_TYPE_RECIPE 0x05 336 #define ICE_AQC_RES_TYPE_PROFILE 0x06 337 #define ICE_AQC_RES_TYPE_SWID 0x07 338 #define ICE_AQC_RES_TYPE_VSI 0x08 339 #define ICE_AQC_RES_TYPE_FLU 0x09 340 #define ICE_AQC_RES_TYPE_WIDE_TABLE_1 0x0A 341 #define ICE_AQC_RES_TYPE_WIDE_TABLE_2 0x0B 342 #define ICE_AQC_RES_TYPE_WIDE_TABLE_4 0x0C 343 #define ICE_AQC_RES_TYPE_GLOBAL_RSS_HASH 0x20 344 #define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21 345 #define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22 346 #define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23 347 #define ICE_AQC_RES_TYPE_FLEX_DESC_PROG 0x30 348 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_PROFID 0x48 349 #define ICE_AQC_RES_TYPE_SWITCH_PROF_BLDR_TCAM 0x49 350 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_PROFID 0x50 351 #define ICE_AQC_RES_TYPE_ACL_PROF_BLDR_TCAM 0x51 352 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60 353 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61 354 /* Resource types 0x62-67 are reserved for Hash profile builder */ 355 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_PROFID 0x68 356 #define ICE_AQC_RES_TYPE_QHASH_PROF_BLDR_TCAM 0x69 357 358 #define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7) 359 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12) 360 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13) 361 362 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00 363 364 #define ICE_AQC_RES_TYPE_S 0 365 #define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S) 366 367 /* Get Resource Allocation command (indirect 0x0204) */ 368 struct ice_aqc_get_res_alloc { 369 __le16 resp_elem_num; /* Used in response, reserved in command */ 370 u8 reserved[6]; 371 __le32 addr_high; 372 __le32 addr_low; 373 }; 374 375 /* Get Resource Allocation Response Buffer per response */ 376 struct ice_aqc_get_res_resp_elem { 377 __le16 res_type; /* Types defined above cmd 0x0204 */ 378 __le16 total_capacity; /* Resources available to all PF's */ 379 __le16 total_function; /* Resources allocated for a PF */ 380 __le16 total_shared; /* Resources allocated as shared */ 381 __le16 total_free; /* Resources un-allocated/not reserved by any PF */ 382 }; 383 384 /* Allocate Resources command (indirect 0x0208) 385 * Free Resources command (indirect 0x0209) 386 */ 387 struct ice_aqc_alloc_free_res_cmd { 388 __le16 num_entries; /* Number of Resource entries */ 389 u8 reserved[6]; 390 __le32 addr_high; 391 __le32 addr_low; 392 }; 393 394 /* Resource descriptor */ 395 struct ice_aqc_res_elem { 396 union { 397 __le16 sw_resp; 398 __le16 flu_resp; 399 } e; 400 }; 401 402 /* Buffer for Allocate/Free Resources commands */ 403 struct ice_aqc_alloc_free_res_elem { 404 __le16 res_type; /* Types defined above cmd 0x0204 */ 405 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 406 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ 407 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) 408 __le16 num_elems; 409 struct ice_aqc_res_elem elem[STRUCT_HACK_VAR_LEN]; 410 }; 411 412 /* Get Allocated Resource Descriptors Command (indirect 0x020A) */ 413 struct ice_aqc_get_allocd_res_desc { 414 union { 415 struct { 416 __le16 res; /* Types defined above cmd 0x0204 */ 417 __le16 first_desc; 418 __le32 reserved; 419 } cmd; 420 struct { 421 __le16 res; 422 __le16 next_desc; 423 __le16 num_desc; 424 __le16 reserved; 425 } resp; 426 } ops; 427 __le32 addr_high; 428 __le32 addr_low; 429 }; 430 431 /* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */ 432 struct ice_aqc_set_vlan_mode { 433 u8 reserved; 434 u8 l2tag_prio_tagging; 435 #define ICE_AQ_VLAN_PRIO_TAG_S 0 436 #define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S) 437 #define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0 438 #define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1 439 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2 440 #define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3 441 #define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4 442 #define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4 443 #define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7 444 u8 l2tag_reserved[64]; 445 u8 rdma_packet; 446 #define ICE_AQ_VLAN_RDMA_TAG_S 0 447 #define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S) 448 #define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10 449 #define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A 450 u8 rdma_reserved[2]; 451 u8 mng_vlan_prot_id; 452 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10 453 #define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11 454 u8 prot_id_reserved[30]; 455 }; 456 457 /* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */ 458 struct ice_aqc_get_vlan_mode { 459 u8 vlan_mode; 460 #define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0) 461 u8 l2tag_prio_tagging; 462 u8 reserved[98]; 463 }; 464 465 /* Add VSI (indirect 0x0210) 466 * Update VSI (indirect 0x0211) 467 * Get VSI (indirect 0x0212) 468 * Free VSI (indirect 0x0213) 469 */ 470 struct ice_aqc_add_get_update_free_vsi { 471 __le16 vsi_num; 472 #define ICE_AQ_VSI_NUM_S 0 473 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) 474 #define ICE_AQ_VSI_IS_VALID BIT(15) 475 __le16 cmd_flags; 476 #define ICE_AQ_VSI_KEEP_ALLOC 0x1 477 u8 vf_id; 478 u8 reserved; 479 __le16 vsi_flags; 480 #define ICE_AQ_VSI_TYPE_S 0 481 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) 482 #define ICE_AQ_VSI_TYPE_VF 0x0 483 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 484 #define ICE_AQ_VSI_TYPE_PF 0x2 485 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 486 __le32 addr_high; 487 __le32 addr_low; 488 }; 489 490 /* Response descriptor for: 491 * Add VSI (indirect 0x0210) 492 * Update VSI (indirect 0x0211) 493 * Free VSI (indirect 0x0213) 494 */ 495 struct ice_aqc_add_update_free_vsi_resp { 496 __le16 vsi_num; 497 __le16 ext_status; 498 __le16 vsi_used; 499 __le16 vsi_free; 500 __le32 addr_high; 501 __le32 addr_low; 502 }; 503 504 struct ice_aqc_get_vsi_resp { 505 __le16 vsi_num; 506 u8 vf_id; 507 /* The vsi_flags field uses the ICE_AQ_VSI_TYPE_* defines for values. 508 * These are found above in struct ice_aqc_add_get_update_free_vsi. 509 */ 510 u8 vsi_flags; 511 __le16 vsi_used; 512 __le16 vsi_free; 513 __le32 addr_high; 514 __le32 addr_low; 515 }; 516 517 struct ice_aqc_vsi_props { 518 __le16 valid_sections; 519 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) 520 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) 521 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) 522 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) 523 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) 524 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) 525 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) 526 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) 527 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) 528 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) 529 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) 530 /* switch section */ 531 u8 sw_id; 532 u8 sw_flags; 533 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) 534 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) 535 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) 536 u8 sw_flags2; 537 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 538 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) 539 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) 540 #define ICE_AQ_VSI_SW_FLAG_RX_PASS_PRUNE_ENA BIT(3) 541 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) 542 u8 veb_stat_id; 543 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 544 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) 545 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) 546 /* security section */ 547 u8 sec_flags; 548 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) 549 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) 550 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 551 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) 552 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) 553 u8 sec_reserved; 554 /* VLAN section */ 555 __le16 port_based_inner_vlan; /* VLANS include priority bits */ 556 u8 inner_vlan_reserved[2]; 557 u8 inner_vlan_flags; 558 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0 559 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S) 560 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 561 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 562 #define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3 563 #define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2) 564 #define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3 565 #define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 566 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 567 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 568 #define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 569 #define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S) 570 #define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5) 571 u8 inner_vlan_reserved2[3]; 572 /* ingress egress up sections */ 573 __le32 ingress_table; /* bitmap, 3 bits per up */ 574 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 575 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) 576 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 577 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) 578 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 579 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) 580 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 581 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) 582 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 583 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) 584 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 585 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) 586 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 587 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) 588 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 589 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) 590 __le32 egress_table; /* same defines as for ingress table */ 591 /* outer tags section */ 592 __le16 port_based_outer_vlan; 593 u8 outer_vlan_flags; 594 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0 595 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S) 596 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0 597 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1 598 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2 599 #define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3 600 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 601 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) 602 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 603 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 604 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 605 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 606 #define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4) 607 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5 608 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) 609 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1 610 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2 611 #define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3 612 #define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7) 613 u8 outer_vlan_reserved; 614 /* queue mapping section */ 615 __le16 mapping_flags; 616 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 617 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) 618 __le16 q_mapping[16]; 619 #define ICE_AQ_VSI_Q_S 0 620 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) 621 __le16 tc_mapping[8]; 622 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 623 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) 624 #define ICE_AQ_VSI_TC_Q_NUM_S 11 625 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) 626 /* queueing option section */ 627 u8 q_opt_rss; 628 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 629 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) 630 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 631 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 632 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 633 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 634 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) 635 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 636 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 637 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 638 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 639 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 640 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) 641 u8 q_opt_tc; 642 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 643 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) 644 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) 645 u8 q_opt_flags; 646 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) 647 u8 q_opt_reserved[3]; 648 /* outer up section */ 649 __le32 outer_up_table; /* same structure and defines as ingress tbl */ 650 /* section 10 */ 651 __le16 sect_10_reserved; 652 /* flow director section */ 653 __le16 fd_options; 654 #define ICE_AQ_VSI_FD_ENABLE BIT(0) 655 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) 656 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) 657 __le16 max_fd_fltr_dedicated; 658 __le16 max_fd_fltr_shared; 659 __le16 fd_def_q; 660 #define ICE_AQ_VSI_FD_DEF_Q_S 0 661 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) 662 #define ICE_AQ_VSI_FD_DEF_GRP_S 12 663 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) 664 __le16 fd_report_opt; 665 #define ICE_AQ_VSI_FD_REPORT_Q_S 0 666 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) 667 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 668 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) 669 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) 670 /* PASID section */ 671 __le32 pasid_id; 672 #define ICE_AQ_VSI_PASID_ID_S 0 673 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) 674 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) 675 u8 reserved[24]; 676 }; 677 678 /* Add/update mirror rule - direct (0x0260) */ 679 #define ICE_AQC_RULE_ID_VALID_S 7 680 #define ICE_AQC_RULE_ID_VALID_M (0x1 << ICE_AQC_RULE_ID_VALID_S) 681 #define ICE_AQC_RULE_ID_S 0 682 #define ICE_AQC_RULE_ID_M (0x3F << ICE_AQC_RULE_ID_S) 683 684 /* Following defines to be used while processing caller specified mirror list 685 * of VSI indexes. 686 */ 687 /* Action: Byte.bit (1.7) 688 * 0 = Remove VSI from mirror rule 689 * 1 = Add VSI to mirror rule 690 */ 691 #define ICE_AQC_RULE_ACT_S 15 692 #define ICE_AQC_RULE_ACT_M (0x1 << ICE_AQC_RULE_ACT_S) 693 /* Action: 1.2:0.0 = Mirrored VSI */ 694 #define ICE_AQC_RULE_MIRRORED_VSI_S 0 695 #define ICE_AQC_RULE_MIRRORED_VSI_M (0x7FF << ICE_AQC_RULE_MIRRORED_VSI_S) 696 697 /* This is to be used by add/update mirror rule Admin Queue command. 698 * In case of add mirror rule - if rule ID is specified as 699 * INVAL_MIRROR_RULE_ID, new rule ID is allocated from shared pool. 700 * If specified rule_id is valid, then it is used. If specified rule_id 701 * is in use then new mirroring rule is added. 702 */ 703 #define ICE_INVAL_MIRROR_RULE_ID 0xFFFF 704 705 struct ice_aqc_add_update_mir_rule { 706 __le16 rule_id; 707 708 __le16 rule_type; 709 #define ICE_AQC_RULE_TYPE_S 0 710 #define ICE_AQC_RULE_TYPE_M (0x7 << ICE_AQC_RULE_TYPE_S) 711 /* VPORT ingress/egress */ 712 #define ICE_AQC_RULE_TYPE_VPORT_INGRESS 0x1 713 #define ICE_AQC_RULE_TYPE_VPORT_EGRESS 0x2 714 /* Physical port ingress mirroring. 715 * All traffic received by this port 716 */ 717 #define ICE_AQC_RULE_TYPE_PPORT_INGRESS 0x6 718 /* Physical port egress mirroring. All traffic sent by this port */ 719 #define ICE_AQC_RULE_TYPE_PPORT_EGRESS 0x7 720 721 /* Number of mirrored entries. 722 * The values are in the command buffer 723 */ 724 __le16 num_entries; 725 726 /* Destination VSI */ 727 __le16 dest; 728 __le32 addr_high; 729 __le32 addr_low; 730 }; 731 732 /* Delete mirror rule - direct(0x0261) */ 733 struct ice_aqc_delete_mir_rule { 734 __le16 rule_id; 735 __le16 rsvd; 736 737 /* Byte.bit: 20.0 = Keep allocation. If set VSI stays part of 738 * the PF allocated resources, otherwise it is returned to the 739 * shared pool 740 */ 741 #define ICE_AQC_FLAG_KEEP_ALLOCD_S 0 742 #define ICE_AQC_FLAG_KEEP_ALLOCD_M (0x1 << ICE_AQC_FLAG_KEEP_ALLOCD_S) 743 __le16 flags; 744 745 u8 reserved[10]; 746 }; 747 748 /* Set/Get storm config - (direct 0x0280, 0x0281) */ 749 /* This structure holds get storm configuration response and same structure 750 * is used to perform set_storm_cfg 751 */ 752 struct ice_aqc_storm_cfg { 753 __le32 bcast_thresh_size; 754 __le32 mcast_thresh_size; 755 /* Bit 18:0 - Traffic upper threshold size 756 * Bit 31:19 - Reserved 757 */ 758 #define ICE_AQ_THRESHOLD_S 0 759 #define ICE_AQ_THRESHOLD_M (0x7FFFF << ICE_AQ_THRESHOLD_S) 760 761 __le32 storm_ctrl_ctrl; 762 /* Bit 0: MDIPW - Drop Multicast packets in previous window 763 * Bit 1: MDICW - Drop multicast packets in current window 764 * Bit 2: BDIPW - Drop broadcast packets in previous window 765 * Bit 3: BDICW - Drop broadcast packets in current window 766 */ 767 #define ICE_AQ_STORM_CTRL_MDIPW_DROP_MULTICAST BIT(0) 768 #define ICE_AQ_STORM_CTRL_MDICW_DROP_MULTICAST BIT(1) 769 #define ICE_AQ_STORM_CTRL_BDIPW_DROP_MULTICAST BIT(2) 770 #define ICE_AQ_STORM_CTRL_BDICW_DROP_MULTICAST BIT(3) 771 /* Bit 7:5 : Reserved */ 772 /* Bit 27:8 : Interval - BSC/MSC Time-interval specification: The 773 * interval size for applying ingress broadcast or multicast storm 774 * control. 775 */ 776 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S 8 777 #define ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_M \ 778 (0xFFFFF << ICE_AQ_STORM_BSC_MSC_TIME_INTERVAL_S) 779 __le32 reserved; 780 }; 781 782 #define ICE_MAX_NUM_RECIPES 64 783 784 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) 785 */ 786 struct ice_aqc_sw_rules { 787 /* ops: add switch rules, referring the number of rules. 788 * ops: update switch rules, referring the number of filters 789 * ops: remove switch rules, referring the entry index. 790 * ops: get switch rules, referring to the number of filters. 791 */ 792 __le16 num_rules_fltr_entry_index; 793 u8 reserved[6]; 794 __le32 addr_high; 795 __le32 addr_low; 796 }; 797 798 /* Add switch rule response: 799 * Content of return buffer is same as the input buffer. The status field and 800 * LUT index are updated as part of the response 801 */ 802 struct ice_aqc_sw_rules_elem_hdr { 803 __le16 type; /* Switch rule type, one of T_... */ 804 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 805 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 806 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 807 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 808 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 809 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 810 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 811 __le16 status; 812 }; 813 814 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry 815 * This structures describes the lookup rules and associated actions. "index" 816 * is returned as part of a response to a successful Add command, and can be 817 * used to identify the rule for Update/Get/Remove commands. 818 */ 819 struct ice_sw_rule_lkup_rx_tx { 820 struct ice_aqc_sw_rules_elem_hdr hdr; 821 822 __le16 recipe_id; 823 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 824 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ 825 __le16 src; 826 __le32 act; 827 828 /* Bit 0:1 - Action type */ 829 #define ICE_SINGLE_ACT_TYPE_S 0x00 830 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) 831 832 /* Bit 2 - Loop back enable 833 * Bit 3 - LAN enable 834 */ 835 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) 836 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) 837 838 /* Action type = 0 - Forward to VSI or VSI list */ 839 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 840 841 #define ICE_SINGLE_ACT_VSI_ID_S 4 842 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) 843 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 844 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) 845 /* This bit needs to be set if action is forward to VSI list */ 846 #define ICE_SINGLE_ACT_VSI_LIST BIT(14) 847 #define ICE_SINGLE_ACT_VALID_BIT BIT(17) 848 #define ICE_SINGLE_ACT_DROP BIT(18) 849 850 /* Action type = 1 - Forward to Queue of Queue group */ 851 #define ICE_SINGLE_ACT_TO_Q 0x1 852 #define ICE_SINGLE_ACT_Q_INDEX_S 4 853 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) 854 #define ICE_SINGLE_ACT_Q_REGION_S 15 855 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) 856 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) 857 858 /* Action type = 2 - Prune */ 859 #define ICE_SINGLE_ACT_PRUNE 0x2 860 #define ICE_SINGLE_ACT_EGRESS BIT(15) 861 #define ICE_SINGLE_ACT_INGRESS BIT(16) 862 #define ICE_SINGLE_ACT_PRUNET BIT(17) 863 /* Bit 18 should be set to 0 for this action */ 864 865 /* Action type = 2 - Pointer */ 866 #define ICE_SINGLE_ACT_PTR 0x2 867 #define ICE_SINGLE_ACT_PTR_VAL_S 4 868 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) 869 /* Bit 17 should be set if pointed action includes a FWD cmd */ 870 #define ICE_SINGLE_ACT_PTR_HAS_FWD BIT(17) 871 /* Bit 18 should be set to 1 */ 872 #define ICE_SINGLE_ACT_PTR_BIT BIT(18) 873 874 /* Action type = 3 - Other actions. Last two bits 875 * are other action identifier 876 */ 877 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 878 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 879 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ 880 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) 881 882 /* Bit 17:18 - Defines other actions */ 883 /* Other action = 0 - Mirror VSI */ 884 #define ICE_SINGLE_OTHER_ACT_MIRROR 0 885 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 886 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ 887 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) 888 889 /* Other action = 3 - Set Stat count */ 890 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 891 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 892 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ 893 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) 894 895 __le16 index; /* The index of the rule in the lookup table */ 896 /* Length and values of the header to be matched per recipe or 897 * lookup-type 898 */ 899 __le16 hdr_len; 900 u8 hdr_data[STRUCT_HACK_VAR_LEN]; 901 }; 902 903 #pragma pack(1) 904 /* Add/Update/Remove large action command/response entry 905 * "index" is returned as part of a response to a successful Add command, and 906 * can be used to identify the action for Update/Get/Remove commands. 907 */ 908 struct ice_sw_rule_lg_act { 909 struct ice_aqc_sw_rules_elem_hdr hdr; 910 911 __le16 index; /* Index in large action table */ 912 __le16 size; 913 /* Max number of large actions */ 914 #define ICE_MAX_LG_ACT 4 915 /* Bit 0:1 - Action type */ 916 #define ICE_LG_ACT_TYPE_S 0 917 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) 918 919 /* Action type = 0 - Forward to VSI or VSI list */ 920 #define ICE_LG_ACT_VSI_FORWARDING 0 921 #define ICE_LG_ACT_VSI_ID_S 3 922 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) 923 #define ICE_LG_ACT_VSI_LIST_ID_S 3 924 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) 925 /* This bit needs to be set if action is forward to VSI list */ 926 #define ICE_LG_ACT_VSI_LIST BIT(13) 927 928 #define ICE_LG_ACT_VALID_BIT BIT(16) 929 930 /* Action type = 1 - Forward to Queue of Queue group */ 931 #define ICE_LG_ACT_TO_Q 0x1 932 #define ICE_LG_ACT_Q_INDEX_S 3 933 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) 934 #define ICE_LG_ACT_Q_REGION_S 14 935 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) 936 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) 937 938 /* Action type = 2 - Prune */ 939 #define ICE_LG_ACT_PRUNE 0x2 940 #define ICE_LG_ACT_EGRESS BIT(14) 941 #define ICE_LG_ACT_INGRESS BIT(15) 942 #define ICE_LG_ACT_PRUNET BIT(16) 943 944 /* Action type = 3 - Mirror VSI */ 945 #define ICE_LG_OTHER_ACT_MIRROR 0x3 946 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 947 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) 948 949 /* Action type = 5 - Generic Value */ 950 #define ICE_LG_ACT_GENERIC 0x5 951 #define ICE_LG_ACT_GENERIC_VALUE_S 3 952 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) 953 #define ICE_LG_ACT_GENERIC_OFFSET_S 19 954 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) 955 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 956 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) 957 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7 958 959 /* Action = 7 - Set Stat count */ 960 #define ICE_LG_ACT_STAT_COUNT 0x7 961 #define ICE_LG_ACT_STAT_COUNT_S 3 962 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) 963 __le32 act[STRUCT_HACK_VAR_LEN]; /* array of size for actions */ 964 }; 965 #pragma pack() 966 967 #pragma pack(1) 968 /* Add/Update/Remove VSI list command/response entry 969 * "index" is returned as part of a response to a successful Add command, and 970 * can be used to identify the VSI list for Update/Get/Remove commands. 971 */ 972 struct ice_sw_rule_vsi_list { 973 struct ice_aqc_sw_rules_elem_hdr hdr; 974 975 __le16 index; /* Index of VSI/Prune list */ 976 __le16 number_vsi; 977 __le16 vsi[STRUCT_HACK_VAR_LEN]; /* Array of number_vsi VSI numbers */ 978 }; 979 #pragma pack() 980 981 #pragma pack(1) 982 /* Query VSI list command/response entry */ 983 struct ice_sw_rule_vsi_list_query { 984 __le16 index; 985 u8 vsi_list[DIVIDE_AND_ROUND_UP(ICE_MAX_VSI, BITS_PER_BYTE)]; 986 }; 987 #pragma pack() 988 989 /* PFC Ignore (direct 0x0301) 990 * The command and response use the same descriptor structure 991 */ 992 struct ice_aqc_pfc_ignore { 993 u8 tc_bitmap; 994 u8 cmd_flags; /* unused in response */ 995 #define ICE_AQC_PFC_IGNORE_SET BIT(7) 996 #define ICE_AQC_PFC_IGNORE_CLEAR 0 997 u8 reserved[14]; 998 }; 999 1000 /* Query PFC Mode (direct 0x0302) 1001 * Set PFC Mode (direct 0x0303) 1002 */ 1003 struct ice_aqc_set_query_pfc_mode { 1004 u8 pfc_mode; 1005 /* For Set Command response, reserved in all other cases */ 1006 #define ICE_AQC_PFC_NOT_CONFIGURED 0 1007 /* For Query Command response, reserved in all other cases */ 1008 #define ICE_AQC_DCB_DIS 0 1009 #define ICE_AQC_PFC_VLAN_BASED_PFC 1 1010 #define ICE_AQC_PFC_DSCP_BASED_PFC 2 1011 u8 rsvd[15]; 1012 }; 1013 1014 /* Set DCB Parameters (direct 0x0306) */ 1015 struct ice_aqc_set_dcb_params { 1016 u8 cmd_flags; /* unused in response */ 1017 #define ICE_AQC_LINK_UP_DCB_CFG BIT(0) 1018 #define ICE_AQC_PERSIST_DCB_CFG BIT(1) 1019 u8 valid_flags; /* unused in response */ 1020 #define ICE_AQC_LINK_UP_DCB_CFG_VALID BIT(0) 1021 #define ICE_AQC_PERSIST_DCB_CFG_VALID BIT(1) 1022 u8 rsvd[14]; 1023 }; 1024 1025 /* Get Default Topology (indirect 0x0400) */ 1026 struct ice_aqc_get_topo { 1027 u8 port_num; 1028 u8 num_branches; 1029 __le16 reserved1; 1030 __le32 reserved2; 1031 __le32 addr_high; 1032 __le32 addr_low; 1033 }; 1034 1035 /* Get/Set Tx Topology (indirect 0x0418/0x0417) */ 1036 struct ice_aqc_get_set_tx_topo { 1037 u8 set_flags; 1038 #define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0) 1039 #define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1) 1040 #define ICE_AQC_TX_TOPO_FLAGS_SET_PSM BIT(2) 1041 #define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4) 1042 #define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5) 1043 u8 get_flags; 1044 #define ICE_AQC_TX_TOPO_GET_NO_UPDATE 0 1045 #define ICE_AQC_TX_TOPO_GET_PSM 1 1046 #define ICE_AQC_TX_TOPO_GET_RAM 2 1047 __le16 reserved1; 1048 __le32 reserved2; 1049 __le32 addr_high; 1050 __le32 addr_low; 1051 }; 1052 1053 /* Update TSE (indirect 0x0403) 1054 * Get TSE (indirect 0x0404) 1055 * Add TSE (indirect 0x0401) 1056 * Delete TSE (indirect 0x040F) 1057 * Move TSE (indirect 0x0408) 1058 * Suspend Nodes (indirect 0x0409) 1059 * Resume Nodes (indirect 0x040A) 1060 */ 1061 struct ice_aqc_sched_elem_cmd { 1062 __le16 num_elem_req; /* Used by commands */ 1063 __le16 num_elem_resp; /* Used by responses */ 1064 __le32 reserved; 1065 __le32 addr_high; 1066 __le32 addr_low; 1067 }; 1068 1069 struct ice_aqc_txsched_move_grp_info_hdr { 1070 __le32 src_parent_teid; 1071 __le32 dest_parent_teid; 1072 __le16 num_elems; 1073 u8 flags; 1074 u8 reserved; 1075 }; 1076 1077 struct ice_aqc_move_elem { 1078 struct ice_aqc_txsched_move_grp_info_hdr hdr; 1079 __le32 teid[STRUCT_HACK_VAR_LEN]; 1080 }; 1081 1082 struct ice_aqc_elem_info_bw { 1083 __le16 bw_profile_idx; 1084 __le16 bw_alloc; 1085 }; 1086 1087 struct ice_aqc_txsched_elem { 1088 u8 elem_type; /* Special field, reserved for some aq calls */ 1089 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 1090 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 1091 #define ICE_AQC_ELEM_TYPE_TC 0x2 1092 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 1093 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 1094 #define ICE_AQC_ELEM_TYPE_LEAF 0x5 1095 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 1096 u8 valid_sections; 1097 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) 1098 #define ICE_AQC_ELEM_VALID_CIR BIT(1) 1099 #define ICE_AQC_ELEM_VALID_EIR BIT(2) 1100 #define ICE_AQC_ELEM_VALID_SHARED BIT(3) 1101 u8 generic; 1102 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 1103 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 1104 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) 1105 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 1106 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) 1107 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 1108 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ 1109 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) 1110 u8 flags; /* Special field, reserved for some aq calls */ 1111 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 1112 struct ice_aqc_elem_info_bw cir_bw; 1113 struct ice_aqc_elem_info_bw eir_bw; 1114 __le16 srl_id; 1115 __le16 reserved2; 1116 }; 1117 1118 struct ice_aqc_txsched_elem_data { 1119 __le32 parent_teid; 1120 __le32 node_teid; 1121 struct ice_aqc_txsched_elem data; 1122 }; 1123 1124 struct ice_aqc_txsched_topo_grp_info_hdr { 1125 __le32 parent_teid; 1126 __le16 num_elems; 1127 __le16 reserved2; 1128 }; 1129 1130 struct ice_aqc_add_elem { 1131 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1132 struct ice_aqc_txsched_elem_data generic[STRUCT_HACK_VAR_LEN]; 1133 }; 1134 1135 struct ice_aqc_get_topo_elem { 1136 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1137 struct ice_aqc_txsched_elem_data 1138 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1139 }; 1140 1141 struct ice_aqc_delete_elem { 1142 struct ice_aqc_txsched_topo_grp_info_hdr hdr; 1143 __le32 teid[STRUCT_HACK_VAR_LEN]; 1144 }; 1145 1146 /* Query Port ETS (indirect 0x040E) 1147 * 1148 * This indirect command is used to query port TC node configuration. 1149 */ 1150 struct ice_aqc_query_port_ets { 1151 __le32 port_teid; 1152 __le32 reserved; 1153 __le32 addr_high; 1154 __le32 addr_low; 1155 }; 1156 1157 struct ice_aqc_port_ets_elem { 1158 u8 tc_valid_bits; 1159 u8 reserved[3]; 1160 /* 3 bits for UP per TC 0-7, 4th byte reserved */ 1161 __le32 up2tc; 1162 u8 tc_bw_share[8]; 1163 __le32 port_eir_prof_id; 1164 __le32 port_cir_prof_id; 1165 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */ 1166 __le32 tc_node_prio; 1167 #define ICE_TC_NODE_PRIO_S 0x4 1168 u8 reserved1[4]; 1169 __le32 tc_node_teid[8]; /* Used for response, reserved in command */ 1170 }; 1171 1172 /* Rate limiting profile for 1173 * Add RL profile (indirect 0x0410) 1174 * Query RL profile (indirect 0x0411) 1175 * Remove RL profile (indirect 0x0415) 1176 * These indirect commands acts on single or multiple 1177 * RL profiles with specified data. 1178 */ 1179 struct ice_aqc_rl_profile { 1180 __le16 num_profiles; 1181 __le16 num_processed; /* Only for response. Reserved in Command. */ 1182 u8 reserved[4]; 1183 __le32 addr_high; 1184 __le32 addr_low; 1185 }; 1186 1187 struct ice_aqc_rl_profile_elem { 1188 u8 level; 1189 u8 flags; 1190 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0 1191 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S) 1192 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0 1193 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1 1194 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2 1195 /* The following flag is used for Query RL Profile Data */ 1196 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7 1197 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S) 1198 1199 __le16 profile_id; 1200 __le16 max_burst_size; 1201 __le16 rl_multiply; 1202 __le16 wake_up_calc; 1203 __le16 rl_encode; 1204 }; 1205 1206 /* Config Node Attributes (indirect 0x0419) 1207 * Query Node Attributes (indirect 0x041A) 1208 */ 1209 struct ice_aqc_node_attr { 1210 __le16 num_entries; /* Number of attributes structures in the buffer */ 1211 u8 reserved[6]; 1212 __le32 addr_high; 1213 __le32 addr_low; 1214 }; 1215 1216 struct ice_aqc_node_attr_elem { 1217 __le32 node_teid; 1218 __le16 max_children; 1219 __le16 children_level; 1220 }; 1221 1222 /* Configure L2 Node CGD (indirect 0x0414) 1223 * This indirect command allows configuring a congestion domain for given L2 1224 * node TEIDs in the scheduler topology. 1225 */ 1226 struct ice_aqc_cfg_l2_node_cgd { 1227 __le16 num_l2_nodes; 1228 u8 reserved[6]; 1229 __le32 addr_high; 1230 __le32 addr_low; 1231 }; 1232 1233 struct ice_aqc_cfg_l2_node_cgd_elem { 1234 __le32 node_teid; 1235 u8 cgd; 1236 u8 reserved[3]; 1237 }; 1238 1239 /* Query Scheduler Resource Allocation (indirect 0x0412) 1240 * This indirect command retrieves the scheduler resources allocated by 1241 * EMP Firmware to the given PF. 1242 */ 1243 struct ice_aqc_query_txsched_res { 1244 u8 reserved[8]; 1245 __le32 addr_high; 1246 __le32 addr_low; 1247 }; 1248 1249 struct ice_aqc_generic_sched_props { 1250 __le16 phys_levels; 1251 __le16 logical_levels; 1252 u8 flattening_bitmap; 1253 u8 max_device_cgds; 1254 u8 max_pf_cgds; 1255 u8 rsvd0; 1256 __le16 rdma_qsets; 1257 u8 rsvd1[22]; 1258 }; 1259 1260 struct ice_aqc_layer_props { 1261 u8 logical_layer; 1262 u8 chunk_size; 1263 __le16 max_device_nodes; 1264 __le16 max_pf_nodes; 1265 u8 rsvd0[4]; 1266 __le16 max_sibl_grp_sz; 1267 __le16 max_cir_rl_profiles; 1268 __le16 max_eir_rl_profiles; 1269 __le16 max_srl_profiles; 1270 u8 rsvd1[14]; 1271 }; 1272 1273 struct ice_aqc_query_txsched_res_resp { 1274 struct ice_aqc_generic_sched_props sched_props; 1275 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 1276 }; 1277 1278 /* Query Node to Root Topology (indirect 0x0413) 1279 * This command uses ice_aqc_get_elem as its data buffer. 1280 */ 1281 struct ice_aqc_query_node_to_root { 1282 __le32 teid; 1283 __le32 num_nodes; /* Response only */ 1284 __le32 addr_high; 1285 __le32 addr_low; 1286 }; 1287 1288 /* Get PHY capabilities (indirect 0x0600) */ 1289 struct ice_aqc_get_phy_caps { 1290 u8 lport_num; 1291 u8 reserved; 1292 __le16 param0; 1293 /* 18.0 - Report qualified modules */ 1294 #define ICE_AQC_GET_PHY_RQM BIT(0) 1295 /* 18.1 - 18.3 : Report mode 1296 * 000b - Report topology capabilities, without media 1297 * 001b - Report topology capabilities, with media 1298 * 010b - Report Active configuration 1299 * 011b - Report PHY Type and FEC mode capabilities 1300 * 100b - Report Default capabilities 1301 */ 1302 #define ICE_AQC_REPORT_MODE_S 1 1303 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) 1304 #define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0 1305 #define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1) 1306 #define ICE_AQC_REPORT_ACTIVE_CFG BIT(2) 1307 #define ICE_AQC_REPORT_DFLT_CFG BIT(3) 1308 __le32 reserved1; 1309 __le32 addr_high; 1310 __le32 addr_low; 1311 }; 1312 1313 /* This is #define of PHY type (Extended): 1314 * The first set of defines is for phy_type_low. 1315 */ 1316 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) 1317 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) 1318 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) 1319 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) 1320 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) 1321 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) 1322 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) 1323 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) 1324 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) 1325 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) 1326 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) 1327 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) 1328 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) 1329 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) 1330 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) 1331 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) 1332 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) 1333 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) 1334 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) 1335 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) 1336 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) 1337 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) 1338 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) 1339 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) 1340 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) 1341 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) 1342 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) 1343 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) 1344 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) 1345 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) 1346 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) 1347 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) 1348 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) 1349 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) 1350 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) 1351 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) 1352 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36) 1353 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37) 1354 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38) 1355 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39) 1356 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40) 1357 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41) 1358 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42) 1359 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43) 1360 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44) 1361 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45) 1362 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46) 1363 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47) 1364 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48) 1365 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49) 1366 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50) 1367 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51) 1368 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52) 1369 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53) 1370 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54) 1371 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55) 1372 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56) 1373 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57) 1374 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58) 1375 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59) 1376 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60) 1377 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61) 1378 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62) 1379 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63) 1380 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 1381 /* The second set of defines is for phy_type_high. */ 1382 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0) 1383 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1) 1384 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) 1385 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) 1386 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) 1387 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 4 1388 1389 struct ice_aqc_get_phy_caps_data { 1390 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1391 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1392 u8 caps; 1393 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) 1394 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) 1395 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) 1396 #define ICE_AQC_PHY_EN_LINK BIT(3) 1397 #define ICE_AQC_PHY_AN_MODE BIT(4) 1398 #define ICE_AQC_PHY_EN_MOD_QUAL BIT(5) 1399 #define ICE_AQC_PHY_EN_LESM BIT(6) 1400 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7) 1401 #define ICE_AQC_PHY_CAPS_MASK MAKEMASK(0xff, 0) 1402 u8 low_power_ctrl_an; 1403 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) 1404 #define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1) 1405 #define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2) 1406 #define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3) 1407 __le16 eee_cap; 1408 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) 1409 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) 1410 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) 1411 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) 1412 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) 1413 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) 1414 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) 1415 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR2 BIT(7) 1416 #define ICE_AQC_PHY_EEE_EN_50GBASE_KR_PAM4 BIT(8) 1417 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR4 BIT(9) 1418 #define ICE_AQC_PHY_EEE_EN_100GBASE_KR2_PAM4 BIT(10) 1419 __le16 eeer_value; 1420 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ 1421 u8 phy_fw_ver[8]; 1422 u8 link_fec_options; 1423 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) 1424 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) 1425 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) 1426 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) 1427 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) 1428 #define ICE_AQC_PHY_FEC_DIS BIT(5) 1429 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) 1430 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) 1431 #define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0) 1432 u8 module_compliance_enforcement; 1433 #define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0) 1434 u8 extended_compliance_code; 1435 #define ICE_MODULE_TYPE_TOTAL_BYTE 3 1436 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 1437 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 1438 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 1439 #define ICE_AQC_MOD_TYPE_IDENT 1 1440 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) 1441 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) 1442 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) 1443 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) 1444 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) 1445 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) 1446 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 1447 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 1448 u8 qualified_module_count; 1449 u8 rsvd2[7]; /* Bytes 47:41 reserved */ 1450 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 1451 struct { 1452 u8 v_oui[3]; 1453 u8 rsvd3; 1454 u8 v_part[16]; 1455 __le32 v_rev; 1456 __le64 rsvd4; 1457 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; 1458 }; 1459 1460 /* Set PHY capabilities (direct 0x0601) 1461 * NOTE: This command must be followed by setup link and restart auto-neg 1462 */ 1463 struct ice_aqc_set_phy_cfg { 1464 u8 lport_num; 1465 u8 reserved[7]; 1466 __le32 addr_high; 1467 __le32 addr_low; 1468 }; 1469 1470 /* Set PHY config command data structure */ 1471 struct ice_aqc_set_phy_cfg_data { 1472 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1473 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1474 u8 caps; 1475 #define ICE_AQ_PHY_ENA_VALID_MASK MAKEMASK(0xef, 0) 1476 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0) 1477 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1) 1478 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2) 1479 #define ICE_AQ_PHY_ENA_LINK BIT(3) 1480 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5) 1481 #define ICE_AQ_PHY_ENA_LESM BIT(6) 1482 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7) 1483 u8 low_power_ctrl_an; 1484 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */ 1485 __le16 eeer_value; 1486 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */ 1487 u8 module_compliance_enforcement; 1488 }; 1489 1490 /* Set MAC Config command data structure (direct 0x0603) */ 1491 struct ice_aqc_set_mac_cfg { 1492 __le16 max_frame_size; 1493 u8 params; 1494 #define ICE_AQ_SET_MAC_PACE_S 3 1495 #define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S) 1496 #define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7) 1497 #define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0 1498 #define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M 1499 u8 tx_tmr_priority; 1500 __le16 tx_tmr_value; 1501 __le16 fc_refresh_threshold; 1502 u8 drop_opts; 1503 #define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0) 1504 #define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0 1505 #define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0) 1506 u8 reserved[7]; 1507 }; 1508 1509 /* Restart AN command data structure (direct 0x0605) 1510 * Also used for response, with only the lport_num field present. 1511 */ 1512 struct ice_aqc_restart_an { 1513 u8 lport_num; 1514 u8 reserved; 1515 u8 cmd_flags; 1516 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1) 1517 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2) 1518 u8 reserved2[13]; 1519 }; 1520 1521 /* Get link status (indirect 0x0607), also used for Link Status Event */ 1522 struct ice_aqc_get_link_status { 1523 u8 lport_num; 1524 u8 reserved; 1525 __le16 cmd_flags; 1526 #define ICE_AQ_LSE_M 0x3 1527 #define ICE_AQ_LSE_NOP 0x0 1528 #define ICE_AQ_LSE_DIS 0x2 1529 #define ICE_AQ_LSE_ENA 0x3 1530 /* only response uses this flag */ 1531 #define ICE_AQ_LSE_IS_ENABLED 0x1 1532 __le32 reserved2; 1533 __le32 addr_high; 1534 __le32 addr_low; 1535 }; 1536 1537 enum ice_get_link_status_data_version { 1538 ICE_GET_LINK_STATUS_DATA_V1 = 1, 1539 }; 1540 1541 #define ICE_GET_LINK_STATUS_DATALEN_V1 32 1542 1543 /* Get link status response data structure, also used for Link Status Event */ 1544 struct ice_aqc_get_link_status_data { 1545 u8 topo_media_conflict; 1546 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) 1547 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) 1548 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) 1549 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4) 1550 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5) 1551 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6) 1552 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7) 1553 u8 link_cfg_err; 1554 #define ICE_AQ_LINK_CFG_ERR BIT(0) 1555 #define ICE_AQ_LINK_ACT_PORT_OPT_INVAL BIT(2) 1556 #define ICE_AQ_LINK_FEAT_ID_OR_CONFIG_ID_INVAL BIT(3) 1557 #define ICE_AQ_LINK_TOPO_CRITICAL_SDP_ERR BIT(4) 1558 #define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5) 1559 #define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6) 1560 #define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7) 1561 u8 link_info; 1562 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ 1563 #define ICE_AQ_LINK_FAULT BIT(1) 1564 #define ICE_AQ_LINK_FAULT_TX BIT(2) 1565 #define ICE_AQ_LINK_FAULT_RX BIT(3) 1566 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) 1567 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ 1568 #define ICE_AQ_MEDIA_AVAILABLE BIT(6) 1569 #define ICE_AQ_SIGNAL_DETECT BIT(7) 1570 u8 an_info; 1571 #define ICE_AQ_AN_COMPLETED BIT(0) 1572 #define ICE_AQ_LP_AN_ABILITY BIT(1) 1573 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ 1574 #define ICE_AQ_FEC_EN BIT(3) 1575 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ 1576 #define ICE_AQ_LINK_PAUSE_TX BIT(5) 1577 #define ICE_AQ_LINK_PAUSE_RX BIT(6) 1578 #define ICE_AQ_QUALIFIED_MODULE BIT(7) 1579 u8 ext_info; 1580 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) 1581 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ 1582 /* Port Tx Suspended */ 1583 #define ICE_AQ_LINK_TX_S 2 1584 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) 1585 #define ICE_AQ_LINK_TX_ACTIVE 0 1586 #define ICE_AQ_LINK_TX_DRAINED 1 1587 #define ICE_AQ_LINK_TX_FLUSHED 3 1588 u8 lb_status; 1589 #define ICE_AQ_LINK_LB_PHY_LCL BIT(0) 1590 #define ICE_AQ_LINK_LB_PHY_RMT BIT(1) 1591 #define ICE_AQ_LINK_LB_MAC_LCL BIT(2) 1592 #define ICE_AQ_LINK_LB_PHY_IDX_S 3 1593 #define ICE_AQ_LINK_LB_PHY_IDX_M (0x7 << ICE_AQ_LB_PHY_IDX_S) 1594 __le16 max_frame_size; 1595 u8 cfg; 1596 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) 1597 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) 1598 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) 1599 #define ICE_AQ_FEC_MASK MAKEMASK(0x7, 0) 1600 /* Pacing Config */ 1601 #define ICE_AQ_CFG_PACING_S 3 1602 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) 1603 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) 1604 #define ICE_AQ_CFG_PACING_TYPE_AVG 0 1605 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M 1606 /* External Device Power Ability */ 1607 u8 power_desc; 1608 #define ICE_AQ_PWR_CLASS_M 0x3F 1609 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 1610 #define ICE_AQ_LINK_PWR_BASET_HIGH 1 1611 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 1612 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 1613 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 1614 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 1615 __le16 link_speed; 1616 #define ICE_AQ_LINK_SPEED_M 0x7FF 1617 #define ICE_AQ_LINK_SPEED_10MB BIT(0) 1618 #define ICE_AQ_LINK_SPEED_100MB BIT(1) 1619 #define ICE_AQ_LINK_SPEED_1000MB BIT(2) 1620 #define ICE_AQ_LINK_SPEED_2500MB BIT(3) 1621 #define ICE_AQ_LINK_SPEED_5GB BIT(4) 1622 #define ICE_AQ_LINK_SPEED_10GB BIT(5) 1623 #define ICE_AQ_LINK_SPEED_20GB BIT(6) 1624 #define ICE_AQ_LINK_SPEED_25GB BIT(7) 1625 #define ICE_AQ_LINK_SPEED_40GB BIT(8) 1626 #define ICE_AQ_LINK_SPEED_50GB BIT(9) 1627 #define ICE_AQ_LINK_SPEED_100GB BIT(10) 1628 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) 1629 __le32 reserved3; /* Aligns next field to 8-byte boundary */ 1630 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ 1631 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ 1632 }; 1633 1634 /* Set event mask command (direct 0x0613) */ 1635 struct ice_aqc_set_event_mask { 1636 u8 lport_num; 1637 u8 reserved[7]; 1638 __le16 event_mask; 1639 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1) 1640 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2) 1641 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3) 1642 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4) 1643 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5) 1644 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6) 1645 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7) 1646 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8) 1647 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) 1648 #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) 1649 #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) 1650 #define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) 1651 u8 reserved1[6]; 1652 }; 1653 1654 /* Set PHY Loopback command (direct 0x0619) */ 1655 struct ice_aqc_set_phy_lb { 1656 u8 lport_num; 1657 u8 lport_num_valid; 1658 #define ICE_AQ_PHY_LB_PORT_NUM_VALID BIT(0) 1659 u8 phy_index; 1660 u8 lb_mode; 1661 #define ICE_AQ_PHY_LB_EN BIT(0) 1662 #define ICE_AQ_PHY_LB_TYPE_M BIT(1) 1663 #define ICE_AQ_PHY_LB_TYPE_LOCAL 0 1664 #define ICE_AQ_PHY_LB_TYPE_REMOTE ICE_AQ_PHY_LB_TYPE_M 1665 #define ICE_AQ_PHY_LB_LEVEL_M BIT(2) 1666 #define ICE_AQ_PHY_LB_LEVEL_PMD 0 1667 #define ICE_AQ_PHY_LB_LEVEL_PCS ICE_AQ_PHY_LB_LEVEL_M 1668 u8 reserved2[12]; 1669 }; 1670 1671 /* Set MAC Loopback command (direct 0x0620) */ 1672 struct ice_aqc_set_mac_lb { 1673 u8 lb_mode; 1674 #define ICE_AQ_MAC_LB_EN BIT(0) 1675 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1) 1676 u8 reserved[15]; 1677 }; 1678 1679 /* Get sensor reading (direct 0x0632) */ 1680 struct ice_aqc_get_sensor_reading { 1681 u8 sensor; 1682 #define ICE_AQC_INT_TEMP_SENSOR 0x0 1683 u8 format; 1684 #define ICE_AQC_INT_TEMP_FORMAT 0x0 1685 u8 reserved[6]; 1686 __le32 addr_high; 1687 __le32 addr_low; 1688 }; 1689 1690 /* Get sensor reading response (direct 0x0632) */ 1691 struct ice_aqc_get_sensor_reading_resp { 1692 union { 1693 u8 raw[8]; 1694 /* Output data for sensor 0x00, format 0x00 */ 1695 struct { 1696 s8 temp; 1697 u8 temp_warning_threshold; 1698 u8 temp_critical_threshold; 1699 u8 temp_fatal_threshold; 1700 u8 reserved[4]; 1701 } s0f0; 1702 } data; 1703 }; 1704 1705 /* DNL Get Status command (indirect 0x0680) 1706 * Structure used for the response, the command uses the generic 1707 * ice_aqc_generic struct to pass a buffer address to the FW. 1708 */ 1709 struct ice_aqc_dnl_get_status { 1710 u8 ctx; 1711 u8 status; 1712 #define ICE_AQ_DNL_STATUS_IDLE 0x0 1713 #define ICE_AQ_DNL_STATUS_RESERVED 0x1 1714 #define ICE_AQ_DNL_STATUS_STOPPED 0x2 1715 #define ICE_AQ_DNL_STATUS_FATAL 0x3 /* Fatal DNL engine error */ 1716 #define ICE_AQ_DNL_SRC_S 3 1717 #define ICE_AQ_DNL_SRC_M (0x3 << ICE_AQ_DNL_SRC_S) 1718 #define ICE_AQ_DNL_SRC_NVM (0x0 << ICE_AQ_DNL_SRC_S) 1719 #define ICE_AQ_DNL_SRC_NVM_SCRATCH (0x1 << ICE_AQ_DNL_SRC_S) 1720 u8 stack_ptr; 1721 #define ICE_AQ_DNL_ST_PTR_S 0x0 1722 #define ICE_AQ_DNL_ST_PTR_M (0x7 << ICE_AQ_DNL_ST_PTR_S) 1723 u8 engine_flags; 1724 #define ICE_AQ_DNL_FLAGS_ERROR BIT(2) 1725 #define ICE_AQ_DNL_FLAGS_NEGATIVE BIT(3) 1726 #define ICE_AQ_DNL_FLAGS_OVERFLOW BIT(4) 1727 #define ICE_AQ_DNL_FLAGS_ZERO BIT(5) 1728 #define ICE_AQ_DNL_FLAGS_CARRY BIT(6) 1729 #define ICE_AQ_DNL_FLAGS_JUMP BIT(7) 1730 __le16 pc; 1731 __le16 activity_id; 1732 __le32 addr_high; 1733 __le32 addr_low; 1734 }; 1735 1736 struct ice_aqc_dnl_get_status_data { 1737 __le16 activity_err_code; 1738 __le16 act_err_code; 1739 #define ICE_AQ_DNL_ACT_ERR_SUCCESS 0x0000 /* no error */ 1740 #define ICE_AQ_DNL_ACT_ERR_PARSE 0x8001 /* NVM parse error */ 1741 #define ICE_AQ_DNL_ACT_ERR_UNSUPPORTED 0x8002 /* unsupported action */ 1742 #define ICE_AQ_DNL_ACT_ERR_NOT_FOUND 0x8003 /* activity not found */ 1743 #define ICE_AQ_DNL_ACT_ERR_BAD_JUMP 0x8004 /* an illegal jump */ 1744 #define ICE_AQ_DNL_ACT_ERR_PSTO_OVER 0x8005 /* persistent store overflow */ 1745 #define ICE_AQ_DNL_ACT_ERR_ST_OVERFLOW 0x8006 /* stack overflow */ 1746 #define ICE_AQ_DNL_ACT_ERR_TIMEOUT 0x8007 /* activity timeout */ 1747 #define ICE_AQ_DNL_ACT_ERR_BREAK 0x0008 /* stopped at breakpoint */ 1748 #define ICE_AQ_DNL_ACT_ERR_INVAL_ARG 0x0101 /* invalid action argument */ 1749 __le32 execution_time; /* in nanoseconds */ 1750 __le16 lib_ver; 1751 u8 psto_local_sz; 1752 u8 psto_global_sz; 1753 u8 stack_sz; 1754 #define ICE_AQ_DNL_STACK_SZ_S 0 1755 #define ICE_AQ_DNL_STACK_SZ_M (0xF << ICE_AQ_DNL_STACK_SZ_S) 1756 u8 port_count; 1757 #define ICE_AQ_DNL_PORT_CNT_S 0 1758 #define ICE_AQ_DNL_PORT_CNT_M (0x1F << ICE_AQ_DNL_PORT_CNT_S) 1759 __le16 act_cache_cntr; 1760 u32 i2c_clk_cntr; 1761 u32 mdio_clk_cntr; 1762 u32 sb_iosf_clk_cntr; 1763 }; 1764 1765 /* DNL run command (direct 0x0681) */ 1766 struct ice_aqc_dnl_run_command { 1767 u8 reserved0; 1768 u8 command; 1769 #define ICE_AQ_DNL_CMD_S 0 1770 #define ICE_AQ_DNL_CMD_M (0x7 << ICE_AQ_DNL_CMD_S) 1771 #define ICE_AQ_DNL_CMD_RESET 0x0 1772 #define ICE_AQ_DNL_CMD_RUN 0x1 1773 #define ICE_AQ_DNL_CMD_STEP 0x3 1774 #define ICE_AQ_DNL_CMD_ABORT 0x4 1775 #define ICE_AQ_DNL_CMD_SET_PC 0x7 1776 #define ICE_AQ_DNL_CMD_SRC_S 3 1777 #define ICE_AQ_DNL_CMD_SRC_M (0x3 << ICE_AQ_DNL_CMD_SRC_S) 1778 #define ICE_AQ_DNL_CMD_SRC_DNL 0x0 1779 #define ICE_AQ_DNL_CMD_SRC_SCRATCH 0x1 1780 __le16 new_pc; 1781 u8 reserved1[12]; 1782 }; 1783 1784 /* DNL call command (indirect 0x0682) 1785 * Struct is used for both command and response 1786 */ 1787 struct ice_aqc_dnl_call_command { 1788 u8 ctx; /* Used in command, reserved in response */ 1789 u8 reserved; 1790 __le16 activity_id; 1791 __le32 reserved1; 1792 __le32 addr_high; 1793 __le32 addr_low; 1794 }; 1795 1796 /* DNL call command/response buffer (indirect 0x0682) */ 1797 struct ice_aqc_dnl_call { 1798 __le32 stores[4]; 1799 }; 1800 1801 /* Used for both commands: 1802 * DNL read sto command (indirect 0x0683) 1803 * DNL write sto command (indirect 0x0684) 1804 */ 1805 struct ice_aqc_dnl_read_write_command { 1806 u8 ctx; 1807 u8 sto_sel; /* STORE select */ 1808 #define ICE_AQC_DNL_STORE_SELECT_STORE 0x0 1809 #define ICE_AQC_DNL_STORE_SELECT_PSTO 0x1 1810 #define ICE_AQC_DNL_STORE_SELECT_STACK 0x2 1811 __le16 offset; 1812 __le32 data; /* Used for write sto only */ 1813 __le32 addr_high; /* Used for read sto only */ 1814 __le32 addr_low; /* Used for read sto only */ 1815 }; 1816 1817 /* Used for both command responses: 1818 * DNL read sto response (indirect 0x0683) 1819 * DNL write sto response (indirect 0x0684) 1820 */ 1821 struct ice_aqc_dnl_read_write_response { 1822 u8 reserved; 1823 u8 status; /* Reserved for read command */ 1824 __le16 size; /* Reserved for write command */ 1825 __le32 data; /* Reserved for write command */ 1826 __le32 addr_high; /* Reserved for write command */ 1827 __le32 addr_low; /* Reserved for write command */ 1828 }; 1829 1830 /* DNL set breakpoints command (indirect 0x0686) */ 1831 struct ice_aqc_dnl_set_breakpoints_command { 1832 __le32 reserved[2]; 1833 __le32 addr_high; 1834 __le32 addr_low; 1835 }; 1836 1837 /* DNL set breakpoints data buffer structure (indirect 0x0686) */ 1838 struct ice_aqc_dnl_set_breakpoints { 1839 u8 ctx; 1840 u8 ena; /* 0- disabled, 1- enabled */ 1841 __le16 offset; 1842 __le16 activity_id; 1843 }; 1844 1845 /* DNL read log data command(indirect 0x0687) */ 1846 struct ice_aqc_dnl_read_log_command { 1847 __le16 reserved0; 1848 __le16 offset; 1849 __le32 reserved1; 1850 __le32 addr_high; 1851 __le32 addr_low; 1852 1853 }; 1854 1855 /* DNL read log data response(indirect 0x0687) */ 1856 struct ice_aqc_dnl_read_log_response { 1857 __le16 reserved; 1858 __le16 size; 1859 __le32 data; 1860 __le32 addr_high; 1861 __le32 addr_low; 1862 1863 }; 1864 1865 struct ice_aqc_link_topo_params { 1866 u8 lport_num; 1867 u8 lport_num_valid; 1868 #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) 1869 u8 node_type_ctx; 1870 #define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0 1871 #define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S) 1872 #define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0 1873 #define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1 1874 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2 1875 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3 1876 #define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4 1877 #define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5 1878 #define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6 1879 #define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7 1880 #define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8 1881 #define ICE_AQC_LINK_TOPO_NODE_CTX_S 4 1882 #define ICE_AQC_LINK_TOPO_NODE_CTX_M \ 1883 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S) 1884 #define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0 1885 #define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1 1886 #define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2 1887 #define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3 1888 #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 1889 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 1890 u8 index; 1891 }; 1892 1893 struct ice_aqc_link_topo_addr { 1894 struct ice_aqc_link_topo_params topo_params; 1895 __le16 handle; 1896 #define ICE_AQC_LINK_TOPO_HANDLE_S 0 1897 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) 1898 /* Used to decode the handle field */ 1899 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) 1900 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) 1901 #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 1902 #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 1903 /* In case of a Mezzanine type */ 1904 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ 1905 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1906 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6 1907 #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S) 1908 /* In case of a LOM type */ 1909 #define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \ 1910 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S) 1911 }; 1912 1913 /* Get Link Topology Handle (direct, 0x06E0) */ 1914 struct ice_aqc_get_link_topo { 1915 struct ice_aqc_link_topo_addr addr; 1916 u8 node_part_num; 1917 #define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 1918 u8 rsvd[9]; 1919 }; 1920 1921 /* Read/Write I2C (direct, 0x06E2/0x06E3) */ 1922 struct ice_aqc_i2c { 1923 struct ice_aqc_link_topo_addr topo_addr; 1924 __le16 i2c_addr; 1925 u8 i2c_params; 1926 #define ICE_AQC_I2C_DATA_SIZE_S 0 1927 #define ICE_AQC_I2C_DATA_SIZE_M (0xF << ICE_AQC_I2C_DATA_SIZE_S) 1928 #define ICE_AQC_I2C_ADDR_TYPE_M BIT(4) 1929 #define ICE_AQC_I2C_ADDR_TYPE_7BIT 0 1930 #define ICE_AQC_I2C_ADDR_TYPE_10BIT ICE_AQC_I2C_ADDR_TYPE_M 1931 #define ICE_AQC_I2C_DATA_OFFSET_S 5 1932 #define ICE_AQC_I2C_DATA_OFFSET_M (0x3 << ICE_AQC_I2C_DATA_OFFSET_S) 1933 #define ICE_AQC_I2C_USE_REPEATED_START BIT(7) 1934 u8 rsvd; 1935 __le16 i2c_bus_addr; 1936 #define ICE_AQC_I2C_ADDR_7BIT_MASK 0x7F 1937 #define ICE_AQC_I2C_ADDR_10BIT_MASK 0x3FF 1938 u8 i2c_data[4]; /* Used only by write command, reserved in read. */ 1939 }; 1940 1941 /* Read I2C Response (direct, 0x06E2) */ 1942 struct ice_aqc_read_i2c_resp { 1943 u8 i2c_data[16]; 1944 }; 1945 1946 /* Read/Write MDIO (direct, 0x06E4/0x06E5) */ 1947 struct ice_aqc_mdio { 1948 struct ice_aqc_link_topo_addr topo_addr; 1949 u8 mdio_device_addr; 1950 #define ICE_AQC_MDIO_DEV_S 0 1951 #define ICE_AQC_MDIO_DEV_M (0x1F << ICE_AQC_MDIO_DEV_S) 1952 #define ICE_AQC_MDIO_CLAUSE_22 BIT(5) 1953 #define ICE_AQC_MDIO_CLAUSE_45 BIT(6) 1954 u8 mdio_bus_address; 1955 #define ICE_AQC_MDIO_BUS_ADDR_S 0 1956 #define ICE_AQC_MDIO_BUS_ADDR_M (0x1F << ICE_AQC_MDIO_BUS_ADDR_S) 1957 __le16 offset; 1958 __le16 data; /* Input in write cmd, output in read cmd. */ 1959 u8 rsvd1[4]; 1960 }; 1961 1962 /* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */ 1963 struct ice_aqc_gpio_by_func { 1964 struct ice_aqc_link_topo_addr topo_addr; 1965 u8 io_func_num; 1966 #define ICE_AQC_GPIO_FUNC_S 0 1967 #define ICE_AQC_GPIO_FUNC_M (0x1F << ICE_AQC_GPIO_IO_FUNC_NUM_S) 1968 u8 io_value; /* Input in write cmd, output in read cmd. */ 1969 #define ICE_AQC_GPIO_ON BIT(0) 1970 #define ICE_AQC_GPIO_OFF 0 1971 u8 rsvd[8]; 1972 }; 1973 1974 /* Set LED (direct, 0x06E8) */ 1975 struct ice_aqc_set_led { 1976 struct ice_aqc_link_topo_addr topo_addr; 1977 u8 color_and_blink; 1978 #define ICE_AQC_LED_COLOR_S 0 1979 #define ICE_AQC_LED_COLOR_M (0x7 << ICE_AQC_LED_COLOR_S) 1980 #define ICE_AQC_LED_COLOR_SKIP 0 1981 #define ICE_AQC_LED_COLOR_RED 1 1982 #define ICE_AQC_LED_COLOR_ORANGE 2 1983 #define ICE_AQC_LED_COLOR_YELLOW 3 1984 #define ICE_AQC_LED_COLOR_GREEN 4 1985 #define ICE_AQC_LED_COLOR_BLUE 5 1986 #define ICE_AQC_LED_COLOR_PURPLE 6 1987 #define ICE_AQC_LED_BLINK_S 3 1988 #define ICE_AQC_LED_BLINK_M (0x7 << ICE_AQC_LED_BLINK_S) 1989 #define ICE_AQC_LED_BLINK_NONE 0 1990 #define ICE_AQC_LED_BLINK_SLOW 1 1991 #define ICE_AQC_LED_BLINK_SLOW_MAC 2 1992 #define ICE_AQC_LED_BLINK_SLOW_FLTR 3 1993 #define ICE_AQC_LED_BLINK_FAST 5 1994 #define ICE_AQC_LED_BLINK_FAST_MAC 6 1995 #define ICE_AQC_LED_BLINK_FAST_FLTR 7 1996 u8 rsvd[9]; 1997 }; 1998 1999 /* Set Port Identification LED (direct, 0x06E9) */ 2000 struct ice_aqc_set_port_id_led { 2001 u8 lport_num; 2002 u8 lport_num_valid; 2003 #define ICE_AQC_PORT_ID_PORT_NUM_VALID BIT(0) 2004 u8 ident_mode; 2005 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0) 2006 #define ICE_AQC_PORT_IDENT_LED_ORIG 0 2007 u8 rsvd[13]; 2008 }; 2009 2010 /* Get Port Options (indirect, 0x06EA) */ 2011 struct ice_aqc_get_port_options { 2012 u8 lport_num; 2013 u8 lport_num_valid; 2014 #define ICE_AQC_PORT_OPT_PORT_NUM_VALID BIT(0) 2015 u8 port_options_count; 2016 #define ICE_AQC_PORT_OPT_COUNT_S 0 2017 #define ICE_AQC_PORT_OPT_COUNT_M (0xF << ICE_AQC_PORT_OPT_COUNT_S) 2018 #define ICE_AQC_PORT_OPT_MAX 16 2019 u8 innermost_phy_index; 2020 u8 port_options; 2021 #define ICE_AQC_PORT_OPT_ACTIVE_S 0 2022 #define ICE_AQC_PORT_OPT_ACTIVE_M (0xF << ICE_AQC_PORT_OPT_ACTIVE_S) 2023 #define ICE_AQC_PORT_OPT_FORCED BIT(6) 2024 #define ICE_AQC_PORT_OPT_VALID BIT(7) 2025 u8 pending_port_option_status; 2026 #define ICE_AQC_PENDING_PORT_OPT_IDX_S 0 2027 #define ICE_AQC_PENDING_PORT_OPT_IDX_M (0xF << ICE_AQC_PENDING_PORT_OPT_IDX_S) 2028 #define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7) 2029 u8 rsvd[2]; 2030 __le32 addr_high; 2031 __le32 addr_low; 2032 }; 2033 2034 struct ice_aqc_get_port_options_elem { 2035 u8 pmd; 2036 #define ICE_AQC_PORT_INV_PORT_OPT 4 2037 #define ICE_AQC_PORT_OPT_PMD_COUNT_S 0 2038 #define ICE_AQC_PORT_OPT_PMD_COUNT_M (0xF << ICE_AQC_PORT_OPT_PMD_COUNT_S) 2039 #define ICE_AQC_PORT_OPT_PMD_WIDTH_S 4 2040 #define ICE_AQC_PORT_OPT_PMD_WIDTH_M (0xF << ICE_AQC_PORT_OPT_PMD_WIDTH_S) 2041 u8 max_lane_speed; 2042 #define ICE_AQC_PORT_OPT_MAX_LANE_S 0 2043 #define ICE_AQC_PORT_OPT_MAX_LANE_M (0xF << ICE_AQC_PORT_OPT_MAX_LANE_S) 2044 #define ICE_AQC_PORT_OPT_MAX_LANE_100M 0 2045 #define ICE_AQC_PORT_OPT_MAX_LANE_1G 1 2046 #define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2 2047 #define ICE_AQC_PORT_OPT_MAX_LANE_5G 3 2048 #define ICE_AQC_PORT_OPT_MAX_LANE_10G 4 2049 #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 2050 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 2051 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 2052 u8 global_scid[2]; 2053 u8 phy_scid[2]; 2054 u8 pf2port_cid[2]; 2055 }; 2056 2057 /* Set Port Option (direct, 0x06EB) */ 2058 struct ice_aqc_set_port_option { 2059 u8 lport_num; 2060 u8 lport_num_valid; 2061 #define ICE_AQC_SET_PORT_OPT_PORT_NUM_VALID BIT(0) 2062 u8 selected_port_option; 2063 u8 rsvd[13]; 2064 }; 2065 2066 /* Set/Get GPIO (direct, 0x06EC/0x06ED) */ 2067 struct ice_aqc_gpio { 2068 __le16 gpio_ctrl_handle; 2069 #define ICE_AQC_GPIO_HANDLE_S 0 2070 #define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S) 2071 u8 gpio_num; 2072 u8 gpio_val; 2073 u8 rsvd[12]; 2074 }; 2075 2076 /* Read/Write SFF EEPROM command (indirect 0x06EE) */ 2077 struct ice_aqc_sff_eeprom { 2078 u8 lport_num; 2079 u8 lport_num_valid; 2080 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0) 2081 __le16 i2c_bus_addr; 2082 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F 2083 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF 2084 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10) 2085 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0 2086 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M 2087 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11 2088 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S) 2089 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0 2090 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1 2091 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2 2092 #define ICE_AQC_SFF_IS_WRITE BIT(15) 2093 __le16 i2c_mem_addr; 2094 __le16 eeprom_page; 2095 #define ICE_AQC_SFF_EEPROM_BANK_S 0 2096 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S) 2097 #define ICE_AQC_SFF_EEPROM_PAGE_S 8 2098 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S) 2099 __le32 addr_high; 2100 __le32 addr_low; 2101 }; 2102 2103 /* SW Set GPIO command (indirect 0x6EF) 2104 * SW Get GPIO command (indirect 0x6F0) 2105 */ 2106 struct ice_aqc_sw_gpio { 2107 __le16 gpio_ctrl_handle; 2108 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S 0 2109 #define ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_M (0x3FF << ICE_AQC_SW_GPIO_CONTROLLER_HANDLE_S) 2110 u8 gpio_num; 2111 #define ICE_AQC_SW_GPIO_NUMBER_S 0 2112 #define ICE_AQC_SW_GPIO_NUMBER_M (0x1F << ICE_AQC_SW_GPIO_NUMBER_S) 2113 u8 gpio_params; 2114 #define ICE_AQC_SW_GPIO_PARAMS_DIRECTION BIT(1) 2115 #define ICE_AQC_SW_GPIO_PARAMS_VALUE BIT(0) 2116 u8 rsvd[12]; 2117 }; 2118 2119 /* Program Topology Device NVM (direct, 0x06F2) */ 2120 struct ice_aqc_prog_topo_dev_nvm { 2121 struct ice_aqc_link_topo_params topo_params; 2122 u8 rsvd[12]; 2123 }; 2124 2125 /* Read Topology Device NVM (direct, 0x06F3) */ 2126 struct ice_aqc_read_topo_dev_nvm { 2127 struct ice_aqc_link_topo_params topo_params; 2128 __le32 start_address; 2129 #define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8 2130 u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE]; 2131 }; 2132 2133 /* NVM Read command (indirect 0x0701) 2134 * NVM Erase commands (direct 0x0702) 2135 * NVM Write commands (indirect 0x0703) 2136 * NVM Write Activate commands (direct 0x0707) 2137 * NVM Shadow RAM Dump commands (direct 0x0707) 2138 */ 2139 struct ice_aqc_nvm { 2140 #define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF 2141 __le16 offset_low; 2142 u8 offset_high; /* For Write Activate offset_high is used as flags2 */ 2143 u8 cmd_flags; 2144 #define ICE_AQC_NVM_LAST_CMD BIT(0) 2145 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Write reply */ 2146 #define ICE_AQC_NVM_PRESERVATION_S 1 /* Used by NVM Write Activate only */ 2147 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S) 2148 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S) 2149 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) 2150 #define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S) 2151 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S) 2152 #define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */ 2153 #define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4) 2154 #define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5) 2155 #define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6) 2156 #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ 2157 #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) 2158 #define ICE_AQC_NVM_FLASH_ONLY BIT(7) 2159 #define ICE_AQC_NVM_RESET_LVL_M MAKEMASK(0x3, 0) /* Write reply only */ 2160 #define ICE_AQC_NVM_POR_FLAG 0 2161 #define ICE_AQC_NVM_PERST_FLAG 1 2162 #define ICE_AQC_NVM_EMPR_FLAG 2 2163 #define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ 2164 /* For Write Activate, several flags are sent as part of a separate 2165 * flags2 field using a separate byte. For simplicity of the software 2166 * interface, we pass the flags as a 16 bit value so these flags are 2167 * all offset by 8 bits 2168 */ 2169 #define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */ 2170 __le16 module_typeid; 2171 __le16 length; 2172 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF 2173 __le32 addr_high; 2174 __le32 addr_low; 2175 }; 2176 2177 /* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */ 2178 #define ICE_AQC_NVM_SECTOR_UNIT 4096 /* In Bytes */ 2179 #define ICE_AQC_NVM_WORD_UNIT 2 /* In Bytes */ 2180 2181 #define ICE_AQC_NVM_START_POINT 0 2182 #define ICE_AQC_NVM_EMP_SR_PTR_OFFSET 0x90 2183 #define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN 2 /* In Bytes */ 2184 #define ICE_AQC_NVM_EMP_SR_PTR_M MAKEMASK(0x7FFF, 0) 2185 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S 15 2186 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M BIT(15) 2187 #define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR 1 2188 2189 #define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET 0x46 2190 #define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN 2 /* In Bytes */ 2191 #define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN 2 /* In Bytes */ 2192 2193 #define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID 0x129 2194 #define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET 2 /* In Bytes */ 2195 #define ICE_AQC_NVM_LLDP_STATUS_M MAKEMASK(0xF, 0) 2196 #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ 2197 #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ 2198 2199 #define ICE_AQC_NVM_MINSREV_MOD_ID 0x130 2200 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B 2201 2202 /* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the 2203 * type field is excluded from the section when reading and writing from 2204 * a module using the module_typeid field with these AQ commands. 2205 */ 2206 struct ice_aqc_nvm_minsrev { 2207 __le16 length; 2208 __le16 validity; 2209 #define ICE_AQC_NVM_MINSREV_NVM_VALID BIT(0) 2210 #define ICE_AQC_NVM_MINSREV_OROM_VALID BIT(1) 2211 __le16 nvm_minsrev_l; 2212 __le16 nvm_minsrev_h; 2213 __le16 orom_minsrev_l; 2214 __le16 orom_minsrev_h; 2215 }; 2216 2217 struct ice_aqc_nvm_tx_topo_user_sel { 2218 __le16 length; 2219 u8 data; 2220 #define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4) 2221 u8 reserved; 2222 }; 2223 2224 /* Used for 0x0704 as well as for 0x0705 commands */ 2225 struct ice_aqc_nvm_cfg { 2226 u8 cmd_flags; 2227 #define ICE_AQC_ANVM_MULTIPLE_ELEMS BIT(0) 2228 #define ICE_AQC_ANVM_IMMEDIATE_FIELD BIT(1) 2229 #define ICE_AQC_ANVM_NEW_CFG BIT(2) 2230 u8 reserved; 2231 __le16 count; 2232 __le16 id; 2233 u8 reserved1[2]; 2234 __le32 addr_high; 2235 __le32 addr_low; 2236 }; 2237 2238 struct ice_aqc_nvm_cfg_data { 2239 __le16 field_id; 2240 __le16 field_options; 2241 __le16 field_value; 2242 }; 2243 2244 /* NVM Checksum Command (direct, 0x0706) */ 2245 struct ice_aqc_nvm_checksum { 2246 u8 flags; 2247 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0) 2248 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1) 2249 u8 rsvd; 2250 __le16 checksum; /* Used only by response */ 2251 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA 2252 u8 rsvd2[12]; 2253 }; 2254 2255 /* 2256 * Send to PF command (indirect 0x0801) ID is only used by PF 2257 * 2258 * Send to VF command (indirect 0x0802) ID is only used by PF 2259 * 2260 */ 2261 struct ice_aqc_pf_vf_msg { 2262 __le32 id; 2263 u32 reserved; 2264 __le32 addr_high; 2265 __le32 addr_low; 2266 }; 2267 2268 /* Write/Read Alternate - Direct (direct 0x0900/0x0902) */ 2269 struct ice_aqc_read_write_alt_direct { 2270 __le32 dword0_addr; 2271 __le32 dword0_value; 2272 __le32 dword1_addr; 2273 __le32 dword1_value; 2274 }; 2275 2276 /* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */ 2277 struct ice_aqc_read_write_alt_indirect { 2278 __le32 base_dword_addr; 2279 __le32 num_dwords; 2280 __le32 addr_high; 2281 __le32 addr_low; 2282 }; 2283 2284 /* Done Alternate Write (direct 0x0904) */ 2285 struct ice_aqc_done_alt_write { 2286 u8 flags; 2287 #define ICE_AQC_CMD_UEFI_BIOS_MODE BIT(0) 2288 #define ICE_AQC_RESP_RESET_NEEDED BIT(1) 2289 u8 reserved[15]; 2290 }; 2291 2292 /* Clear Port Alternate Write (direct 0x0906) */ 2293 struct ice_aqc_clear_port_alt_write { 2294 u8 reserved[16]; 2295 }; 2296 2297 /* Get LLDP MIB (indirect 0x0A00) 2298 * Note: This is also used by the LLDP MIB Change Event (0x0A01) 2299 * as the format is the same. 2300 */ 2301 struct ice_aqc_lldp_get_mib { 2302 u8 type; 2303 #define ICE_AQ_LLDP_MIB_TYPE_S 0 2304 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S) 2305 #define ICE_AQ_LLDP_MIB_LOCAL 0 2306 #define ICE_AQ_LLDP_MIB_REMOTE 1 2307 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2 2308 #define ICE_AQ_LLDP_BRID_TYPE_S 2 2309 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S) 2310 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0 2311 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1 2312 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */ 2313 #define ICE_AQ_LLDP_TX_S 0x4 2314 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S) 2315 #define ICE_AQ_LLDP_TX_ACTIVE 0 2316 #define ICE_AQ_LLDP_TX_SUSPENDED 1 2317 #define ICE_AQ_LLDP_TX_FLUSHED 3 2318 /* DCBX mode */ 2319 #define ICE_AQ_LLDP_DCBX_S 6 2320 #define ICE_AQ_LLDP_DCBX_M (0x3 << ICE_AQ_LLDP_DCBX_S) 2321 #define ICE_AQ_LLDP_DCBX_NA 0 2322 #define ICE_AQ_LLDP_DCBX_CEE 1 2323 #define ICE_AQ_LLDP_DCBX_IEEE 2 2324 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00) 2325 * and in the LLDP MIB Change Event (0x0A01). They are valid for the 2326 * Get LLDP MIB (0x0A00) response only. 2327 */ 2328 u8 state; 2329 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_S 0 2330 #define ICE_AQ_LLDP_MIB_CHANGE_STATE_M \ 2331 (0x1 << ICE_AQ_LLDP_MIB_CHANGE_STATE_S) 2332 #define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0 2333 #define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1 2334 __le16 local_len; 2335 __le16 remote_len; 2336 u8 reserved[2]; 2337 __le32 addr_high; 2338 __le32 addr_low; 2339 }; 2340 2341 /* Configure LLDP MIB Change Event (direct 0x0A01) */ 2342 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */ 2343 struct ice_aqc_lldp_set_mib_change { 2344 u8 command; 2345 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2346 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1 2347 #define ICE_AQ_LLDP_MIB_PENDING_S 1 2348 #define ICE_AQ_LLDP_MIB_PENDING_M \ 2349 (0x1 << ICE_AQ_LLDP_MIB_PENDING_S) 2350 #define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0 2351 #define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1 2352 u8 reserved[15]; 2353 }; 2354 2355 /* Add LLDP TLV (indirect 0x0A02) 2356 * Delete LLDP TLV (indirect 0x0A04) 2357 */ 2358 struct ice_aqc_lldp_add_delete_tlv { 2359 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2360 u8 reserved1[1]; 2361 __le16 len; 2362 u8 reserved2[4]; 2363 __le32 addr_high; 2364 __le32 addr_low; 2365 }; 2366 2367 /* Update LLDP TLV (indirect 0x0A03) */ 2368 struct ice_aqc_lldp_update_tlv { 2369 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2370 u8 reserved; 2371 __le16 old_len; 2372 __le16 new_offset; 2373 __le16 new_len; 2374 __le32 addr_high; 2375 __le32 addr_low; 2376 }; 2377 2378 /* Stop LLDP (direct 0x0A05) */ 2379 struct ice_aqc_lldp_stop { 2380 u8 command; 2381 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0) 2382 #define ICE_AQ_LLDP_AGENT_STOP 0x0 2383 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK 2384 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1) 2385 u8 reserved[15]; 2386 }; 2387 2388 /* Start LLDP (direct 0x0A06) */ 2389 struct ice_aqc_lldp_start { 2390 u8 command; 2391 #define ICE_AQ_LLDP_AGENT_START BIT(0) 2392 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1) 2393 u8 reserved[15]; 2394 }; 2395 2396 /* Get CEE DCBX Oper Config (0x0A07) 2397 * The command uses the generic descriptor struct and 2398 * returns the struct below as an indirect response. 2399 */ 2400 struct ice_aqc_get_cee_dcb_cfg_resp { 2401 u8 oper_num_tc; 2402 u8 oper_prio_tc[4]; 2403 u8 oper_tc_bw[8]; 2404 u8 oper_pfc_en; 2405 __le16 oper_app_prio; 2406 #define ICE_AQC_CEE_APP_FCOE_S 0 2407 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S) 2408 #define ICE_AQC_CEE_APP_ISCSI_S 3 2409 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S) 2410 #define ICE_AQC_CEE_APP_FIP_S 8 2411 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S) 2412 __le32 tlv_status; 2413 #define ICE_AQC_CEE_PG_STATUS_S 0 2414 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S) 2415 #define ICE_AQC_CEE_PFC_STATUS_S 3 2416 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S) 2417 #define ICE_AQC_CEE_FCOE_STATUS_S 8 2418 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S) 2419 #define ICE_AQC_CEE_ISCSI_STATUS_S 11 2420 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S) 2421 #define ICE_AQC_CEE_FIP_STATUS_S 16 2422 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S) 2423 u8 reserved[12]; 2424 }; 2425 2426 /* Set Local LLDP MIB (indirect 0x0A08) 2427 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX 2428 */ 2429 struct ice_aqc_lldp_set_local_mib { 2430 u8 type; 2431 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0) 2432 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0 2433 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1) 2434 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0 2435 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M 2436 u8 reserved0; 2437 __le16 length; 2438 u8 reserved1[4]; 2439 __le32 addr_high; 2440 __le32 addr_low; 2441 }; 2442 2443 struct ice_aqc_lldp_set_local_mib_resp { 2444 u8 status; 2445 #define SET_LOCAL_MIB_RESP_EVENT_M BIT(0) 2446 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_SILENT 0 2447 #define SET_LOCAL_MIB_RESP_MIB_CHANGE_EVENT SET_LOCAL_MIB_RESP_EVENT_M 2448 u8 reserved[15]; 2449 }; 2450 2451 /* Stop/Start LLDP Agent (direct 0x0A09) 2452 * Used for stopping/starting specific LLDP agent. e.g. DCBX. 2453 * The same structure is used for the response, with the command field 2454 * being used as the status field. 2455 */ 2456 struct ice_aqc_lldp_stop_start_specific_agent { 2457 u8 command; 2458 #define ICE_AQC_START_STOP_AGENT_M BIT(0) 2459 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0 2460 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M 2461 u8 reserved[15]; 2462 }; 2463 2464 /* LLDP Filter Control (direct 0x0A0A) */ 2465 struct ice_aqc_lldp_filter_ctrl { 2466 u8 cmd_flags; 2467 #define ICE_AQC_LLDP_FILTER_ACTION_M MAKEMASK(3, 0) 2468 #define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0 2469 #define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1 2470 #define ICE_AQC_LLDP_FILTER_ACTION_UPDATE 0x2 2471 u8 reserved1; 2472 __le16 vsi_num; 2473 u8 reserved2[12]; 2474 }; 2475 2476 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */ 2477 struct ice_aqc_get_set_rss_key { 2478 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15) 2479 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0 2480 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S) 2481 __le16 vsi_id; 2482 u8 reserved[6]; 2483 __le32 addr_high; 2484 __le32 addr_low; 2485 }; 2486 2487 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28 2488 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC 2489 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \ 2490 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \ 2491 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE) 2492 2493 /** 2494 * struct ice_aqc_get_set_rss_keys - Get/Set RSS hash key command buffer 2495 * @standard_rss_key: 40 most significant bytes of hash key 2496 * @extended_hash_key: 12 least significant bytes of hash key 2497 * 2498 * Set/Get 40 byte hash key using standard_rss_key field, and set 2499 * extended_hash_key field to zero. Set/Get 52 byte hash key using 2500 * standard_rss_key field for 40 most significant bytes and the 2501 * extended_hash_key field for the 12 least significant bytes of hash key. 2502 */ 2503 struct ice_aqc_get_set_rss_keys { 2504 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE]; 2505 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE]; 2506 }; 2507 2508 enum ice_lut_type { 2509 ICE_LUT_VSI = 0, 2510 ICE_LUT_PF = 1, 2511 ICE_LUT_GLOBAL = 2, 2512 ICE_LUT_TYPE_MASK = 3 2513 }; 2514 2515 enum ice_lut_size { 2516 ICE_LUT_VSI_SIZE = 64, 2517 ICE_LUT_GLOBAL_SIZE = 512, 2518 ICE_LUT_PF_SIZE = 2048, 2519 }; 2520 2521 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */ 2522 struct ice_aqc_get_set_rss_lut { 2523 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15) 2524 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0 2525 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S) 2526 __le16 vsi_id; 2527 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0 2528 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \ 2529 (ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) 2530 2531 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2 2532 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \ 2533 (ICE_LUT_TYPE_MASK << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) 2534 2535 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1 2536 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2 2537 2538 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4 2539 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \ 2540 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) 2541 2542 __le16 flags; 2543 __le32 reserved; 2544 __le32 addr_high; 2545 __le32 addr_low; 2546 }; 2547 2548 /* Add Tx LAN Queues (indirect 0x0C30) */ 2549 struct ice_aqc_add_txqs { 2550 u8 num_qgrps; 2551 u8 reserved[3]; 2552 __le32 reserved1; 2553 __le32 addr_high; 2554 __le32 addr_low; 2555 }; 2556 2557 /* This is the descriptor of each queue entry for the Add Tx LAN Queues 2558 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. 2559 */ 2560 struct ice_aqc_add_txqs_perq { 2561 __le16 txq_id; 2562 u8 rsvd[2]; 2563 __le32 q_teid; 2564 u8 txq_ctx[22]; 2565 u8 rsvd2[2]; 2566 struct ice_aqc_txsched_elem info; 2567 }; 2568 2569 /* The format of the command buffer for Add Tx LAN Queues (0x0C30) 2570 * is an array of the following structs. Please note that the length of 2571 * each struct ice_aqc_add_tx_qgrp is variable due 2572 * to the variable number of queues in each group! 2573 */ 2574 struct ice_aqc_add_tx_qgrp { 2575 __le32 parent_teid; 2576 u8 num_txqs; 2577 u8 rsvd[3]; 2578 struct ice_aqc_add_txqs_perq txqs[STRUCT_HACK_VAR_LEN]; 2579 }; 2580 2581 /* Disable Tx LAN Queues (indirect 0x0C31) */ 2582 struct ice_aqc_dis_txqs { 2583 u8 cmd_type; 2584 #define ICE_AQC_Q_DIS_CMD_S 0 2585 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) 2586 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) 2587 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) 2588 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) 2589 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) 2590 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) 2591 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) 2592 u8 num_entries; 2593 __le16 vmvf_and_timeout; 2594 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 2595 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) 2596 #define ICE_AQC_Q_DIS_TIMEOUT_S 10 2597 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) 2598 __le32 blocked_cgds; 2599 __le32 addr_high; 2600 __le32 addr_low; 2601 }; 2602 2603 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31) 2604 * contains the following structures, arrayed one after the 2605 * other. 2606 * Note: Since the q_id is 16 bits wide, if the 2607 * number of queues is even, then 2 bytes of alignment MUST be 2608 * added before the start of the next group, to allow correct 2609 * alignment of the parent_teid field. 2610 */ 2611 #pragma pack(1) 2612 struct ice_aqc_dis_txq_item { 2613 __le32 parent_teid; 2614 u8 num_qs; 2615 u8 rsvd; 2616 /* The length of the q_id array varies according to num_qs */ 2617 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 2618 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ 2619 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2620 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ 2621 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) 2622 __le16 q_id[STRUCT_HACK_VAR_LEN]; 2623 }; 2624 #pragma pack() 2625 2626 /* Tx LAN Queues Cleanup Event (0x0C31) */ 2627 struct ice_aqc_txqs_cleanup { 2628 __le16 caller_opc; 2629 __le16 cmd_tag; 2630 u8 reserved[12]; 2631 }; 2632 2633 /* Move / Reconfigure Tx Queues (indirect 0x0C32) */ 2634 struct ice_aqc_move_txqs { 2635 u8 cmd_type; 2636 #define ICE_AQC_Q_CMD_TYPE_S 0 2637 #define ICE_AQC_Q_CMD_TYPE_M (0x3 << ICE_AQC_Q_CMD_TYPE_S) 2638 #define ICE_AQC_Q_CMD_TYPE_MOVE 1 2639 #define ICE_AQC_Q_CMD_TYPE_TC_CHANGE 2 2640 #define ICE_AQC_Q_CMD_TYPE_MOVE_AND_TC 3 2641 #define ICE_AQC_Q_CMD_SUBSEQ_CALL BIT(2) 2642 #define ICE_AQC_Q_CMD_FLUSH_PIPE BIT(3) 2643 u8 num_qs; 2644 u8 rsvd; 2645 u8 timeout; 2646 #define ICE_AQC_Q_CMD_TIMEOUT_S 2 2647 #define ICE_AQC_Q_CMD_TIMEOUT_M (0x3F << ICE_AQC_Q_CMD_TIMEOUT_S) 2648 __le32 blocked_cgds; 2649 __le32 addr_high; 2650 __le32 addr_low; 2651 }; 2652 2653 /* Per-queue data buffer for the Move Tx LAN Queues command/response */ 2654 struct ice_aqc_move_txqs_elem { 2655 __le16 txq_id; 2656 u8 q_cgd; 2657 u8 rsvd; 2658 __le32 q_teid; 2659 }; 2660 2661 /* Indirect data buffer for the Move Tx LAN Queues command/response */ 2662 struct ice_aqc_move_txqs_data { 2663 __le32 src_teid; 2664 __le32 dest_teid; 2665 struct ice_aqc_move_txqs_elem txqs[STRUCT_HACK_VAR_LEN]; 2666 }; 2667 2668 /* Add Tx RDMA Queue Set (indirect 0x0C33) */ 2669 struct ice_aqc_add_rdma_qset { 2670 u8 num_qset_grps; 2671 u8 reserved[7]; 2672 __le32 addr_high; 2673 __le32 addr_low; 2674 }; 2675 2676 /* This is the descriptor of each qset entry for the Add Tx RDMA Queue Set 2677 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset. 2678 */ 2679 struct ice_aqc_add_tx_rdma_qset_entry { 2680 __le16 tx_qset_id; 2681 u8 rsvd[2]; 2682 __le32 qset_teid; 2683 struct ice_aqc_txsched_elem info; 2684 }; 2685 2686 /* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33) 2687 * is an array of the following structs. Please note that the length of 2688 * each struct ice_aqc_add_rdma_qset is variable due to the variable 2689 * number of queues in each group! 2690 */ 2691 struct ice_aqc_add_rdma_qset_data { 2692 __le32 parent_teid; 2693 __le16 num_qsets; 2694 u8 rsvd[2]; 2695 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[STRUCT_HACK_VAR_LEN]; 2696 }; 2697 2698 /* Move RDMA Queue Set (indirect 0x0C34) */ 2699 struct ice_aqc_move_rdma_qset_cmd { 2700 u8 num_rdma_qset; /* Used by commands and response */ 2701 #define ICE_AQC_PF_MODE_SAME_PF 0x0 2702 #define ICE_AQC_PF_MODE_GIVE_OWNERSHIP 0x1 2703 #define ICE_AQC_PF_MODE_KEEP_OWNERSHIP 0x2 2704 u8 flags; 2705 u8 reserved[6]; 2706 __le32 addr_high; 2707 __le32 addr_low; 2708 }; 2709 2710 /* Buffer */ 2711 struct ice_aqc_move_rdma_qset_buffer_desc { 2712 __le16 tx_qset_id; 2713 __le16 qset_teid; 2714 }; 2715 2716 struct ice_aqc_move_rdma_qset_buffer { 2717 __le32 src_parent_teid; 2718 __le32 dest_parent_teid; 2719 struct ice_aqc_move_rdma_qset_buffer_desc descs[STRUCT_HACK_VAR_LEN]; 2720 }; 2721 2722 /* Download Package (indirect 0x0C40) */ 2723 /* Also used for Update Package (indirect 0x0C41 and 0x0C42) */ 2724 struct ice_aqc_download_pkg { 2725 u8 flags; 2726 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01 2727 u8 reserved[3]; 2728 __le32 reserved1; 2729 __le32 addr_high; 2730 __le32 addr_low; 2731 }; 2732 2733 struct ice_aqc_download_pkg_resp { 2734 __le32 error_offset; 2735 __le32 error_info; 2736 __le32 addr_high; 2737 __le32 addr_low; 2738 }; 2739 2740 /* Get Package Info List (indirect 0x0C43) */ 2741 struct ice_aqc_get_pkg_info_list { 2742 __le32 reserved1; 2743 __le32 reserved2; 2744 __le32 addr_high; 2745 __le32 addr_low; 2746 }; 2747 2748 /* Version format for packages */ 2749 struct ice_pkg_ver { 2750 u8 major; 2751 u8 minor; 2752 u8 update; 2753 u8 draft; 2754 }; 2755 2756 #define ICE_PKG_NAME_SIZE 32 2757 #define ICE_SEG_ID_SIZE 28 2758 #define ICE_SEG_NAME_SIZE 28 2759 2760 struct ice_aqc_get_pkg_info { 2761 struct ice_pkg_ver ver; 2762 char name[ICE_SEG_NAME_SIZE]; 2763 __le32 track_id; 2764 u8 is_in_nvm; 2765 u8 is_active; 2766 u8 is_active_at_boot; 2767 u8 is_modified; 2768 }; 2769 2770 /* Get Package Info List response buffer format (0x0C43) */ 2771 struct ice_aqc_get_pkg_info_resp { 2772 __le32 count; 2773 struct ice_aqc_get_pkg_info pkg_info[STRUCT_HACK_VAR_LEN]; 2774 }; 2775 2776 /* Driver Shared Parameters (direct, 0x0C90) */ 2777 struct ice_aqc_driver_shared_params { 2778 u8 set_or_get_op; 2779 #define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0) 2780 #define ICE_AQC_DRIVER_PARAM_SET ((u8)0) 2781 #define ICE_AQC_DRIVER_PARAM_GET ((u8)1) 2782 u8 param_indx; 2783 #define ICE_AQC_DRIVER_PARAM_MAX_IDX 15 2784 u8 rsvd[2]; 2785 __le32 param_val; 2786 __le32 addr_high; 2787 __le32 addr_low; 2788 }; 2789 2790 /* Lan Queue Overflow Event (direct, 0x1001) */ 2791 struct ice_aqc_event_lan_overflow { 2792 __le32 prtdcb_ruptq; 2793 __le32 qtx_ctl; 2794 u8 reserved[8]; 2795 }; 2796 2797 /* Debug Dump Internal Data (indirect 0xFF08) */ 2798 struct ice_aqc_debug_dump_internals { 2799 u8 cluster_id; 2800 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0 2801 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2 2802 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3 2803 /* EMP_DRAM only dumpable in device debug mode */ 2804 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4 2805 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5 2806 /* AUX_REGS only dumpable in device debug mode */ 2807 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6 2808 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7 2809 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8 2810 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG 9 2811 #define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE 21 2812 u8 reserved; 2813 __le16 table_id; /* Used only for non-memory clusters */ 2814 __le32 idx; /* In table entries for tables, in bytes for memory */ 2815 __le32 addr_high; 2816 __le32 addr_low; 2817 }; 2818 2819 enum ice_aqc_fw_logging_mod { 2820 ICE_AQC_FW_LOG_ID_GENERAL = 0, 2821 ICE_AQC_FW_LOG_ID_CTRL, 2822 ICE_AQC_FW_LOG_ID_LINK, 2823 ICE_AQC_FW_LOG_ID_LINK_TOPO, 2824 ICE_AQC_FW_LOG_ID_DNL, 2825 ICE_AQC_FW_LOG_ID_I2C, 2826 ICE_AQC_FW_LOG_ID_SDP, 2827 ICE_AQC_FW_LOG_ID_MDIO, 2828 ICE_AQC_FW_LOG_ID_ADMINQ, 2829 ICE_AQC_FW_LOG_ID_HDMA, 2830 ICE_AQC_FW_LOG_ID_LLDP, 2831 ICE_AQC_FW_LOG_ID_DCBX, 2832 ICE_AQC_FW_LOG_ID_DCB, 2833 ICE_AQC_FW_LOG_ID_XLR, 2834 ICE_AQC_FW_LOG_ID_NVM, 2835 ICE_AQC_FW_LOG_ID_AUTH, 2836 ICE_AQC_FW_LOG_ID_VPD, 2837 ICE_AQC_FW_LOG_ID_IOSF, 2838 ICE_AQC_FW_LOG_ID_PARSER, 2839 ICE_AQC_FW_LOG_ID_SW, 2840 ICE_AQC_FW_LOG_ID_SCHEDULER, 2841 ICE_AQC_FW_LOG_ID_TXQ, 2842 ICE_AQC_FW_LOG_ID_RSVD, 2843 ICE_AQC_FW_LOG_ID_POST, 2844 ICE_AQC_FW_LOG_ID_WATCHDOG, 2845 ICE_AQC_FW_LOG_ID_TASK_DISPATCH, 2846 ICE_AQC_FW_LOG_ID_MNG, 2847 ICE_AQC_FW_LOG_ID_SYNCE, 2848 ICE_AQC_FW_LOG_ID_HEALTH, 2849 ICE_AQC_FW_LOG_ID_TSDRV, 2850 ICE_AQC_FW_LOG_ID_PFREG, 2851 ICE_AQC_FW_LOG_ID_MDLVER, 2852 ICE_AQC_FW_LOG_ID_MAX, 2853 }; 2854 2855 /* Set Health Status (direct 0xFF20) */ 2856 struct ice_aqc_set_health_status_config { 2857 u8 event_source; 2858 #define ICE_AQC_HEALTH_STATUS_SET_PF_SPECIFIC_MASK BIT(0) 2859 #define ICE_AQC_HEALTH_STATUS_SET_ALL_PF_MASK BIT(1) 2860 #define ICE_AQC_HEALTH_STATUS_SET_GLOBAL_MASK BIT(2) 2861 u8 reserved[15]; 2862 }; 2863 2864 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT 0x101 2865 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_TYPE 0x102 2866 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_QUAL 0x103 2867 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_COMM 0x104 2868 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_CONFLICT 0x105 2869 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106 2870 #define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107 2871 #define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108 2872 #define ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE 0x109 2873 #define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B 2874 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C 2875 #define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D 2876 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED 0x10F 2877 #define ICE_AQC_HEALTH_STATUS_ERR_PARALLEL_FAULT 0x110 2878 #define ICE_AQC_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED 0x111 2879 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST_TOPO 0x112 2880 #define ICE_AQC_HEALTH_STATUS_ERR_NETLIST 0x113 2881 #define ICE_AQC_HEALTH_STATUS_ERR_TOPO_CONFLICT 0x114 2882 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 2883 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 2884 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 2885 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120 2886 #define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121 2887 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 2888 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 2889 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 2890 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_AUTH 0x503 2891 #define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504 2892 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505 2893 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506 2894 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION 0x507 2895 #define ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION 0x508 2896 #define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509 2897 #define ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT 0x50A 2898 #define ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET 0x50B 2899 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL 0x50C 2900 #define ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL 0x50D 2901 #define ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP 0x1000 2902 #define ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL 0x1001 2903 #define ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ 0x1002 2904 2905 /* Get Health Status codes (indirect 0xFF21) */ 2906 struct ice_aqc_get_supported_health_status_codes { 2907 __le16 health_code_count; 2908 u8 reserved[6]; 2909 __le32 addr_high; 2910 __le32 addr_low; 2911 }; 2912 2913 /* Get Health Status (indirect 0xFF22) */ 2914 struct ice_aqc_get_health_status { 2915 __le16 health_status_count; 2916 u8 reserved[6]; 2917 __le32 addr_high; 2918 __le32 addr_low; 2919 }; 2920 2921 /* Get Health Status event buffer entry, (0xFF22) 2922 * repeated per reported health status 2923 */ 2924 struct ice_aqc_health_status_elem { 2925 __le16 health_status_code; 2926 __le16 event_source; 2927 #define ICE_AQC_HEALTH_STATUS_PF (0x1) 2928 #define ICE_AQC_HEALTH_STATUS_PORT (0x2) 2929 #define ICE_AQC_HEALTH_STATUS_GLOBAL (0x3) 2930 __le32 internal_data1; 2931 #define ICE_AQC_HEALTH_STATUS_UNDEFINED_DATA (0xDEADBEEF) 2932 __le32 internal_data2; 2933 }; 2934 2935 /* Clear Health Status (direct 0xFF23) */ 2936 struct ice_aqc_clear_health_status { 2937 __le32 reserved[4]; 2938 }; 2939 2940 /* Set FW Logging configuration (indirect 0xFF30) 2941 * Register for FW Logging (indirect 0xFF31) 2942 * Query FW Logging (indirect 0xFF32) 2943 * FW Log Event (indirect 0xFF33) 2944 * Get FW Log (indirect 0xFF34) 2945 * Clear FW Log (indirect 0xFF35) 2946 */ 2947 struct ice_aqc_fw_log { 2948 u8 cmd_flags; 2949 #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) 2950 #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) 2951 #define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) 2952 #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) 2953 #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) 2954 #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) 2955 #define ICE_AQC_FW_LOG_PERSISTENT BIT(0) 2956 u8 rsp_flag; 2957 #define ICE_AQC_FW_LOG_MORE_DATA BIT(1) 2958 __le16 fw_rt_msb; 2959 union { 2960 struct { 2961 __le32 fw_rt_lsb; 2962 } sync; 2963 struct { 2964 __le16 log_resolution; 2965 #define ICE_AQC_FW_LOG_MIN_RESOLUTION (1) 2966 #define ICE_AQC_FW_LOG_MAX_RESOLUTION (128) 2967 __le16 mdl_cnt; 2968 } cfg; 2969 } ops; 2970 __le32 addr_high; 2971 __le32 addr_low; 2972 }; 2973 2974 /* Response Buffer for: 2975 * Set Firmware Logging Configuration (0xFF30) 2976 * Query FW Logging (0xFF32) 2977 */ 2978 struct ice_aqc_fw_log_cfg_resp { 2979 __le16 module_identifier; 2980 u8 log_level; 2981 u8 rsvd0; 2982 }; 2983 2984 /** 2985 * struct ice_aq_desc - Admin Queue (AQ) descriptor 2986 * @flags: ICE_AQ_FLAG_* flags 2987 * @opcode: AQ command opcode 2988 * @datalen: length in bytes of indirect/external data buffer 2989 * @retval: return value from firmware 2990 * @cookie_high: opaque data high-half 2991 * @cookie_low: opaque data low-half 2992 * @params: command-specific parameters 2993 * 2994 * Descriptor format for commands the driver posts on the Admin Transmit Queue 2995 * (ATQ). The firmware writes back onto the command descriptor and returns 2996 * the result of the command. Asynchronous events that are not an immediate 2997 * result of the command are written to the Admin Receive Queue (ARQ) using 2998 * the same descriptor format. Descriptors are in little-endian notation with 2999 * 32-bit words. 3000 */ 3001 struct ice_aq_desc { 3002 __le16 flags; 3003 __le16 opcode; 3004 __le16 datalen; 3005 __le16 retval; 3006 __le32 cookie_high; 3007 __le32 cookie_low; 3008 union { 3009 u8 raw[16]; 3010 struct ice_aqc_generic generic; 3011 struct ice_aqc_get_ver get_ver; 3012 struct ice_aqc_driver_ver driver_ver; 3013 struct ice_aqc_q_shutdown q_shutdown; 3014 struct ice_aqc_get_exp_err exp_err; 3015 struct ice_aqc_req_res res_owner; 3016 struct ice_aqc_manage_mac_read mac_read; 3017 struct ice_aqc_manage_mac_write mac_write; 3018 struct ice_aqc_clear_pxe clear_pxe; 3019 struct ice_aqc_config_no_drop_policy no_drop; 3020 struct ice_aqc_add_update_mir_rule add_update_rule; 3021 struct ice_aqc_delete_mir_rule del_rule; 3022 struct ice_aqc_list_caps get_cap; 3023 struct ice_aqc_get_phy_caps get_phy; 3024 struct ice_aqc_set_phy_cfg set_phy; 3025 struct ice_aqc_restart_an restart_an; 3026 struct ice_aqc_get_sensor_reading get_sensor_reading; 3027 struct ice_aqc_get_sensor_reading_resp get_sensor_reading_resp; 3028 struct ice_aqc_dnl_get_status get_status; 3029 struct ice_aqc_dnl_run_command dnl_run; 3030 struct ice_aqc_dnl_call_command dnl_call; 3031 struct ice_aqc_dnl_read_write_command dnl_read_write; 3032 struct ice_aqc_dnl_read_write_response dnl_read_write_resp; 3033 struct ice_aqc_dnl_set_breakpoints_command dnl_set_brk; 3034 struct ice_aqc_dnl_read_log_command dnl_read_log; 3035 struct ice_aqc_dnl_read_log_response dnl_read_log_resp; 3036 struct ice_aqc_i2c read_write_i2c; 3037 struct ice_aqc_read_i2c_resp read_i2c_resp; 3038 struct ice_aqc_mdio read_write_mdio; 3039 struct ice_aqc_gpio_by_func read_write_gpio_by_func; 3040 struct ice_aqc_gpio read_write_gpio; 3041 struct ice_aqc_sw_gpio sw_read_write_gpio; 3042 struct ice_aqc_set_led set_led; 3043 struct ice_aqc_mdio read_mdio; 3044 struct ice_aqc_mdio write_mdio; 3045 struct ice_aqc_sff_eeprom read_write_sff_param; 3046 struct ice_aqc_set_port_id_led set_port_id_led; 3047 struct ice_aqc_get_port_options get_port_options; 3048 struct ice_aqc_set_port_option set_port_option; 3049 struct ice_aqc_get_sw_cfg get_sw_conf; 3050 struct ice_aqc_set_port_params set_port_params; 3051 struct ice_aqc_sw_rules sw_rules; 3052 struct ice_aqc_storm_cfg storm_conf; 3053 struct ice_aqc_get_topo get_topo; 3054 struct ice_aqc_sched_elem_cmd sched_elem_cmd; 3055 struct ice_aqc_query_txsched_res query_sched_res; 3056 struct ice_aqc_query_node_to_root query_node_to_root; 3057 struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd; 3058 struct ice_aqc_query_port_ets port_ets; 3059 struct ice_aqc_rl_profile rl_profile; 3060 struct ice_aqc_node_attr node_attr; 3061 struct ice_aqc_nvm nvm; 3062 struct ice_aqc_nvm_cfg nvm_cfg; 3063 struct ice_aqc_nvm_checksum nvm_checksum; 3064 struct ice_aqc_pf_vf_msg virt; 3065 struct ice_aqc_read_write_alt_direct read_write_alt_direct; 3066 struct ice_aqc_read_write_alt_indirect read_write_alt_indirect; 3067 struct ice_aqc_done_alt_write done_alt_write; 3068 struct ice_aqc_clear_port_alt_write clear_port_alt_write; 3069 struct ice_aqc_pfc_ignore pfc_ignore; 3070 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode; 3071 struct ice_aqc_set_dcb_params set_dcb_params; 3072 struct ice_aqc_lldp_get_mib lldp_get_mib; 3073 struct ice_aqc_lldp_set_mib_change lldp_set_event; 3074 struct ice_aqc_lldp_add_delete_tlv lldp_add_delete_tlv; 3075 struct ice_aqc_lldp_update_tlv lldp_update_tlv; 3076 struct ice_aqc_lldp_stop lldp_stop; 3077 struct ice_aqc_lldp_start lldp_start; 3078 struct ice_aqc_lldp_set_local_mib lldp_set_mib; 3079 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl; 3080 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; 3081 struct ice_aqc_get_set_rss_lut get_set_rss_lut; 3082 struct ice_aqc_get_set_rss_key get_set_rss_key; 3083 struct ice_aqc_add_txqs add_txqs; 3084 struct ice_aqc_dis_txqs dis_txqs; 3085 struct ice_aqc_move_txqs move_txqs; 3086 struct ice_aqc_add_rdma_qset add_rdma_qset; 3087 struct ice_aqc_move_rdma_qset_cmd move_rdma_qset; 3088 struct ice_aqc_txqs_cleanup txqs_cleanup; 3089 struct ice_aqc_add_get_update_free_vsi vsi_cmd; 3090 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res; 3091 struct ice_aqc_get_vsi_resp get_vsi_resp; 3092 struct ice_aqc_download_pkg download_pkg; 3093 struct ice_aqc_get_pkg_info_list get_pkg_info_list; 3094 struct ice_aqc_driver_shared_params drv_shared_params; 3095 struct ice_aqc_fw_log fw_log; 3096 struct ice_aqc_debug_dump_internals debug_dump; 3097 struct ice_aqc_set_mac_lb set_mac_lb; 3098 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; 3099 struct ice_aqc_get_res_alloc get_res; 3100 struct ice_aqc_get_allocd_res_desc get_res_desc; 3101 struct ice_aqc_set_mac_cfg set_mac_cfg; 3102 struct ice_aqc_set_event_mask set_event_mask; 3103 struct ice_aqc_get_link_status get_link_status; 3104 struct ice_aqc_event_lan_overflow lan_overflow; 3105 struct ice_aqc_get_link_topo get_link_topo; 3106 struct ice_aqc_set_health_status_config 3107 set_health_status_config; 3108 struct ice_aqc_get_supported_health_status_codes 3109 get_supported_health_status_codes; 3110 struct ice_aqc_get_health_status get_health_status; 3111 struct ice_aqc_clear_health_status clear_health_status; 3112 struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm; 3113 struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm; 3114 struct ice_aqc_get_set_tx_topo get_set_tx_topo; 3115 } params; 3116 }; 3117 3118 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ 3119 #define ICE_AQ_LG_BUF 512 3120 3121 /* Flags sub-structure 3122 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 3123 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 3124 */ 3125 3126 /* command flags and offsets */ 3127 #define ICE_AQ_FLAG_DD_S 0 3128 #define ICE_AQ_FLAG_CMP_S 1 3129 #define ICE_AQ_FLAG_ERR_S 2 3130 #define ICE_AQ_FLAG_VFE_S 3 3131 #define ICE_AQ_FLAG_LB_S 9 3132 #define ICE_AQ_FLAG_RD_S 10 3133 #define ICE_AQ_FLAG_VFC_S 11 3134 #define ICE_AQ_FLAG_BUF_S 12 3135 #define ICE_AQ_FLAG_SI_S 13 3136 #define ICE_AQ_FLAG_EI_S 14 3137 #define ICE_AQ_FLAG_FE_S 15 3138 3139 #define ICE_AQ_FLAG_DD BIT(ICE_AQ_FLAG_DD_S) /* 0x1 */ 3140 #define ICE_AQ_FLAG_CMP BIT(ICE_AQ_FLAG_CMP_S) /* 0x2 */ 3141 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ 3142 #define ICE_AQ_FLAG_VFE BIT(ICE_AQ_FLAG_VFE_S) /* 0x8 */ 3143 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ 3144 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ 3145 #define ICE_AQ_FLAG_VFC BIT(ICE_AQ_FLAG_VFC_S) /* 0x800 */ 3146 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ 3147 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ 3148 #define ICE_AQ_FLAG_EI BIT(ICE_AQ_FLAG_EI_S) /* 0x4000 */ 3149 #define ICE_AQ_FLAG_FE BIT(ICE_AQ_FLAG_FE_S) /* 0x8000 */ 3150 3151 /* error codes */ 3152 enum ice_aq_err { 3153 ICE_AQ_RC_OK = 0, /* Success */ 3154 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */ 3155 ICE_AQ_RC_ENOENT = 2, /* No such element */ 3156 ICE_AQ_RC_ESRCH = 3, /* Bad opcode */ 3157 ICE_AQ_RC_EINTR = 4, /* Operation interrupted */ 3158 ICE_AQ_RC_EIO = 5, /* I/O error */ 3159 ICE_AQ_RC_ENXIO = 6, /* No such resource */ 3160 ICE_AQ_RC_E2BIG = 7, /* Arg too long */ 3161 ICE_AQ_RC_EAGAIN = 8, /* Try again */ 3162 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ 3163 ICE_AQ_RC_EACCES = 10, /* Permission denied */ 3164 ICE_AQ_RC_EFAULT = 11, /* Bad address */ 3165 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ 3166 ICE_AQ_RC_EEXIST = 13, /* Object already exists */ 3167 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */ 3168 ICE_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 3169 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */ 3170 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */ 3171 ICE_AQ_RC_ERANGE = 18, /* Parameter out of range */ 3172 ICE_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 3173 ICE_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 3174 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 3175 ICE_AQ_RC_EFBIG = 22, /* File too big */ 3176 ICE_AQ_RC_ESBCOMP = 23, /* SB-IOSF completion unsuccessful */ 3177 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */ 3178 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */ 3179 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */ 3180 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */ 3181 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */ 3182 ICE_AQ_RC_EACCES_BMCU = 29, /* BMC Update in progress */ 3183 }; 3184 3185 /* Admin Queue command opcodes */ 3186 enum ice_adminq_opc { 3187 /* AQ commands */ 3188 ice_aqc_opc_get_ver = 0x0001, 3189 ice_aqc_opc_driver_ver = 0x0002, 3190 ice_aqc_opc_q_shutdown = 0x0003, 3191 ice_aqc_opc_get_exp_err = 0x0005, 3192 3193 /* resource ownership */ 3194 ice_aqc_opc_req_res = 0x0008, 3195 ice_aqc_opc_release_res = 0x0009, 3196 3197 /* device/function capabilities */ 3198 ice_aqc_opc_list_func_caps = 0x000A, 3199 ice_aqc_opc_list_dev_caps = 0x000B, 3200 3201 /* manage MAC address */ 3202 ice_aqc_opc_manage_mac_read = 0x0107, 3203 ice_aqc_opc_manage_mac_write = 0x0108, 3204 3205 /* PXE */ 3206 ice_aqc_opc_clear_pxe_mode = 0x0110, 3207 3208 ice_aqc_opc_config_no_drop_policy = 0x0112, 3209 3210 /* internal switch commands */ 3211 ice_aqc_opc_get_sw_cfg = 0x0200, 3212 ice_aqc_opc_set_port_params = 0x0203, 3213 3214 /* Alloc/Free/Get Resources */ 3215 ice_aqc_opc_get_res_alloc = 0x0204, 3216 ice_aqc_opc_alloc_res = 0x0208, 3217 ice_aqc_opc_free_res = 0x0209, 3218 ice_aqc_opc_get_allocd_res_desc = 0x020A, 3219 ice_aqc_opc_set_vlan_mode_parameters = 0x020C, 3220 ice_aqc_opc_get_vlan_mode_parameters = 0x020D, 3221 3222 /* VSI commands */ 3223 ice_aqc_opc_add_vsi = 0x0210, 3224 ice_aqc_opc_update_vsi = 0x0211, 3225 ice_aqc_opc_get_vsi_params = 0x0212, 3226 ice_aqc_opc_free_vsi = 0x0213, 3227 3228 /* Mirroring rules - add/update, delete */ 3229 ice_aqc_opc_add_update_mir_rule = 0x0260, 3230 ice_aqc_opc_del_mir_rule = 0x0261, 3231 3232 /* storm configuration */ 3233 ice_aqc_opc_set_storm_cfg = 0x0280, 3234 ice_aqc_opc_get_storm_cfg = 0x0281, 3235 3236 /* switch rules population commands */ 3237 ice_aqc_opc_add_sw_rules = 0x02A0, 3238 ice_aqc_opc_update_sw_rules = 0x02A1, 3239 ice_aqc_opc_remove_sw_rules = 0x02A2, 3240 ice_aqc_opc_get_sw_rules = 0x02A3, 3241 ice_aqc_opc_clear_pf_cfg = 0x02A4, 3242 3243 /* DCB commands */ 3244 ice_aqc_opc_pfc_ignore = 0x0301, 3245 ice_aqc_opc_query_pfc_mode = 0x0302, 3246 ice_aqc_opc_set_pfc_mode = 0x0303, 3247 ice_aqc_opc_set_dcb_params = 0x0306, 3248 3249 /* transmit scheduler commands */ 3250 ice_aqc_opc_get_dflt_topo = 0x0400, 3251 ice_aqc_opc_add_sched_elems = 0x0401, 3252 ice_aqc_opc_cfg_sched_elems = 0x0403, 3253 ice_aqc_opc_get_sched_elems = 0x0404, 3254 ice_aqc_opc_move_sched_elems = 0x0408, 3255 ice_aqc_opc_suspend_sched_elems = 0x0409, 3256 ice_aqc_opc_resume_sched_elems = 0x040A, 3257 ice_aqc_opc_query_port_ets = 0x040E, 3258 ice_aqc_opc_delete_sched_elems = 0x040F, 3259 ice_aqc_opc_add_rl_profiles = 0x0410, 3260 ice_aqc_opc_query_rl_profiles = 0x0411, 3261 ice_aqc_opc_query_sched_res = 0x0412, 3262 ice_aqc_opc_query_node_to_root = 0x0413, 3263 ice_aqc_opc_cfg_l2_node_cgd = 0x0414, 3264 ice_aqc_opc_remove_rl_profiles = 0x0415, 3265 ice_aqc_opc_set_tx_topo = 0x0417, 3266 ice_aqc_opc_get_tx_topo = 0x0418, 3267 ice_aqc_opc_cfg_node_attr = 0x0419, 3268 ice_aqc_opc_query_node_attr = 0x041A, 3269 3270 /* PHY commands */ 3271 ice_aqc_opc_get_phy_caps = 0x0600, 3272 ice_aqc_opc_set_phy_cfg = 0x0601, 3273 ice_aqc_opc_set_mac_cfg = 0x0603, 3274 ice_aqc_opc_restart_an = 0x0605, 3275 ice_aqc_opc_get_link_status = 0x0607, 3276 ice_aqc_opc_set_event_mask = 0x0613, 3277 ice_aqc_opc_set_mac_lb = 0x0620, 3278 ice_aqc_opc_get_sensor_reading = 0x0632, 3279 ice_aqc_opc_dnl_get_status = 0x0680, 3280 ice_aqc_opc_dnl_run = 0x0681, 3281 ice_aqc_opc_dnl_call = 0x0682, 3282 ice_aqc_opc_dnl_read_sto = 0x0683, 3283 ice_aqc_opc_dnl_write_sto = 0x0684, 3284 ice_aqc_opc_dnl_set_breakpoints = 0x0686, 3285 ice_aqc_opc_dnl_read_log = 0x0687, 3286 ice_aqc_opc_get_link_topo = 0x06E0, 3287 ice_aqc_opc_read_i2c = 0x06E2, 3288 ice_aqc_opc_write_i2c = 0x06E3, 3289 ice_aqc_opc_read_mdio = 0x06E4, 3290 ice_aqc_opc_write_mdio = 0x06E5, 3291 ice_aqc_opc_set_gpio_by_func = 0x06E6, 3292 ice_aqc_opc_get_gpio_by_func = 0x06E7, 3293 ice_aqc_opc_set_led = 0x06E8, 3294 ice_aqc_opc_set_port_id_led = 0x06E9, 3295 ice_aqc_opc_get_port_options = 0x06EA, 3296 ice_aqc_opc_set_port_option = 0x06EB, 3297 ice_aqc_opc_set_gpio = 0x06EC, 3298 ice_aqc_opc_get_gpio = 0x06ED, 3299 ice_aqc_opc_sff_eeprom = 0x06EE, 3300 ice_aqc_opc_sw_set_gpio = 0x06EF, 3301 ice_aqc_opc_sw_get_gpio = 0x06F0, 3302 ice_aqc_opc_prog_topo_dev_nvm = 0x06F2, 3303 ice_aqc_opc_read_topo_dev_nvm = 0x06F3, 3304 3305 /* NVM commands */ 3306 ice_aqc_opc_nvm_read = 0x0701, 3307 ice_aqc_opc_nvm_erase = 0x0702, 3308 ice_aqc_opc_nvm_write = 0x0703, 3309 ice_aqc_opc_nvm_cfg_read = 0x0704, 3310 ice_aqc_opc_nvm_cfg_write = 0x0705, 3311 ice_aqc_opc_nvm_checksum = 0x0706, 3312 ice_aqc_opc_nvm_write_activate = 0x0707, 3313 ice_aqc_opc_nvm_sr_dump = 0x0707, 3314 ice_aqc_opc_nvm_save_factory_settings = 0x0708, 3315 ice_aqc_opc_nvm_update_empr = 0x0709, 3316 ice_aqc_opc_nvm_pkg_data = 0x070A, 3317 ice_aqc_opc_nvm_pass_component_tbl = 0x070B, 3318 3319 /* PF/VF mailbox commands */ 3320 ice_mbx_opc_send_msg_to_pf = 0x0801, 3321 ice_mbx_opc_send_msg_to_vf = 0x0802, 3322 /* Alternate Structure Commands */ 3323 ice_aqc_opc_write_alt_direct = 0x0900, 3324 ice_aqc_opc_write_alt_indirect = 0x0901, 3325 ice_aqc_opc_read_alt_direct = 0x0902, 3326 ice_aqc_opc_read_alt_indirect = 0x0903, 3327 ice_aqc_opc_done_alt_write = 0x0904, 3328 ice_aqc_opc_clear_port_alt_write = 0x0906, 3329 /* LLDP commands */ 3330 ice_aqc_opc_lldp_get_mib = 0x0A00, 3331 ice_aqc_opc_lldp_set_mib_change = 0x0A01, 3332 ice_aqc_opc_lldp_add_tlv = 0x0A02, 3333 ice_aqc_opc_lldp_update_tlv = 0x0A03, 3334 ice_aqc_opc_lldp_delete_tlv = 0x0A04, 3335 ice_aqc_opc_lldp_stop = 0x0A05, 3336 ice_aqc_opc_lldp_start = 0x0A06, 3337 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07, 3338 ice_aqc_opc_lldp_set_local_mib = 0x0A08, 3339 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09, 3340 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A, 3341 ice_execute_pending_lldp_mib = 0x0A0B, 3342 3343 /* RSS commands */ 3344 ice_aqc_opc_set_rss_key = 0x0B02, 3345 ice_aqc_opc_set_rss_lut = 0x0B03, 3346 ice_aqc_opc_get_rss_key = 0x0B04, 3347 ice_aqc_opc_get_rss_lut = 0x0B05, 3348 3349 /* Tx queue handling commands/events */ 3350 ice_aqc_opc_add_txqs = 0x0C30, 3351 ice_aqc_opc_dis_txqs = 0x0C31, 3352 ice_aqc_opc_txqs_cleanup = 0x0C31, 3353 ice_aqc_opc_move_recfg_txqs = 0x0C32, 3354 ice_aqc_opc_add_rdma_qset = 0x0C33, 3355 ice_aqc_opc_move_rdma_qset = 0x0C34, 3356 3357 /* package commands */ 3358 ice_aqc_opc_download_pkg = 0x0C40, 3359 ice_aqc_opc_upload_section = 0x0C41, 3360 ice_aqc_opc_update_pkg = 0x0C42, 3361 ice_aqc_opc_get_pkg_info_list = 0x0C43, 3362 3363 ice_aqc_opc_driver_shared_params = 0x0C90, 3364 3365 /* Standalone Commands/Events */ 3366 ice_aqc_opc_event_lan_overflow = 0x1001, 3367 3368 /* debug commands */ 3369 ice_aqc_opc_debug_dump_internals = 0xFF08, 3370 3371 /* SystemDiagnostic commands */ 3372 ice_aqc_opc_set_health_status_config = 0xFF20, 3373 ice_aqc_opc_get_supported_health_status_codes = 0xFF21, 3374 ice_aqc_opc_get_health_status = 0xFF22, 3375 ice_aqc_opc_clear_health_status = 0xFF23, 3376 3377 /* FW Logging Commands */ 3378 ice_aqc_opc_fw_logs_config = 0xFF30, 3379 ice_aqc_opc_fw_logs_register = 0xFF31, 3380 ice_aqc_opc_fw_logs_query = 0xFF32, 3381 ice_aqc_opc_fw_logs_event = 0xFF33, 3382 ice_aqc_opc_fw_logs_get = 0xFF34, 3383 ice_aqc_opc_fw_logs_clear = 0xFF35 3384 }; 3385 3386 #endif /* _ICE_ADMINQ_CMD_H_ */ 3387