1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 /* 34 * NS8250... UART registers. 35 */ 36 37 /* 8250 registers #[0-6]. */ 38 39 #define com_data 0 /* data register (R/W) */ 40 #define REG_DATA com_data 41 42 #define com_ier 1 /* interrupt enable register (W) */ 43 #define REG_IER com_ier 44 #define IER_ERXRDY 0x1 45 #define IER_ETXRDY 0x2 46 #define IER_ERLS 0x4 47 #define IER_EMSC 0x8 48 49 #define com_iir 2 /* interrupt identification register (R) */ 50 #define REG_IIR com_iir 51 #define IIR_IMASK 0xf 52 #define IIR_RXTOUT 0xc 53 #define IIR_RLS 0x6 54 #define IIR_RXRDY 0x4 55 #define IIR_TXRDY 0x2 56 #define IIR_NOPEND 0x1 57 #define IIR_MLSC 0x0 58 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 59 60 #define com_lcr 3 /* line control register (R/W) */ 61 #define com_cfcr com_lcr /* character format control register (R/W) */ 62 #define REG_LCR com_lcr 63 #define LCR_DLAB 0x80 64 #define CFCR_DLAB LCR_DLAB 65 #define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 66 #define CFCR_EFR_ENABLE LCR_EFR_ENABLE 67 #define LCR_SBREAK 0x40 68 #define CFCR_SBREAK LCR_SBREAK 69 #define LCR_PZERO 0x30 70 #define CFCR_PZERO LCR_PZERO 71 #define LCR_PONE 0x20 72 #define CFCR_PONE LCR_PONE 73 #define LCR_PEVEN 0x10 74 #define CFCR_PEVEN LCR_PEVEN 75 #define LCR_PODD 0x00 76 #define CFCR_PODD LCR_PODD 77 #define LCR_PENAB 0x08 78 #define CFCR_PENAB LCR_PENAB 79 #define LCR_STOPB 0x04 80 #define CFCR_STOPB LCR_STOPB 81 #define LCR_8BITS 0x03 82 #define CFCR_8BITS LCR_8BITS 83 #define LCR_7BITS 0x02 84 #define CFCR_7BITS LCR_7BITS 85 #define LCR_6BITS 0x01 86 #define CFCR_6BITS LCR_6BITS 87 #define LCR_5BITS 0x00 88 #define CFCR_5BITS LCR_5BITS 89 90 #define com_mcr 4 /* modem control register (R/W) */ 91 #define REG_MCR com_mcr 92 #define MCR_PRESCALE 0x80 /* only available on 16650 up */ 93 #define MCR_LOOPBACK 0x10 94 #define MCR_IE 0x08 95 #define MCR_IENABLE MCR_IE 96 #define MCR_DRS 0x04 97 #define MCR_RTS 0x02 98 #define MCR_DTR 0x01 99 100 #define com_lsr 5 /* line status register (R/W) */ 101 #define REG_LSR com_lsr 102 #define LSR_RCV_FIFO 0x80 103 #define LSR_TEMT 0x40 104 #define LSR_TSRE LSR_TEMT 105 #define LSR_THRE 0x20 106 #define LSR_TXRDY LSR_THRE 107 #define LSR_BI 0x10 108 #define LSR_FE 0x08 109 #define LSR_PE 0x04 110 #define LSR_OE 0x02 111 #define LSR_RXRDY 0x01 112 #define LSR_RCV_MASK 0x1f 113 114 #define com_msr 6 /* modem status register (R/W) */ 115 #define REG_MSR com_msr 116 #define MSR_DCD 0x80 117 #define MSR_RI 0x40 118 #define MSR_DSR 0x20 119 #define MSR_CTS 0x10 120 #define MSR_DDCD 0x08 121 #define MSR_TERI 0x04 122 #define MSR_DDSR 0x02 123 #define MSR_DCTS 0x01 124 125 /* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 126 #define com_dll 0 /* divisor latch low (R/W) */ 127 #define com_dlbl com_dll 128 #define com_dlm 1 /* divisor latch high (R/W) */ 129 #define com_dlbh com_dlm 130 #define REG_DLL com_dll 131 #define REG_DLH com_dlm 132 133 /* 16450 register #7. Not multiplexed. */ 134 #define com_scr 7 /* scratch register (R/W) */ 135 136 /* 16550 register #2. Not multiplexed. */ 137 #define com_fcr 2 /* FIFO control register (W) */ 138 #define com_fifo com_fcr 139 #define REG_FCR com_fcr 140 #define FCR_ENABLE 0x01 141 #define FIFO_ENABLE FCR_ENABLE 142 #define FCR_RCV_RST 0x02 143 #define FIFO_RCV_RST FCR_RCV_RST 144 #define FCR_XMT_RST 0x04 145 #define FIFO_XMT_RST FCR_XMT_RST 146 #define FCR_DMA 0x08 147 #define FIFO_DMA_MODE FCR_DMA 148 #define FCR_RX_LOW 0x00 149 #define FIFO_RX_LOW FCR_RX_LOW 150 #define FCR_RX_MEDL 0x40 151 #define FIFO_RX_MEDL FCR_RX_MEDL 152 #define FCR_RX_MEDH 0x80 153 #define FIFO_RX_MEDH FCR_RX_MEDH 154 #define FCR_RX_HIGH 0xc0 155 #define FIFO_RX_HIGH FCR_RX_HIGH 156 157 /* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 158 159 #define com_efr 2 /* enhanced features register (R/W) */ 160 #define REG_EFR com_efr 161 #define EFR_CTS 0x80 162 #define EFR_AUTOCTS EFR_CTS 163 #define EFR_RTS 0x40 164 #define EFR_AUTORTS EFR_RTS 165 #define EFR_EFE 0x10 /* enhanced functions enable */ 166 167 #define com_xon1 4 /* XON 1 character (R/W) */ 168 #define com_xon2 5 /* XON 2 character (R/W) */ 169 #define com_xoff1 6 /* XOFF 1 character (R/W) */ 170 #define com_xoff2 7 /* XOFF 2 character (R/W) */ 171 172 /* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 173 #define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 174 175 /* 16950 register #3. R/W access enabled by ACR[7]. */ 176 #define com_rfl 3 /* receiver fifo level (R) */ 177 178 /* 179 * 16950 register #4. Access enabled by ACR[7]. Also requires 180 * !LCR_EFR_ENABLE. 181 */ 182 #define com_tfl 4 /* transmitter fifo level (R) */ 183 184 /* 185 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 186 * requires ACR[6]. 187 */ 188 #define com_icr 5 /* index control register (R/W) */ 189 190 /* 191 * 16950 register #7. It is the same as com_scr except it has a different 192 * abbreviation in the manufacturer's data sheet and it also serves as an 193 * index into the Indexed Control register set. 194 */ 195 #define com_spr com_scr /* scratch pad (and index) register (R/W) */ 196 #define REG_SPR com_scr 197 198 /* 199 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 200 * data in ICR (if ICR is accessible). 201 */ 202 203 #define com_acr 0 /* additional control register (R/W) */ 204 #define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 205 #define ACR_ICRE 0x40 /* ICR enable */ 206 #define ACR_TLE 0x20 /* TTL/RTL enable */ 207 208 #define com_cpr 1 /* clock prescaler register (R/W) */ 209 #define com_tcr 2 /* times clock register (R/W) */ 210 #define com_ttl 4 /* transmitter trigger level (R/W) */ 211 #define com_rtl 5 /* receiver trigger level (R/W) */ 212 /* ... */ 213 214 /* Hardware extension mode register for RSB-2000/3000. */ 215 #define com_emr com_msr 216 #define EMR_EXBUFF 0x04 217 #define EMR_CTSFLW 0x08 218 #define EMR_DSRFLW 0x10 219 #define EMR_RTSFLW 0x20 220 #define EMR_DTRFLW 0x40 221 #define EMR_EFMODE 0x80 222