1 /*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 4. Neither the name of the University nor the names of its contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 30 * $FreeBSD$ 31 */ 32 33 /* 34 * NS8250... UART registers. 35 */ 36 37 /* 8250 registers #[0-6]. */ 38 39 #define com_data 0 /* data register (R/W) */ 40 #define REG_DATA com_data 41 42 #define com_ier 1 /* interrupt enable register (W) */ 43 #define REG_IER com_ier 44 #define IER_ERXRDY 0x1 45 #define IER_ETXRDY 0x2 46 #define IER_ERLS 0x4 47 #define IER_EMSC 0x8 48 /* 49 * Receive timeout interrupt enable. 50 * Implemented in Intel XScale, Ingenic XBurst. 51 */ 52 #define IER_RXTMOUT 0x10 53 54 #define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC\5RXTMOUT" 55 56 #define com_iir 2 /* interrupt identification register (R) */ 57 #define REG_IIR com_iir 58 #define IIR_IMASK 0xf 59 #define IIR_RXTOUT 0xc 60 #define IIR_BUSY 0x7 61 #define IIR_RLS 0x6 62 #define IIR_RXRDY 0x4 63 #define IIR_TXRDY 0x2 64 #define IIR_NOPEND 0x1 65 #define IIR_MLSC 0x0 66 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 67 68 #define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY" 69 70 #define com_lcr 3 /* line control register (R/W) */ 71 #define com_cfcr com_lcr /* character format control register (R/W) */ 72 #define REG_LCR com_lcr 73 #define LCR_DLAB 0x80 74 #define CFCR_DLAB LCR_DLAB 75 #define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 76 #define CFCR_EFR_ENABLE LCR_EFR_ENABLE 77 #define LCR_SBREAK 0x40 78 #define CFCR_SBREAK LCR_SBREAK 79 #define LCR_PZERO 0x30 80 #define CFCR_PZERO LCR_PZERO 81 #define LCR_PONE 0x20 82 #define CFCR_PONE LCR_PONE 83 #define LCR_PEVEN 0x10 84 #define CFCR_PEVEN LCR_PEVEN 85 #define LCR_PODD 0x00 86 #define CFCR_PODD LCR_PODD 87 #define LCR_PENAB 0x08 88 #define CFCR_PENAB LCR_PENAB 89 #define LCR_STOPB 0x04 90 #define CFCR_STOPB LCR_STOPB 91 #define LCR_8BITS 0x03 92 #define CFCR_8BITS LCR_8BITS 93 #define LCR_7BITS 0x02 94 #define CFCR_7BITS LCR_7BITS 95 #define LCR_6BITS 0x01 96 #define CFCR_6BITS LCR_6BITS 97 #define LCR_5BITS 0x00 98 #define CFCR_5BITS LCR_5BITS 99 100 #define com_mcr 4 /* modem control register (R/W) */ 101 #define REG_MCR com_mcr 102 #define MCR_PRESCALE 0x80 /* only available on 16650 up */ 103 #define MCR_LOOPBACK 0x10 104 #define MCR_IE 0x08 105 #define MCR_IENABLE MCR_IE 106 #define MCR_DRS 0x04 107 #define MCR_RTS 0x02 108 #define MCR_DTR 0x01 109 110 #define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE" 111 112 #define com_lsr 5 /* line status register (R/W) */ 113 #define REG_LSR com_lsr 114 #define LSR_RCV_FIFO 0x80 115 #define LSR_TEMT 0x40 116 #define LSR_TSRE LSR_TEMT 117 #define LSR_THRE 0x20 118 #define LSR_TXRDY LSR_THRE 119 #define LSR_BI 0x10 120 #define LSR_FE 0x08 121 #define LSR_PE 0x04 122 #define LSR_OE 0x02 123 #define LSR_RXRDY 0x01 124 #define LSR_RCV_MASK 0x1f 125 126 #define LSR_BITS "\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO" 127 128 #define com_msr 6 /* modem status register (R/W) */ 129 #define REG_MSR com_msr 130 #define MSR_DCD 0x80 131 #define MSR_RI 0x40 132 #define MSR_DSR 0x20 133 #define MSR_CTS 0x10 134 #define MSR_DDCD 0x08 135 #define MSR_TERI 0x04 136 #define MSR_DDSR 0x02 137 #define MSR_DCTS 0x01 138 139 #define MSR_BITS "\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD" 140 141 /* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 142 #define com_dll 0 /* divisor latch low (R/W) */ 143 #define com_dlbl com_dll 144 #define com_dlm 1 /* divisor latch high (R/W) */ 145 #define com_dlbh com_dlm 146 #define REG_DLL com_dll 147 #define REG_DLH com_dlm 148 149 /* 16450 register #7. Not multiplexed. */ 150 #define com_scr 7 /* scratch register (R/W) */ 151 152 /* 16550 register #2. Not multiplexed. */ 153 #define com_fcr 2 /* FIFO control register (W) */ 154 #define com_fifo com_fcr 155 #define REG_FCR com_fcr 156 #define FCR_ENABLE 0x01 157 #define FIFO_ENABLE FCR_ENABLE 158 #define FCR_RCV_RST 0x02 159 #define FIFO_RCV_RST FCR_RCV_RST 160 #define FCR_XMT_RST 0x04 161 #define FIFO_XMT_RST FCR_XMT_RST 162 #define FCR_DMA 0x08 163 #define FIFO_DMA_MODE FCR_DMA 164 #ifdef CPU_XBURST 165 #define FCR_UART_ON 0x10 166 #endif 167 #define FCR_RX_LOW 0x00 168 #define FIFO_RX_LOW FCR_RX_LOW 169 #define FCR_RX_MEDL 0x40 170 #define FIFO_RX_MEDL FCR_RX_MEDL 171 #define FCR_RX_MEDH 0x80 172 #define FIFO_RX_MEDH FCR_RX_MEDH 173 #define FCR_RX_HIGH 0xc0 174 #define FIFO_RX_HIGH FCR_RX_HIGH 175 176 #define FCR_BITS "\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA" 177 178 /* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 179 180 #define com_efr 2 /* enhanced features register (R/W) */ 181 #define REG_EFR com_efr 182 #define EFR_CTS 0x80 183 #define EFR_AUTOCTS EFR_CTS 184 #define EFR_RTS 0x40 185 #define EFR_AUTORTS EFR_RTS 186 #define EFR_EFE 0x10 /* enhanced functions enable */ 187 188 #define com_xon1 4 /* XON 1 character (R/W) */ 189 #define com_xon2 5 /* XON 2 character (R/W) */ 190 #define com_xoff1 6 /* XOFF 1 character (R/W) */ 191 #define com_xoff2 7 /* XOFF 2 character (R/W) */ 192 193 #define DW_REG_USR 31 /* DesignWare derived Uart Status Reg */ 194 #define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */ 195 #define REG_USR com_usr 196 #define USR_BUSY 1 /* Uart Busy. Serial transfer in progress */ 197 #define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */ 198 199 /* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 200 #define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 201 202 /* 16950 register #3. R/W access enabled by ACR[7]. */ 203 #define com_rfl 3 /* receiver fifo level (R) */ 204 205 /* 206 * 16950 register #4. Access enabled by ACR[7]. Also requires 207 * !LCR_EFR_ENABLE. 208 */ 209 #define com_tfl 4 /* transmitter fifo level (R) */ 210 211 /* 212 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 213 * requires ACR[6]. 214 */ 215 #define com_icr 5 /* index control register (R/W) */ 216 #define REG_ICR com_icr 217 218 /* 219 * 16950 register #7. It is the same as com_scr except it has a different 220 * abbreviation in the manufacturer's data sheet and it also serves as an 221 * index into the Indexed Control register set. 222 */ 223 #define com_spr com_scr /* scratch pad (and index) register (R/W) */ 224 #define REG_SPR com_scr 225 226 /* 227 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 228 * data in ICR (if ICR is accessible). 229 */ 230 231 #define com_acr 0 /* additional control register (R/W) */ 232 #define REG_ACR com_acr 233 #define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 234 #define ACR_ICRE 0x40 /* ICR enable */ 235 #define ACR_TLE 0x20 /* TTL/RTL enable */ 236 237 #define com_cpr 1 /* clock prescaler register (R/W) */ 238 #define com_tcr 2 /* times clock register (R/W) */ 239 #define com_ttl 4 /* transmitter trigger level (R/W) */ 240 #define com_rtl 5 /* receiver trigger level (R/W) */ 241 /* ... */ 242 243 /* Hardware extension mode register for RSB-2000/3000. */ 244 #define com_emr com_msr 245 #define EMR_EXBUFF 0x04 246 #define EMR_CTSFLW 0x08 247 #define EMR_DSRFLW 0x10 248 #define EMR_RTSFLW 0x20 249 #define EMR_DTRFLW 0x40 250 #define EMR_EFMODE 0x80 251