1 /*- 2 * Copyright (c) 2010 Fabien Thomas 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Uncore PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #include <machine/apicvar.h> 42 #include <machine/cpu.h> 43 #include <machine/cpufunc.h> 44 #include <machine/specialreg.h> 45 46 #define UCF_PMC_CAPS \ 47 (PMC_CAP_READ | PMC_CAP_WRITE) 48 49 #define UCP_PMC_CAPS \ 50 (PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 51 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 52 53 #define SELECTSEL(x) \ 54 (((x) == PMC_CPU_INTEL_SANDYBRIDGE) ? UCP_CB0_EVSEL0 : UCP_EVSEL0) 55 56 #define SELECTOFF(x) \ 57 (((x) == PMC_CPU_INTEL_SANDYBRIDGE) ? UCF_OFFSET_SB : UCF_OFFSET) 58 59 static enum pmc_cputype uncore_cputype; 60 61 struct uncore_cpu { 62 volatile uint32_t pc_resync; 63 volatile uint32_t pc_ucfctrl; /* Fixed function control. */ 64 volatile uint64_t pc_globalctrl; /* Global control register. */ 65 struct pmc_hw pc_uncorepmcs[]; 66 }; 67 68 static struct uncore_cpu **uncore_pcpu; 69 70 static uint64_t uncore_pmcmask; 71 72 static int uncore_ucf_ri; /* relative index of fixed counters */ 73 static int uncore_ucf_width; 74 static int uncore_ucf_npmc; 75 76 static int uncore_ucp_width; 77 static int uncore_ucp_npmc; 78 79 static int 80 uncore_pcpu_noop(struct pmc_mdep *md, int cpu) 81 { 82 (void) md; 83 (void) cpu; 84 return (0); 85 } 86 87 static int 88 uncore_pcpu_init(struct pmc_mdep *md, int cpu) 89 { 90 struct pmc_cpu *pc; 91 struct uncore_cpu *cc; 92 struct pmc_hw *phw; 93 int uncore_ri, n, npmc; 94 95 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 96 ("[ucf,%d] insane cpu number %d", __LINE__, cpu)); 97 98 PMCDBG(MDP,INI,1,"uncore-init cpu=%d", cpu); 99 100 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; 101 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; 102 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; 103 104 cc = malloc(sizeof(struct uncore_cpu) + npmc * sizeof(struct pmc_hw), 105 M_PMC, M_WAITOK | M_ZERO); 106 107 uncore_pcpu[cpu] = cc; 108 pc = pmc_pcpu[cpu]; 109 110 KASSERT(pc != NULL && cc != NULL, 111 ("[uncore,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 112 113 for (n = 0, phw = cc->pc_uncorepmcs; n < npmc; n++, phw++) { 114 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 115 PMC_PHW_CPU_TO_STATE(cpu) | 116 PMC_PHW_INDEX_TO_STATE(n + uncore_ri); 117 phw->phw_pmc = NULL; 118 pc->pc_hwpmcs[n + uncore_ri] = phw; 119 } 120 121 return (0); 122 } 123 124 static int 125 uncore_pcpu_fini(struct pmc_mdep *md, int cpu) 126 { 127 int uncore_ri, n, npmc; 128 struct pmc_cpu *pc; 129 struct uncore_cpu *cc; 130 131 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 132 ("[uncore,%d] insane cpu number (%d)", __LINE__, cpu)); 133 134 PMCDBG(MDP,INI,1,"uncore-pcpu-fini cpu=%d", cpu); 135 136 if ((cc = uncore_pcpu[cpu]) == NULL) 137 return (0); 138 139 uncore_pcpu[cpu] = NULL; 140 141 pc = pmc_pcpu[cpu]; 142 143 KASSERT(pc != NULL, ("[uncore,%d] NULL per-cpu %d state", __LINE__, 144 cpu)); 145 146 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; 147 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; 148 149 for (n = 0; n < npmc; n++) 150 wrmsr(SELECTSEL(uncore_cputype) + n, 0); 151 152 wrmsr(UCF_CTRL, 0); 153 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; 154 155 for (n = 0; n < npmc; n++) 156 pc->pc_hwpmcs[n + uncore_ri] = NULL; 157 158 free(cc, M_PMC); 159 160 return (0); 161 } 162 163 /* 164 * Fixed function counters. 165 */ 166 167 static pmc_value_t 168 ucf_perfctr_value_to_reload_count(pmc_value_t v) 169 { 170 v &= (1ULL << uncore_ucf_width) - 1; 171 return (1ULL << uncore_ucf_width) - v; 172 } 173 174 static pmc_value_t 175 ucf_reload_count_to_perfctr_value(pmc_value_t rlc) 176 { 177 return (1ULL << uncore_ucf_width) - rlc; 178 } 179 180 static int 181 ucf_allocate_pmc(int cpu, int ri, struct pmc *pm, 182 const struct pmc_op_pmcallocate *a) 183 { 184 enum pmc_event ev; 185 uint32_t caps, flags; 186 187 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 188 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 189 190 PMCDBG(MDP,ALL,1, "ucf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 191 192 if (ri < 0 || ri > uncore_ucf_npmc) 193 return (EINVAL); 194 195 caps = a->pm_caps; 196 197 if (a->pm_class != PMC_CLASS_UCF || 198 (caps & UCF_PMC_CAPS) != caps) 199 return (EINVAL); 200 201 ev = pm->pm_event; 202 if (ev < PMC_EV_UCF_FIRST || ev > PMC_EV_UCF_LAST) 203 return (EINVAL); 204 205 flags = UCF_EN; 206 207 pm->pm_md.pm_ucf.pm_ucf_ctrl = (flags << (ri * 4)); 208 209 PMCDBG(MDP,ALL,2, "ucf-allocate config=0x%jx", 210 (uintmax_t) pm->pm_md.pm_ucf.pm_ucf_ctrl); 211 212 return (0); 213 } 214 215 static int 216 ucf_config_pmc(int cpu, int ri, struct pmc *pm) 217 { 218 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 219 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 220 221 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 222 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 223 224 PMCDBG(MDP,CFG,1, "ucf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 225 226 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, 227 cpu)); 228 229 uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc = pm; 230 231 return (0); 232 } 233 234 static int 235 ucf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 236 { 237 int error; 238 struct pmc_hw *phw; 239 char ucf_name[PMC_NAME_MAX]; 240 241 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri]; 242 243 (void) snprintf(ucf_name, sizeof(ucf_name), "UCF-%d", ri); 244 if ((error = copystr(ucf_name, pi->pm_name, PMC_NAME_MAX, 245 NULL)) != 0) 246 return (error); 247 248 pi->pm_class = PMC_CLASS_UCF; 249 250 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 251 pi->pm_enabled = TRUE; 252 *ppmc = phw->phw_pmc; 253 } else { 254 pi->pm_enabled = FALSE; 255 *ppmc = NULL; 256 } 257 258 return (0); 259 } 260 261 static int 262 ucf_get_config(int cpu, int ri, struct pmc **ppm) 263 { 264 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 265 266 return (0); 267 } 268 269 static int 270 ucf_read_pmc(int cpu, int ri, pmc_value_t *v) 271 { 272 struct pmc *pm; 273 pmc_value_t tmp; 274 275 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 276 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 277 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 278 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 279 280 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 281 282 KASSERT(pm, 283 ("[uncore,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 284 ri, ri + uncore_ucf_ri)); 285 286 tmp = rdmsr(UCF_CTR0 + ri); 287 288 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 289 *v = ucf_perfctr_value_to_reload_count(tmp); 290 else 291 *v = tmp; 292 293 PMCDBG(MDP,REA,1, "ucf-read cpu=%d ri=%d -> v=%jx", cpu, ri, *v); 294 295 return (0); 296 } 297 298 static int 299 ucf_release_pmc(int cpu, int ri, struct pmc *pmc) 300 { 301 PMCDBG(MDP,REL,1, "ucf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 302 303 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 304 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 305 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 306 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 307 308 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc == NULL, 309 ("[uncore,%d] PHW pmc non-NULL", __LINE__)); 310 311 return (0); 312 } 313 314 static int 315 ucf_start_pmc(int cpu, int ri) 316 { 317 struct pmc *pm; 318 struct uncore_cpu *ucfc; 319 320 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 321 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 322 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 323 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 324 325 PMCDBG(MDP,STA,1,"ucf-start cpu=%d ri=%d", cpu, ri); 326 327 ucfc = uncore_pcpu[cpu]; 328 pm = ucfc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 329 330 ucfc->pc_ucfctrl |= pm->pm_md.pm_ucf.pm_ucf_ctrl; 331 332 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); 333 334 do { 335 ucfc->pc_resync = 0; 336 ucfc->pc_globalctrl |= (1ULL << (ri + SELECTOFF(uncore_cputype))); 337 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); 338 } while (ucfc->pc_resync != 0); 339 340 PMCDBG(MDP,STA,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", 341 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), 342 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); 343 344 return (0); 345 } 346 347 static int 348 ucf_stop_pmc(int cpu, int ri) 349 { 350 uint32_t fc; 351 struct uncore_cpu *ucfc; 352 353 PMCDBG(MDP,STO,1,"ucf-stop cpu=%d ri=%d", cpu, ri); 354 355 ucfc = uncore_pcpu[cpu]; 356 357 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 358 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 359 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 360 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 361 362 fc = (UCF_MASK << (ri * 4)); 363 364 ucfc->pc_ucfctrl &= ~fc; 365 366 PMCDBG(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl); 367 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); 368 369 do { 370 ucfc->pc_resync = 0; 371 ucfc->pc_globalctrl &= ~(1ULL << (ri + SELECTOFF(uncore_cputype))); 372 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); 373 } while (ucfc->pc_resync != 0); 374 375 PMCDBG(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", 376 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), 377 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); 378 379 return (0); 380 } 381 382 static int 383 ucf_write_pmc(int cpu, int ri, pmc_value_t v) 384 { 385 struct uncore_cpu *cc; 386 struct pmc *pm; 387 388 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 389 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 390 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 391 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 392 393 cc = uncore_pcpu[cpu]; 394 pm = cc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 395 396 KASSERT(pm, 397 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 398 399 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 400 v = ucf_reload_count_to_perfctr_value(v); 401 402 wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */ 403 wrmsr(UCF_CTR0 + ri, v); 404 wrmsr(UCF_CTRL, cc->pc_ucfctrl); 405 406 PMCDBG(MDP,WRI,1, "ucf-write cpu=%d ri=%d v=%jx ucfctrl=%jx ", 407 cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL)); 408 409 return (0); 410 } 411 412 413 static void 414 ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 415 { 416 struct pmc_classdep *pcd; 417 418 KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__)); 419 420 PMCDBG(MDP,INI,1, "%s", "ucf-initialize"); 421 422 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF]; 423 424 pcd->pcd_caps = UCF_PMC_CAPS; 425 pcd->pcd_class = PMC_CLASS_UCF; 426 pcd->pcd_num = npmc; 427 pcd->pcd_ri = md->pmd_npmc; 428 pcd->pcd_width = pmcwidth; 429 430 pcd->pcd_allocate_pmc = ucf_allocate_pmc; 431 pcd->pcd_config_pmc = ucf_config_pmc; 432 pcd->pcd_describe = ucf_describe; 433 pcd->pcd_get_config = ucf_get_config; 434 pcd->pcd_get_msr = NULL; 435 pcd->pcd_pcpu_fini = uncore_pcpu_noop; 436 pcd->pcd_pcpu_init = uncore_pcpu_noop; 437 pcd->pcd_read_pmc = ucf_read_pmc; 438 pcd->pcd_release_pmc = ucf_release_pmc; 439 pcd->pcd_start_pmc = ucf_start_pmc; 440 pcd->pcd_stop_pmc = ucf_stop_pmc; 441 pcd->pcd_write_pmc = ucf_write_pmc; 442 443 md->pmd_npmc += npmc; 444 } 445 446 /* 447 * Intel programmable PMCs. 448 */ 449 450 /* 451 * Event descriptor tables. 452 * 453 * For each event id, we track: 454 * 455 * 1. The CPUs that the event is valid for. 456 * 457 * 2. If the event uses a fixed UMASK, the value of the umask field. 458 * If the event doesn't use a fixed UMASK, a mask of legal bits 459 * to check against. 460 */ 461 462 struct ucp_event_descr { 463 enum pmc_event ucp_ev; 464 unsigned char ucp_evcode; 465 unsigned char ucp_umask; 466 unsigned char ucp_flags; 467 }; 468 469 #define UCP_F_I7 (1 << 0) /* CPU: Core i7 */ 470 #define UCP_F_WM (1 << 1) /* CPU: Westmere */ 471 #define UCP_F_SB (1 << 2) /* CPU: Sandy Bridge */ 472 #define UCP_F_FM (1 << 3) /* Fixed mask */ 473 474 #define UCP_F_ALLCPUS \ 475 (UCP_F_I7 | UCP_F_WM) 476 477 #define UCP_F_CMASK 0xFF000000 478 479 static struct ucp_event_descr ucp_events[] = { 480 #undef UCPDESCR 481 #define UCPDESCR(N,EV,UM,FLAGS) { \ 482 .ucp_ev = PMC_EV_UCP_EVENT_##N, \ 483 .ucp_evcode = (EV), \ 484 .ucp_umask = (UM), \ 485 .ucp_flags = (FLAGS) \ 486 } 487 488 UCPDESCR(00H_01H, 0x00, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 489 UCPDESCR(00H_02H, 0x00, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 490 UCPDESCR(00H_04H, 0x00, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 491 492 UCPDESCR(01H_01H, 0x01, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 493 UCPDESCR(01H_02H, 0x01, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 494 UCPDESCR(01H_04H, 0x01, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 495 496 UCPDESCR(02H_01H, 0x02, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 497 UCPDESCR(03H_01H, 0x03, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 498 UCPDESCR(03H_02H, 0x03, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 499 UCPDESCR(03H_04H, 0x03, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 500 UCPDESCR(03H_08H, 0x03, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 501 UCPDESCR(03H_10H, 0x03, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 502 UCPDESCR(03H_20H, 0x03, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 503 UCPDESCR(03H_40H, 0x03, 0x40, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 504 505 UCPDESCR(04H_01H, 0x04, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 506 UCPDESCR(04H_02H, 0x04, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 507 UCPDESCR(04H_04H, 0x04, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 508 UCPDESCR(04H_08H, 0x04, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 509 UCPDESCR(04H_10H, 0x04, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 510 511 UCPDESCR(05H_01H, 0x05, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 512 UCPDESCR(05H_02H, 0x05, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 513 UCPDESCR(05H_04H, 0x05, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 514 515 UCPDESCR(06H_01H, 0x06, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 516 UCPDESCR(06H_02H, 0x06, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 517 UCPDESCR(06H_04H, 0x06, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 518 UCPDESCR(06H_08H, 0x06, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 519 UCPDESCR(06H_10H, 0x06, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 520 UCPDESCR(06H_20H, 0x06, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 521 522 UCPDESCR(07H_01H, 0x07, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 523 UCPDESCR(07H_02H, 0x07, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 524 UCPDESCR(07H_04H, 0x07, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 525 UCPDESCR(07H_08H, 0x07, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 526 UCPDESCR(07H_10H, 0x07, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 527 UCPDESCR(07H_20H, 0x07, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 528 UCPDESCR(07H_24H, 0x07, 0x24, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 529 530 UCPDESCR(08H_01H, 0x08, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 531 UCPDESCR(08H_02H, 0x08, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 532 UCPDESCR(08H_04H, 0x08, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 533 UCPDESCR(08H_03H, 0x08, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 534 535 UCPDESCR(09H_01H, 0x09, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 536 UCPDESCR(09H_02H, 0x09, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 537 UCPDESCR(09H_04H, 0x09, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 538 UCPDESCR(09H_03H, 0x09, 0x03, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 539 540 UCPDESCR(0AH_01H, 0x0A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 541 UCPDESCR(0AH_02H, 0x0A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 542 UCPDESCR(0AH_04H, 0x0A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 543 UCPDESCR(0AH_08H, 0x0A, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 544 UCPDESCR(0AH_0FH, 0x0A, 0x0F, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 545 546 UCPDESCR(0BH_01H, 0x0B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 547 UCPDESCR(0BH_02H, 0x0B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 548 UCPDESCR(0BH_04H, 0x0B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 549 UCPDESCR(0BH_08H, 0x0B, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 550 UCPDESCR(0BH_10H, 0x0B, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 551 UCPDESCR(0BH_1FH, 0x0B, 0x1F, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 552 553 UCPDESCR(0CH_01H, 0x0C, 0x01, UCP_F_FM | UCP_F_WM), 554 UCPDESCR(0CH_02H, 0x0C, 0x02, UCP_F_FM | UCP_F_WM), 555 UCPDESCR(0CH_04H_E, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 556 UCPDESCR(0CH_04H_F, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 557 UCPDESCR(0CH_04H_M, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 558 UCPDESCR(0CH_04H_S, 0x0C, 0x04, UCP_F_FM | UCP_F_WM), 559 UCPDESCR(0CH_08H_E, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 560 UCPDESCR(0CH_08H_F, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 561 UCPDESCR(0CH_08H_M, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 562 UCPDESCR(0CH_08H_S, 0x0C, 0x08, UCP_F_FM | UCP_F_WM), 563 564 UCPDESCR(20H_01H, 0x20, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 565 UCPDESCR(20H_02H, 0x20, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 566 UCPDESCR(20H_04H, 0x20, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 567 UCPDESCR(20H_08H, 0x20, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 568 UCPDESCR(20H_10H, 0x20, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 569 UCPDESCR(20H_20H, 0x20, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 570 571 UCPDESCR(21H_01H, 0x21, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 572 UCPDESCR(21H_02H, 0x21, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 573 UCPDESCR(21H_04H, 0x21, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 574 575 UCPDESCR(22H_01H, 0x22, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM | 576 UCP_F_SB), 577 UCPDESCR(22H_02H, 0x22, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM | 578 UCP_F_SB), 579 UCPDESCR(22H_04H, 0x22, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM | 580 UCP_F_SB), 581 UCPDESCR(22H_08H, 0x22, 0x08, UCP_F_FM | UCP_F_SB), 582 UCPDESCR(22H_20H, 0x22, 0x20, UCP_F_FM | UCP_F_SB), 583 UCPDESCR(22H_40H, 0x22, 0x40, UCP_F_FM | UCP_F_SB), 584 UCPDESCR(22H_80H, 0x22, 0x80, UCP_F_FM | UCP_F_SB), 585 586 UCPDESCR(23H_01H, 0x23, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 587 UCPDESCR(23H_02H, 0x23, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 588 UCPDESCR(23H_04H, 0x23, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 589 590 UCPDESCR(24H_02H, 0x24, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 591 UCPDESCR(24H_04H, 0x24, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 592 593 UCPDESCR(25H_01H, 0x25, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 594 UCPDESCR(25H_02H, 0x25, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 595 UCPDESCR(25H_04H, 0x25, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 596 597 UCPDESCR(26H_01H, 0x26, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 598 599 UCPDESCR(27H_01H, 0x27, 0x01, UCP_F_FM | UCP_F_I7), 600 UCPDESCR(27H_02H, 0x27, 0x02, UCP_F_FM | UCP_F_I7), 601 UCPDESCR(27H_04H, 0x27, 0x04, UCP_F_FM | UCP_F_I7), 602 UCPDESCR(27H_08H, 0x27, 0x08, UCP_F_FM | UCP_F_I7), 603 UCPDESCR(27H_10H, 0x27, 0x10, UCP_F_FM | UCP_F_I7), 604 UCPDESCR(27H_20H, 0x27, 0x20, UCP_F_FM | UCP_F_I7), 605 606 UCPDESCR(28H_01H, 0x28, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 607 UCPDESCR(28H_02H, 0x28, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 608 UCPDESCR(28H_04H, 0x28, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 609 UCPDESCR(28H_08H, 0x28, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 610 UCPDESCR(28H_10H, 0x28, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 611 UCPDESCR(28H_20H, 0x28, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 612 613 UCPDESCR(29H_01H, 0x29, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 614 UCPDESCR(29H_02H, 0x29, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 615 UCPDESCR(29H_04H, 0x29, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 616 UCPDESCR(29H_08H, 0x29, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 617 UCPDESCR(29H_10H, 0x29, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 618 UCPDESCR(29H_20H, 0x29, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 619 620 UCPDESCR(2AH_01H, 0x2A, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 621 UCPDESCR(2AH_02H, 0x2A, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 622 UCPDESCR(2AH_04H, 0x2A, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 623 UCPDESCR(2AH_07H, 0x2A, 0x07, UCP_F_FM | UCP_F_WM), 624 625 UCPDESCR(2BH_01H, 0x2B, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 626 UCPDESCR(2BH_02H, 0x2B, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 627 UCPDESCR(2BH_04H, 0x2B, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 628 UCPDESCR(2BH_07H, 0x2B, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 629 630 UCPDESCR(2CH_01H, 0x2C, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 631 UCPDESCR(2CH_02H, 0x2C, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 632 UCPDESCR(2CH_04H, 0x2C, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 633 UCPDESCR(2CH_07H, 0x2C, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 634 635 UCPDESCR(2DH_01H, 0x2D, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 636 UCPDESCR(2DH_02H, 0x2D, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 637 UCPDESCR(2DH_04H, 0x2D, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 638 UCPDESCR(2DH_07H, 0x2D, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 639 640 UCPDESCR(2EH_01H, 0x2E, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 641 UCPDESCR(2EH_02H, 0x2E, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 642 UCPDESCR(2EH_04H, 0x2E, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 643 UCPDESCR(2EH_07H, 0x2E, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 644 645 UCPDESCR(2FH_01H, 0x2F, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 646 UCPDESCR(2FH_02H, 0x2F, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 647 UCPDESCR(2FH_04H, 0x2F, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 648 UCPDESCR(2FH_07H, 0x2F, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 649 UCPDESCR(2FH_08H, 0x2F, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 650 UCPDESCR(2FH_10H, 0x2F, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 651 UCPDESCR(2FH_20H, 0x2F, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 652 UCPDESCR(2FH_38H, 0x2F, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 653 654 UCPDESCR(30H_01H, 0x30, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 655 UCPDESCR(30H_02H, 0x30, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 656 UCPDESCR(30H_04H, 0x30, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 657 UCPDESCR(30H_07H, 0x30, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 658 659 UCPDESCR(31H_01H, 0x31, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 660 UCPDESCR(31H_02H, 0x31, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 661 UCPDESCR(31H_04H, 0x31, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 662 UCPDESCR(31H_07H, 0x31, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 663 664 UCPDESCR(32H_01H, 0x32, 0x01, UCP_F_FM | UCP_F_WM), 665 UCPDESCR(32H_02H, 0x32, 0x02, UCP_F_FM | UCP_F_WM), 666 UCPDESCR(32H_04H, 0x32, 0x04, UCP_F_FM | UCP_F_WM), 667 UCPDESCR(32H_07H, 0x32, 0x07, UCP_F_FM | UCP_F_WM), 668 669 UCPDESCR(33H_01H, 0x33, 0x01, UCP_F_FM | UCP_F_WM), 670 UCPDESCR(33H_02H, 0x33, 0x02, UCP_F_FM | UCP_F_WM), 671 UCPDESCR(33H_04H, 0x33, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 672 UCPDESCR(33H_07H, 0x33, 0x07, UCP_F_FM | UCP_F_WM), 673 674 UCPDESCR(34H_01H, 0x34, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), 675 UCPDESCR(34H_02H, 0x34, 0x02, UCP_F_FM | UCP_F_WM | UCP_F_SB), 676 UCPDESCR(34H_04H, 0x34, 0x04, UCP_F_FM | UCP_F_WM | UCP_F_SB), 677 UCPDESCR(34H_08H, 0x34, 0x08, UCP_F_FM | UCP_F_WM | UCP_F_SB), 678 UCPDESCR(34H_10H, 0x34, 0x10, UCP_F_FM | UCP_F_WM | UCP_F_SB), 679 UCPDESCR(34H_20H, 0x34, 0x20, UCP_F_FM | UCP_F_WM | UCP_F_SB), 680 UCPDESCR(34H_40H, 0x34, 0x40, UCP_F_FM | UCP_F_SB), 681 UCPDESCR(34H_80H, 0x34, 0x80, UCP_F_FM | UCP_F_SB), 682 683 UCPDESCR(35H_01H, 0x35, 0x01, UCP_F_FM | UCP_F_WM), 684 UCPDESCR(35H_02H, 0x35, 0x02, UCP_F_FM | UCP_F_WM), 685 UCPDESCR(35H_04H, 0x35, 0x04, UCP_F_FM | UCP_F_WM), 686 687 UCPDESCR(40H_01H, 0x40, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 688 UCPDESCR(40H_02H, 0x40, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 689 UCPDESCR(40H_04H, 0x40, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 690 UCPDESCR(40H_08H, 0x40, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 691 UCPDESCR(40H_10H, 0x40, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 692 UCPDESCR(40H_20H, 0x40, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 693 UCPDESCR(40H_07H, 0x40, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 694 UCPDESCR(40H_38H, 0x40, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 695 696 UCPDESCR(41H_01H, 0x41, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 697 UCPDESCR(41H_02H, 0x41, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 698 UCPDESCR(41H_04H, 0x41, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 699 UCPDESCR(41H_08H, 0x41, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 700 UCPDESCR(41H_10H, 0x41, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 701 UCPDESCR(41H_20H, 0x41, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 702 UCPDESCR(41H_07H, 0x41, 0x07, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 703 UCPDESCR(41H_38H, 0x41, 0x38, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 704 705 UCPDESCR(42H_01H, 0x42, 0x01, UCP_F_FM | UCP_F_WM), 706 UCPDESCR(42H_02H, 0x42, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 707 UCPDESCR(42H_04H, 0x42, 0x04, UCP_F_FM | UCP_F_WM), 708 UCPDESCR(42H_08H, 0x42, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 709 710 UCPDESCR(43H_01H, 0x43, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 711 UCPDESCR(43H_02H, 0x43, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 712 713 UCPDESCR(60H_01H, 0x60, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 714 UCPDESCR(60H_02H, 0x60, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 715 UCPDESCR(60H_04H, 0x60, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 716 717 UCPDESCR(61H_01H, 0x61, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 718 UCPDESCR(61H_02H, 0x61, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 719 UCPDESCR(61H_04H, 0x61, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 720 721 UCPDESCR(62H_01H, 0x62, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 722 UCPDESCR(62H_02H, 0x62, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 723 UCPDESCR(62H_04H, 0x62, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 724 725 UCPDESCR(63H_01H, 0x63, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 726 UCPDESCR(63H_02H, 0x63, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 727 UCPDESCR(63H_04H, 0x63, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 728 UCPDESCR(63H_08H, 0x63, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 729 UCPDESCR(63H_10H, 0x63, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 730 UCPDESCR(63H_20H, 0x63, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 731 732 UCPDESCR(64H_01H, 0x64, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 733 UCPDESCR(64H_02H, 0x64, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 734 UCPDESCR(64H_04H, 0x64, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 735 UCPDESCR(64H_08H, 0x64, 0x08, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 736 UCPDESCR(64H_10H, 0x64, 0x10, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 737 UCPDESCR(64H_20H, 0x64, 0x20, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 738 739 UCPDESCR(65H_01H, 0x65, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 740 UCPDESCR(65H_02H, 0x65, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 741 UCPDESCR(65H_04H, 0x65, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 742 743 UCPDESCR(66H_01H, 0x66, 0x01, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 744 UCPDESCR(66H_02H, 0x66, 0x02, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 745 UCPDESCR(66H_04H, 0x66, 0x04, UCP_F_FM | UCP_F_I7 | UCP_F_WM), 746 747 UCPDESCR(67H_01H, 0x67, 0x01, UCP_F_FM | UCP_F_WM), 748 749 UCPDESCR(80H_01H, 0x80, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), 750 UCPDESCR(80H_02H, 0x80, 0x02, UCP_F_FM | UCP_F_WM), 751 UCPDESCR(80H_04H, 0x80, 0x04, UCP_F_FM | UCP_F_WM), 752 UCPDESCR(80H_08H, 0x80, 0x08, UCP_F_FM | UCP_F_WM), 753 754 UCPDESCR(81H_01H, 0x81, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), 755 UCPDESCR(81H_02H, 0x81, 0x02, UCP_F_FM | UCP_F_WM), 756 UCPDESCR(81H_04H, 0x81, 0x04, UCP_F_FM | UCP_F_WM), 757 UCPDESCR(81H_08H, 0x81, 0x08, UCP_F_FM | UCP_F_WM), 758 UCPDESCR(81H_20H, 0x81, 0x20, UCP_F_FM | UCP_F_SB), 759 UCPDESCR(81H_80H, 0x81, 0x80, UCP_F_FM | UCP_F_SB), 760 761 UCPDESCR(82H_01H, 0x82, 0x01, UCP_F_FM | UCP_F_WM), 762 763 UCPDESCR(83H_01H, 0x83, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), 764 UCPDESCR(83H_02H, 0x83, 0x02, UCP_F_FM | UCP_F_WM), 765 UCPDESCR(83H_04H, 0x83, 0x04, UCP_F_FM | UCP_F_WM), 766 UCPDESCR(83H_08H, 0x83, 0x08, UCP_F_FM | UCP_F_WM), 767 768 UCPDESCR(84H_01H, 0x84, 0x01, UCP_F_FM | UCP_F_WM | UCP_F_SB), 769 UCPDESCR(84H_02H, 0x84, 0x02, UCP_F_FM | UCP_F_WM), 770 UCPDESCR(84H_04H, 0x84, 0x04, UCP_F_FM | UCP_F_WM), 771 UCPDESCR(84H_08H, 0x84, 0x08, UCP_F_FM | UCP_F_WM), 772 UCPDESCR(85H_02H, 0x85, 0x02, UCP_F_FM | UCP_F_WM), 773 UCPDESCR(86H_01H, 0x86, 0x01, UCP_F_FM | UCP_F_WM) 774 }; 775 776 static const int nucp_events = sizeof(ucp_events) / sizeof(ucp_events[0]); 777 778 static pmc_value_t 779 ucp_perfctr_value_to_reload_count(pmc_value_t v) 780 { 781 v &= (1ULL << uncore_ucp_width) - 1; 782 return (1ULL << uncore_ucp_width) - v; 783 } 784 785 static pmc_value_t 786 ucp_reload_count_to_perfctr_value(pmc_value_t rlc) 787 { 788 return (1ULL << uncore_ucp_width) - rlc; 789 } 790 791 static int 792 ucp_event_sandybridge_ok_on_counter(enum pmc_event pe, int ri) 793 { 794 uint32_t mask; 795 796 switch (pe) { 797 /* 798 * Events valid only on counter 0. 799 */ 800 case PMC_EV_UCP_EVENT_80H_01H: 801 case PMC_EV_UCP_EVENT_83H_01H: 802 mask = (1 << 0); 803 break; 804 805 default: 806 mask = ~0; /* Any row index is ok. */ 807 } 808 809 return (mask & (1 << ri)); 810 } 811 812 static int 813 ucp_allocate_pmc(int cpu, int ri, struct pmc *pm, 814 const struct pmc_op_pmcallocate *a) 815 { 816 int n; 817 enum pmc_event ev; 818 struct ucp_event_descr *ie; 819 uint32_t caps, config, cpuflag, evsel; 820 821 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 822 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 823 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 824 ("[uncore,%d] illegal row-index value %d", __LINE__, ri)); 825 826 /* check requested capabilities */ 827 caps = a->pm_caps; 828 if ((UCP_PMC_CAPS & caps) != caps) 829 return (EPERM); 830 831 ev = pm->pm_event; 832 833 switch (uncore_cputype) { 834 case PMC_CPU_INTEL_SANDYBRIDGE: 835 if (ucp_event_sandybridge_ok_on_counter(ev, ri) == 0) 836 return (EINVAL); 837 break; 838 default: 839 break; 840 } 841 842 843 /* 844 * Look for an event descriptor with matching CPU and event id 845 * fields. 846 */ 847 848 switch (uncore_cputype) { 849 case PMC_CPU_INTEL_COREI7: 850 cpuflag = UCP_F_I7; 851 break; 852 case PMC_CPU_INTEL_SANDYBRIDGE: 853 cpuflag = UCP_F_SB; 854 break; 855 case PMC_CPU_INTEL_WESTMERE: 856 cpuflag = UCP_F_WM; 857 break; 858 default: 859 return (EINVAL); 860 } 861 862 for (n = 0, ie = ucp_events; n < nucp_events; n++, ie++) 863 if (ie->ucp_ev == ev && ie->ucp_flags & cpuflag) 864 break; 865 866 if (n == nucp_events) 867 return (EINVAL); 868 869 /* 870 * A matching event descriptor has been found, so start 871 * assembling the contents of the event select register. 872 */ 873 evsel = ie->ucp_evcode | UCP_EN; 874 875 config = a->pm_md.pm_ucp.pm_ucp_config & ~UCP_F_CMASK; 876 877 /* 878 * If the event uses a fixed umask value, reject any umask 879 * bits set by the user. 880 */ 881 if (ie->ucp_flags & UCP_F_FM) { 882 883 if (UCP_UMASK(config) != 0) 884 return (EINVAL); 885 886 evsel |= (ie->ucp_umask << 8); 887 888 } else 889 return (EINVAL); 890 891 if (caps & PMC_CAP_THRESHOLD) 892 evsel |= (a->pm_md.pm_ucp.pm_ucp_config & UCP_F_CMASK); 893 if (caps & PMC_CAP_EDGE) 894 evsel |= UCP_EDGE; 895 if (caps & PMC_CAP_INVERT) 896 evsel |= UCP_INV; 897 898 pm->pm_md.pm_ucp.pm_ucp_evsel = evsel; 899 900 return (0); 901 } 902 903 static int 904 ucp_config_pmc(int cpu, int ri, struct pmc *pm) 905 { 906 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 907 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 908 909 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 910 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 911 912 PMCDBG(MDP,CFG,1, "ucp-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 913 914 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, 915 cpu)); 916 917 uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc = pm; 918 919 return (0); 920 } 921 922 static int 923 ucp_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 924 { 925 int error; 926 struct pmc_hw *phw; 927 char ucp_name[PMC_NAME_MAX]; 928 929 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri]; 930 931 (void) snprintf(ucp_name, sizeof(ucp_name), "UCP-%d", ri); 932 if ((error = copystr(ucp_name, pi->pm_name, PMC_NAME_MAX, 933 NULL)) != 0) 934 return (error); 935 936 pi->pm_class = PMC_CLASS_UCP; 937 938 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 939 pi->pm_enabled = TRUE; 940 *ppmc = phw->phw_pmc; 941 } else { 942 pi->pm_enabled = FALSE; 943 *ppmc = NULL; 944 } 945 946 return (0); 947 } 948 949 static int 950 ucp_get_config(int cpu, int ri, struct pmc **ppm) 951 { 952 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; 953 954 return (0); 955 } 956 957 static int 958 ucp_read_pmc(int cpu, int ri, pmc_value_t *v) 959 { 960 struct pmc *pm; 961 pmc_value_t tmp; 962 963 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 964 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 965 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 966 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 967 968 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; 969 970 KASSERT(pm, 971 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 972 ri)); 973 974 tmp = rdmsr(UCP_PMC0 + ri); 975 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 976 *v = ucp_perfctr_value_to_reload_count(tmp); 977 else 978 *v = tmp; 979 980 PMCDBG(MDP,REA,1, "ucp-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 981 ri, *v); 982 983 return (0); 984 } 985 986 static int 987 ucp_release_pmc(int cpu, int ri, struct pmc *pm) 988 { 989 (void) pm; 990 991 PMCDBG(MDP,REL,1, "ucp-release cpu=%d ri=%d pm=%p", cpu, ri, 992 pm); 993 994 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 995 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 996 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 997 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 998 999 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc 1000 == NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__)); 1001 1002 return (0); 1003 } 1004 1005 static int 1006 ucp_start_pmc(int cpu, int ri) 1007 { 1008 struct pmc *pm; 1009 uint32_t evsel; 1010 struct uncore_cpu *cc; 1011 1012 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1013 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 1014 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 1015 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 1016 1017 cc = uncore_pcpu[cpu]; 1018 pm = cc->pc_uncorepmcs[ri].phw_pmc; 1019 1020 KASSERT(pm, 1021 ("[uncore,%d] starting cpu%d,ri%d with no pmc configured", 1022 __LINE__, cpu, ri)); 1023 1024 PMCDBG(MDP,STA,1, "ucp-start cpu=%d ri=%d", cpu, ri); 1025 1026 evsel = pm->pm_md.pm_ucp.pm_ucp_evsel; 1027 1028 PMCDBG(MDP,STA,2, 1029 "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 1030 cpu, ri, SELECTSEL(uncore_cputype) + ri, evsel); 1031 1032 /* Event specific configuration. */ 1033 switch (pm->pm_event) { 1034 case PMC_EV_UCP_EVENT_0CH_04H_E: 1035 case PMC_EV_UCP_EVENT_0CH_08H_E: 1036 wrmsr(MSR_GQ_SNOOP_MESF,0x2); 1037 break; 1038 case PMC_EV_UCP_EVENT_0CH_04H_F: 1039 case PMC_EV_UCP_EVENT_0CH_08H_F: 1040 wrmsr(MSR_GQ_SNOOP_MESF,0x8); 1041 break; 1042 case PMC_EV_UCP_EVENT_0CH_04H_M: 1043 case PMC_EV_UCP_EVENT_0CH_08H_M: 1044 wrmsr(MSR_GQ_SNOOP_MESF,0x1); 1045 break; 1046 case PMC_EV_UCP_EVENT_0CH_04H_S: 1047 case PMC_EV_UCP_EVENT_0CH_08H_S: 1048 wrmsr(MSR_GQ_SNOOP_MESF,0x4); 1049 break; 1050 default: 1051 break; 1052 } 1053 1054 wrmsr(SELECTSEL(uncore_cputype) + ri, evsel); 1055 1056 do { 1057 cc->pc_resync = 0; 1058 cc->pc_globalctrl |= (1ULL << ri); 1059 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl); 1060 } while (cc->pc_resync != 0); 1061 1062 return (0); 1063 } 1064 1065 static int 1066 ucp_stop_pmc(int cpu, int ri) 1067 { 1068 struct pmc *pm; 1069 struct uncore_cpu *cc; 1070 1071 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1072 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 1073 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 1074 ("[uncore,%d] illegal row index %d", __LINE__, ri)); 1075 1076 cc = uncore_pcpu[cpu]; 1077 pm = cc->pc_uncorepmcs[ri].phw_pmc; 1078 1079 KASSERT(pm, 1080 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1081 cpu, ri)); 1082 1083 PMCDBG(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri); 1084 1085 /* stop hw. */ 1086 wrmsr(SELECTSEL(uncore_cputype) + ri, 0); 1087 1088 do { 1089 cc->pc_resync = 0; 1090 cc->pc_globalctrl &= ~(1ULL << ri); 1091 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl); 1092 } while (cc->pc_resync != 0); 1093 1094 return (0); 1095 } 1096 1097 static int 1098 ucp_write_pmc(int cpu, int ri, pmc_value_t v) 1099 { 1100 struct pmc *pm; 1101 struct uncore_cpu *cc; 1102 1103 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1104 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 1105 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 1106 ("[uncore,%d] illegal row index %d", __LINE__, ri)); 1107 1108 cc = uncore_pcpu[cpu]; 1109 pm = cc->pc_uncorepmcs[ri].phw_pmc; 1110 1111 KASSERT(pm, 1112 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1113 cpu, ri)); 1114 1115 PMCDBG(MDP,WRI,1, "ucp-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1116 UCP_PMC0 + ri, v); 1117 1118 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1119 v = ucp_reload_count_to_perfctr_value(v); 1120 1121 /* 1122 * Write the new value to the counter. The counter will be in 1123 * a stopped state when the pcd_write() entry point is called. 1124 */ 1125 1126 wrmsr(UCP_PMC0 + ri, v); 1127 1128 return (0); 1129 } 1130 1131 1132 static void 1133 ucp_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 1134 { 1135 struct pmc_classdep *pcd; 1136 1137 KASSERT(md != NULL, ("[ucp,%d] md is NULL", __LINE__)); 1138 1139 PMCDBG(MDP,INI,1, "%s", "ucp-initialize"); 1140 1141 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP]; 1142 1143 pcd->pcd_caps = UCP_PMC_CAPS; 1144 pcd->pcd_class = PMC_CLASS_UCP; 1145 pcd->pcd_num = npmc; 1146 pcd->pcd_ri = md->pmd_npmc; 1147 pcd->pcd_width = pmcwidth; 1148 1149 pcd->pcd_allocate_pmc = ucp_allocate_pmc; 1150 pcd->pcd_config_pmc = ucp_config_pmc; 1151 pcd->pcd_describe = ucp_describe; 1152 pcd->pcd_get_config = ucp_get_config; 1153 pcd->pcd_get_msr = NULL; 1154 pcd->pcd_pcpu_fini = uncore_pcpu_fini; 1155 pcd->pcd_pcpu_init = uncore_pcpu_init; 1156 pcd->pcd_read_pmc = ucp_read_pmc; 1157 pcd->pcd_release_pmc = ucp_release_pmc; 1158 pcd->pcd_start_pmc = ucp_start_pmc; 1159 pcd->pcd_stop_pmc = ucp_stop_pmc; 1160 pcd->pcd_write_pmc = ucp_write_pmc; 1161 1162 md->pmd_npmc += npmc; 1163 } 1164 1165 int 1166 pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu) 1167 { 1168 uncore_cputype = md->pmd_cputype; 1169 uncore_pmcmask = 0; 1170 1171 /* 1172 * Initialize programmable counters. 1173 */ 1174 1175 uncore_ucp_npmc = 8; 1176 uncore_ucp_width = 48; 1177 1178 uncore_pmcmask |= ((1ULL << uncore_ucp_npmc) - 1); 1179 1180 ucp_initialize(md, maxcpu, uncore_ucp_npmc, uncore_ucp_width); 1181 1182 /* 1183 * Initialize fixed function counters, if present. 1184 */ 1185 uncore_ucf_ri = uncore_ucp_npmc; 1186 uncore_ucf_npmc = 1; 1187 uncore_ucf_width = 48; 1188 1189 ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width); 1190 uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << SELECTOFF(uncore_cputype); 1191 1192 PMCDBG(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask, 1193 uncore_ucf_ri); 1194 1195 uncore_pcpu = malloc(sizeof(struct uncore_cpu **) * maxcpu, M_PMC, 1196 M_ZERO | M_WAITOK); 1197 1198 return (0); 1199 } 1200 1201 void 1202 pmc_uncore_finalize(struct pmc_mdep *md) 1203 { 1204 PMCDBG(MDP,INI,1, "%s", "uncore-finalize"); 1205 1206 free(uncore_pcpu, M_PMC); 1207 uncore_pcpu = NULL; 1208 } 1209