1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010 Fabien Thomas 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel Uncore PMCs. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/pmc.h> 39 #include <sys/pmckern.h> 40 #include <sys/systm.h> 41 42 #include <machine/intr_machdep.h> 43 #include <x86/apicvar.h> 44 #include <machine/cpu.h> 45 #include <machine/cpufunc.h> 46 #include <machine/specialreg.h> 47 48 #define UCF_PMC_CAPS \ 49 (PMC_CAP_READ | PMC_CAP_WRITE) 50 51 #define UCP_PMC_CAPS \ 52 (PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 53 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 54 55 #define SELECTSEL(x) \ 56 (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \ 57 UCP_CB0_EVSEL0 : UCP_EVSEL0) 58 59 #define SELECTOFF(x) \ 60 (((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \ 61 UCF_OFFSET_SB : UCF_OFFSET) 62 63 static enum pmc_cputype uncore_cputype; 64 65 struct uncore_cpu { 66 volatile uint32_t pc_ucfctrl; /* Fixed function control. */ 67 volatile uint64_t pc_globalctrl; /* Global control register. */ 68 struct pmc_hw pc_uncorepmcs[]; 69 }; 70 71 static struct uncore_cpu **uncore_pcpu; 72 73 static uint64_t uncore_pmcmask; 74 75 static int uncore_ucf_ri; /* relative index of fixed counters */ 76 static int uncore_ucf_width; 77 static int uncore_ucf_npmc; 78 79 static int uncore_ucp_width; 80 static int uncore_ucp_npmc; 81 82 static int 83 uncore_pcpu_noop(struct pmc_mdep *md, int cpu) 84 { 85 (void) md; 86 (void) cpu; 87 return (0); 88 } 89 90 static int 91 uncore_pcpu_init(struct pmc_mdep *md, int cpu) 92 { 93 struct pmc_cpu *pc; 94 struct uncore_cpu *cc; 95 struct pmc_hw *phw; 96 int uncore_ri, n, npmc; 97 98 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 99 ("[ucf,%d] insane cpu number %d", __LINE__, cpu)); 100 101 PMCDBG1(MDP,INI,1,"uncore-init cpu=%d", cpu); 102 103 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; 104 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; 105 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; 106 107 cc = malloc(sizeof(struct uncore_cpu) + npmc * sizeof(struct pmc_hw), 108 M_PMC, M_WAITOK | M_ZERO); 109 110 uncore_pcpu[cpu] = cc; 111 pc = pmc_pcpu[cpu]; 112 113 KASSERT(pc != NULL && cc != NULL, 114 ("[uncore,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 115 116 for (n = 0, phw = cc->pc_uncorepmcs; n < npmc; n++, phw++) { 117 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 118 PMC_PHW_CPU_TO_STATE(cpu) | 119 PMC_PHW_INDEX_TO_STATE(n + uncore_ri); 120 phw->phw_pmc = NULL; 121 pc->pc_hwpmcs[n + uncore_ri] = phw; 122 } 123 124 return (0); 125 } 126 127 static int 128 uncore_pcpu_fini(struct pmc_mdep *md, int cpu) 129 { 130 int uncore_ri, n, npmc; 131 struct pmc_cpu *pc; 132 struct uncore_cpu *cc; 133 134 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 135 ("[uncore,%d] insane cpu number (%d)", __LINE__, cpu)); 136 137 PMCDBG1(MDP,INI,1,"uncore-pcpu-fini cpu=%d", cpu); 138 139 if ((cc = uncore_pcpu[cpu]) == NULL) 140 return (0); 141 142 uncore_pcpu[cpu] = NULL; 143 144 pc = pmc_pcpu[cpu]; 145 146 KASSERT(pc != NULL, ("[uncore,%d] NULL per-cpu %d state", __LINE__, 147 cpu)); 148 149 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num; 150 uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri; 151 152 for (n = 0; n < npmc; n++) 153 wrmsr(SELECTSEL(uncore_cputype) + n, 0); 154 155 wrmsr(UCF_CTRL, 0); 156 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num; 157 158 for (n = 0; n < npmc; n++) 159 pc->pc_hwpmcs[n + uncore_ri] = NULL; 160 161 free(cc, M_PMC); 162 163 return (0); 164 } 165 166 /* 167 * Fixed function counters. 168 */ 169 170 static pmc_value_t 171 ucf_perfctr_value_to_reload_count(pmc_value_t v) 172 { 173 174 /* If the PMC has overflowed, return a reload count of zero. */ 175 if ((v & (1ULL << (uncore_ucf_width - 1))) == 0) 176 return (0); 177 v &= (1ULL << uncore_ucf_width) - 1; 178 return (1ULL << uncore_ucf_width) - v; 179 } 180 181 static pmc_value_t 182 ucf_reload_count_to_perfctr_value(pmc_value_t rlc) 183 { 184 return (1ULL << uncore_ucf_width) - rlc; 185 } 186 187 static int 188 ucf_allocate_pmc(int cpu, int ri, struct pmc *pm, 189 const struct pmc_op_pmcallocate *a) 190 { 191 uint32_t flags; 192 193 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 194 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 195 196 PMCDBG2(MDP,ALL,1, "ucf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 197 198 if (ri < 0 || ri > uncore_ucf_npmc) 199 return (EINVAL); 200 201 if (a->pm_class != PMC_CLASS_UCF) 202 return (EINVAL); 203 204 flags = UCF_EN; 205 206 pm->pm_md.pm_ucf.pm_ucf_ctrl = (flags << (ri * 4)); 207 208 PMCDBG1(MDP,ALL,2, "ucf-allocate config=0x%jx", 209 (uintmax_t) pm->pm_md.pm_ucf.pm_ucf_ctrl); 210 211 return (0); 212 } 213 214 static int 215 ucf_config_pmc(int cpu, int ri, struct pmc *pm) 216 { 217 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 218 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 219 220 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 221 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 222 223 PMCDBG3(MDP,CFG,1, "ucf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 224 225 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, 226 cpu)); 227 228 uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc = pm; 229 230 return (0); 231 } 232 233 static int 234 ucf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 235 { 236 struct pmc_hw *phw; 237 238 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri]; 239 240 snprintf(pi->pm_name, sizeof(pi->pm_name), "UCF-%d", ri); 241 pi->pm_class = PMC_CLASS_UCF; 242 243 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 244 pi->pm_enabled = TRUE; 245 *ppmc = phw->phw_pmc; 246 } else { 247 pi->pm_enabled = FALSE; 248 *ppmc = NULL; 249 } 250 251 return (0); 252 } 253 254 static int 255 ucf_get_config(int cpu, int ri, struct pmc **ppm) 256 { 257 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 258 259 return (0); 260 } 261 262 static int 263 ucf_read_pmc(int cpu, int ri, pmc_value_t *v) 264 { 265 struct pmc *pm; 266 pmc_value_t tmp; 267 268 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 269 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 270 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 271 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 272 273 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 274 275 KASSERT(pm, 276 ("[uncore,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 277 ri, ri + uncore_ucf_ri)); 278 279 tmp = rdmsr(UCF_CTR0 + ri); 280 281 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 282 *v = ucf_perfctr_value_to_reload_count(tmp); 283 else 284 *v = tmp; 285 286 PMCDBG3(MDP,REA,1, "ucf-read cpu=%d ri=%d -> v=%jx", cpu, ri, *v); 287 288 return (0); 289 } 290 291 static int 292 ucf_release_pmc(int cpu, int ri, struct pmc *pmc) 293 { 294 PMCDBG3(MDP,REL,1, "ucf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 295 296 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 297 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 298 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 299 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 300 301 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc == NULL, 302 ("[uncore,%d] PHW pmc non-NULL", __LINE__)); 303 304 return (0); 305 } 306 307 static int 308 ucf_start_pmc(int cpu, int ri) 309 { 310 struct pmc *pm; 311 struct uncore_cpu *ucfc; 312 313 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 314 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 315 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 316 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 317 318 PMCDBG2(MDP,STA,1,"ucf-start cpu=%d ri=%d", cpu, ri); 319 320 ucfc = uncore_pcpu[cpu]; 321 pm = ucfc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 322 323 ucfc->pc_ucfctrl |= pm->pm_md.pm_ucf.pm_ucf_ctrl; 324 325 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); 326 327 ucfc->pc_globalctrl |= (1ULL << (ri + SELECTOFF(uncore_cputype))); 328 wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl); 329 330 PMCDBG4(MDP,STA,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", 331 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), 332 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); 333 334 return (0); 335 } 336 337 static int 338 ucf_stop_pmc(int cpu, int ri) 339 { 340 uint32_t fc; 341 struct uncore_cpu *ucfc; 342 343 PMCDBG2(MDP,STO,1,"ucf-stop cpu=%d ri=%d", cpu, ri); 344 345 ucfc = uncore_pcpu[cpu]; 346 347 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 348 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 349 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 350 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 351 352 fc = (UCF_MASK << (ri * 4)); 353 354 ucfc->pc_ucfctrl &= ~fc; 355 356 PMCDBG1(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl); 357 wrmsr(UCF_CTRL, ucfc->pc_ucfctrl); 358 359 /* Don't need to write UC_GLOBAL_CTRL, one disable is enough. */ 360 361 PMCDBG4(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)", 362 ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL), 363 ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL)); 364 365 return (0); 366 } 367 368 static int 369 ucf_write_pmc(int cpu, int ri, pmc_value_t v) 370 { 371 struct uncore_cpu *cc; 372 struct pmc *pm; 373 374 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 375 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 376 KASSERT(ri >= 0 && ri < uncore_ucf_npmc, 377 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 378 379 cc = uncore_pcpu[cpu]; 380 pm = cc->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc; 381 382 KASSERT(pm, 383 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 384 385 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 386 v = ucf_reload_count_to_perfctr_value(v); 387 388 wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */ 389 wrmsr(UCF_CTR0 + ri, v); 390 wrmsr(UCF_CTRL, cc->pc_ucfctrl); 391 392 PMCDBG4(MDP,WRI,1, "ucf-write cpu=%d ri=%d v=%jx ucfctrl=%jx ", 393 cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL)); 394 395 return (0); 396 } 397 398 399 static void 400 ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 401 { 402 struct pmc_classdep *pcd; 403 404 KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__)); 405 406 PMCDBG0(MDP,INI,1, "ucf-initialize"); 407 408 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF]; 409 410 pcd->pcd_caps = UCF_PMC_CAPS; 411 pcd->pcd_class = PMC_CLASS_UCF; 412 pcd->pcd_num = npmc; 413 pcd->pcd_ri = md->pmd_npmc; 414 pcd->pcd_width = pmcwidth; 415 416 pcd->pcd_allocate_pmc = ucf_allocate_pmc; 417 pcd->pcd_config_pmc = ucf_config_pmc; 418 pcd->pcd_describe = ucf_describe; 419 pcd->pcd_get_config = ucf_get_config; 420 pcd->pcd_get_msr = NULL; 421 pcd->pcd_pcpu_fini = uncore_pcpu_noop; 422 pcd->pcd_pcpu_init = uncore_pcpu_noop; 423 pcd->pcd_read_pmc = ucf_read_pmc; 424 pcd->pcd_release_pmc = ucf_release_pmc; 425 pcd->pcd_start_pmc = ucf_start_pmc; 426 pcd->pcd_stop_pmc = ucf_stop_pmc; 427 pcd->pcd_write_pmc = ucf_write_pmc; 428 429 md->pmd_npmc += npmc; 430 } 431 432 /* 433 * Intel programmable PMCs. 434 */ 435 436 /* 437 * Event descriptor tables. 438 * 439 * For each event id, we track: 440 * 441 * 1. The CPUs that the event is valid for. 442 * 443 * 2. If the event uses a fixed UMASK, the value of the umask field. 444 * If the event doesn't use a fixed UMASK, a mask of legal bits 445 * to check against. 446 */ 447 448 struct ucp_event_descr { 449 enum pmc_event ucp_ev; 450 unsigned char ucp_evcode; 451 unsigned char ucp_umask; 452 unsigned char ucp_flags; 453 }; 454 455 #define UCP_F_I7 (1 << 0) /* CPU: Core i7 */ 456 #define UCP_F_WM (1 << 1) /* CPU: Westmere */ 457 #define UCP_F_SB (1 << 2) /* CPU: Sandy Bridge */ 458 #define UCP_F_HW (1 << 3) /* CPU: Haswell */ 459 #define UCP_F_FM (1 << 4) /* Fixed mask */ 460 461 #define UCP_F_ALLCPUS \ 462 (UCP_F_I7 | UCP_F_WM) 463 464 #define UCP_F_CMASK 0xFF000000 465 466 static pmc_value_t 467 ucp_perfctr_value_to_reload_count(pmc_value_t v) 468 { 469 v &= (1ULL << uncore_ucp_width) - 1; 470 return (1ULL << uncore_ucp_width) - v; 471 } 472 473 static pmc_value_t 474 ucp_reload_count_to_perfctr_value(pmc_value_t rlc) 475 { 476 return (1ULL << uncore_ucp_width) - rlc; 477 } 478 479 /* 480 * Counter specific event information for Sandybridge and Haswell 481 */ 482 static int 483 ucp_event_sb_hw_ok_on_counter(uint8_t ev, int ri) 484 { 485 uint32_t mask; 486 487 switch (ev) { 488 /* 489 * Events valid only on counter 0. 490 */ 491 case 0x80: 492 case 0x83: 493 mask = (1 << 0); 494 break; 495 496 default: 497 mask = ~0; /* Any row index is ok. */ 498 } 499 500 return (mask & (1 << ri)); 501 } 502 503 static int 504 ucp_allocate_pmc(int cpu, int ri, struct pmc *pm, 505 const struct pmc_op_pmcallocate *a) 506 { 507 uint8_t ev; 508 const struct pmc_md_ucp_op_pmcallocate *ucp; 509 510 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 511 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 512 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 513 ("[uncore,%d] illegal row-index value %d", __LINE__, ri)); 514 515 if (a->pm_class != PMC_CLASS_UCP) 516 return (EINVAL); 517 518 ucp = &a->pm_md.pm_ucp; 519 ev = UCP_EVSEL(ucp->pm_ucp_config); 520 switch (uncore_cputype) { 521 case PMC_CPU_INTEL_HASWELL: 522 case PMC_CPU_INTEL_SANDYBRIDGE: 523 if (ucp_event_sb_hw_ok_on_counter(ev, ri) == 0) 524 return (EINVAL); 525 break; 526 default: 527 break; 528 } 529 530 pm->pm_md.pm_ucp.pm_ucp_evsel = ucp->pm_ucp_config | UCP_EN; 531 532 return (0); 533 } 534 535 static int 536 ucp_config_pmc(int cpu, int ri, struct pmc *pm) 537 { 538 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 539 ("[uncore,%d] illegal CPU %d", __LINE__, cpu)); 540 541 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 542 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 543 544 PMCDBG3(MDP,CFG,1, "ucp-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 545 546 KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__, 547 cpu)); 548 549 uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc = pm; 550 551 return (0); 552 } 553 554 static int 555 ucp_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 556 { 557 struct pmc_hw *phw; 558 559 phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri]; 560 561 snprintf(pi->pm_name, sizeof(pi->pm_name), "UCP-%d", ri); 562 pi->pm_class = PMC_CLASS_UCP; 563 564 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 565 pi->pm_enabled = TRUE; 566 *ppmc = phw->phw_pmc; 567 } else { 568 pi->pm_enabled = FALSE; 569 *ppmc = NULL; 570 } 571 572 return (0); 573 } 574 575 static int 576 ucp_get_config(int cpu, int ri, struct pmc **ppm) 577 { 578 *ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; 579 580 return (0); 581 } 582 583 static int 584 ucp_read_pmc(int cpu, int ri, pmc_value_t *v) 585 { 586 struct pmc *pm; 587 pmc_value_t tmp; 588 589 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 590 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 591 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 592 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 593 594 pm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc; 595 596 KASSERT(pm, 597 ("[uncore,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 598 ri)); 599 600 tmp = rdmsr(UCP_PMC0 + ri); 601 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 602 *v = ucp_perfctr_value_to_reload_count(tmp); 603 else 604 *v = tmp; 605 606 PMCDBG4(MDP,REA,1, "ucp-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 607 ri, *v); 608 609 return (0); 610 } 611 612 static int 613 ucp_release_pmc(int cpu, int ri, struct pmc *pm) 614 { 615 (void) pm; 616 617 PMCDBG3(MDP,REL,1, "ucp-release cpu=%d ri=%d pm=%p", cpu, ri, 618 pm); 619 620 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 621 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 622 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 623 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 624 625 KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc 626 == NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__)); 627 628 return (0); 629 } 630 631 static int 632 ucp_start_pmc(int cpu, int ri) 633 { 634 struct pmc *pm; 635 uint64_t evsel; 636 struct uncore_cpu *cc; 637 638 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 639 ("[uncore,%d] illegal CPU value %d", __LINE__, cpu)); 640 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 641 ("[uncore,%d] illegal row-index %d", __LINE__, ri)); 642 643 cc = uncore_pcpu[cpu]; 644 pm = cc->pc_uncorepmcs[ri].phw_pmc; 645 646 KASSERT(pm, 647 ("[uncore,%d] starting cpu%d,ri%d with no pmc configured", 648 __LINE__, cpu, ri)); 649 650 PMCDBG2(MDP,STA,1, "ucp-start cpu=%d ri=%d", cpu, ri); 651 652 evsel = pm->pm_md.pm_ucp.pm_ucp_evsel; 653 654 PMCDBG4(MDP,STA,2, 655 "ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 656 cpu, ri, SELECTSEL(uncore_cputype) + ri, evsel); 657 658 wrmsr(SELECTSEL(uncore_cputype) + ri, evsel); 659 660 cc->pc_globalctrl |= (1ULL << ri); 661 wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl); 662 663 return (0); 664 } 665 666 static int 667 ucp_stop_pmc(int cpu, int ri) 668 { 669 struct pmc *pm __diagused; 670 struct uncore_cpu *cc; 671 672 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 673 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 674 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 675 ("[uncore,%d] illegal row index %d", __LINE__, ri)); 676 677 cc = uncore_pcpu[cpu]; 678 pm = cc->pc_uncorepmcs[ri].phw_pmc; 679 680 KASSERT(pm, 681 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 682 cpu, ri)); 683 684 PMCDBG2(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri); 685 686 /* stop hw. */ 687 wrmsr(SELECTSEL(uncore_cputype) + ri, 0); 688 689 /* Don't need to write UC_GLOBAL_CTRL, one disable is enough. */ 690 691 return (0); 692 } 693 694 static int 695 ucp_write_pmc(int cpu, int ri, pmc_value_t v) 696 { 697 struct pmc *pm; 698 struct uncore_cpu *cc; 699 700 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 701 ("[uncore,%d] illegal cpu value %d", __LINE__, cpu)); 702 KASSERT(ri >= 0 && ri < uncore_ucp_npmc, 703 ("[uncore,%d] illegal row index %d", __LINE__, ri)); 704 705 cc = uncore_pcpu[cpu]; 706 pm = cc->pc_uncorepmcs[ri].phw_pmc; 707 708 KASSERT(pm, 709 ("[uncore,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 710 cpu, ri)); 711 712 PMCDBG4(MDP,WRI,1, "ucp-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 713 UCP_PMC0 + ri, v); 714 715 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 716 v = ucp_reload_count_to_perfctr_value(v); 717 718 /* 719 * Write the new value to the counter. The counter will be in 720 * a stopped state when the pcd_write() entry point is called. 721 */ 722 723 wrmsr(UCP_PMC0 + ri, v); 724 725 return (0); 726 } 727 728 729 static void 730 ucp_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 731 { 732 struct pmc_classdep *pcd; 733 734 KASSERT(md != NULL, ("[ucp,%d] md is NULL", __LINE__)); 735 736 PMCDBG0(MDP,INI,1, "ucp-initialize"); 737 738 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP]; 739 740 pcd->pcd_caps = UCP_PMC_CAPS; 741 pcd->pcd_class = PMC_CLASS_UCP; 742 pcd->pcd_num = npmc; 743 pcd->pcd_ri = md->pmd_npmc; 744 pcd->pcd_width = pmcwidth; 745 746 pcd->pcd_allocate_pmc = ucp_allocate_pmc; 747 pcd->pcd_config_pmc = ucp_config_pmc; 748 pcd->pcd_describe = ucp_describe; 749 pcd->pcd_get_config = ucp_get_config; 750 pcd->pcd_get_msr = NULL; 751 pcd->pcd_pcpu_fini = uncore_pcpu_fini; 752 pcd->pcd_pcpu_init = uncore_pcpu_init; 753 pcd->pcd_read_pmc = ucp_read_pmc; 754 pcd->pcd_release_pmc = ucp_release_pmc; 755 pcd->pcd_start_pmc = ucp_start_pmc; 756 pcd->pcd_stop_pmc = ucp_stop_pmc; 757 pcd->pcd_write_pmc = ucp_write_pmc; 758 759 md->pmd_npmc += npmc; 760 } 761 762 int 763 pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu) 764 { 765 uncore_cputype = md->pmd_cputype; 766 uncore_pmcmask = 0; 767 768 /* 769 * Initialize programmable counters. 770 */ 771 772 uncore_ucp_npmc = 8; 773 uncore_ucp_width = 48; 774 775 uncore_pmcmask |= ((1ULL << uncore_ucp_npmc) - 1); 776 777 ucp_initialize(md, maxcpu, uncore_ucp_npmc, uncore_ucp_width); 778 779 /* 780 * Initialize fixed function counters, if present. 781 */ 782 uncore_ucf_ri = uncore_ucp_npmc; 783 uncore_ucf_npmc = 1; 784 uncore_ucf_width = 48; 785 786 ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width); 787 uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << SELECTOFF(uncore_cputype); 788 789 PMCDBG2(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask, 790 uncore_ucf_ri); 791 792 uncore_pcpu = malloc(sizeof(*uncore_pcpu) * maxcpu, M_PMC, 793 M_ZERO | M_WAITOK); 794 795 return (0); 796 } 797 798 void 799 pmc_uncore_finalize(struct pmc_mdep *md) 800 { 801 PMCDBG0(MDP,INI,1, "uncore-finalize"); 802 803 free(uncore_pcpu, M_PMC); 804 uncore_pcpu = NULL; 805 } 806