1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Justin Hibbits 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/pmc.h> 35 #include <sys/pmckern.h> 36 #include <sys/systm.h> 37 38 #include <machine/pmc_mdep.h> 39 #include <machine/spr.h> 40 #include <machine/cpu.h> 41 42 #include "hwpmc_powerpc.h" 43 44 #define PPC970_MAX_PMCS 8 45 #define PMC_PPC970_FLAG_PMCS 0x000000ff 46 47 /* MMCR0, PMC1 is 8 bytes in, PMC2 is 1 byte in. */ 48 #define PPC970_SET_MMCR0_PMCSEL(r, x, i) \ 49 ((r & ~(0x1f << (7 * (1 - i) + 1))) | (x << (7 * (1 - i) + 1))) 50 /* MMCR1 has 6 PMC*SEL items (PMC3->PMC8), in sequence. */ 51 #define PPC970_SET_MMCR1_PMCSEL(r, x, i) \ 52 ((r & ~(0x1f << (5 * (7 - i) + 2))) | (x << (5 * (7 - i) + 2))) 53 54 /* How PMC works on PPC970: 55 * 56 * Any PMC can count a direct event. Indirect events are handled specially. 57 * Direct events: As published. 58 * 59 * Encoding 00 000 -- Add byte lane bit counters 60 * MMCR1[24:31] -- select bit matching PMC being an adder. 61 * Bus events: 62 * PMCxSEL: 1x -- select from byte lane: 10 == lower lane (0/1), 11 == upper 63 * lane (2/3). 64 * PMCxSEL[2:4] -- bit in the byte lane selected. 65 * 66 * PMC[1,2,5,6] == lane 0/lane 2 67 * PMC[3,4,7,8] == lane 1,3 68 * 69 * 70 * Lanes: 71 * Lane 0 -- TTM0(FPU,ISU,IFU,VPU) 72 * TTM1(IDU,ISU,STS) 73 * LSU0 byte 0 74 * LSU1 byte 0 75 * Lane 1 -- TTM0 76 * TTM1 77 * LSU0 byte 1 78 * LSU1 byte 1 79 * Lane 2 -- TTM0 80 * TTM1 81 * LSU0 byte 2 82 * LSU1 byte 2 or byte 6 83 * Lane 3 -- TTM0 84 * TTM1 85 * LSU0 byte 3 86 * LSU1 byte 3 or byte 7 87 * 88 * Adders: 89 * Add byte lane for PMC (above), bit 0+4, 1+5, 2+6, 3+7 90 */ 91 92 static struct pmc_ppc_event ppc970_event_codes[] = { 93 {PMC_EV_PPC970_INSTR_COMPLETED, 94 .pe_flags = PMC_PPC970_FLAG_PMCS, 95 .pe_code = 0x09 96 }, 97 {PMC_EV_PPC970_MARKED_GROUP_DISPATCH, 98 .pe_flags = PMC_FLAG_PMC1, 99 .pe_code = 0x2 100 }, 101 {PMC_EV_PPC970_MARKED_STORE_COMPLETED, 102 .pe_flags = PMC_FLAG_PMC1, 103 .pe_code = 0x03 104 }, 105 {PMC_EV_PPC970_GCT_EMPTY, 106 .pe_flags = PMC_FLAG_PMC1, 107 .pe_code = 0x04 108 }, 109 {PMC_EV_PPC970_RUN_CYCLES, 110 .pe_flags = PMC_FLAG_PMC1, 111 .pe_code = 0x05 112 }, 113 {PMC_EV_PPC970_OVERFLOW, 114 .pe_flags = PMC_PPC970_FLAG_PMCS, 115 .pe_code = 0x0a 116 }, 117 {PMC_EV_PPC970_CYCLES, 118 .pe_flags = PMC_PPC970_FLAG_PMCS, 119 .pe_code = 0x0f 120 }, 121 {PMC_EV_PPC970_THRESHOLD_TIMEOUT, 122 .pe_flags = PMC_FLAG_PMC2, 123 .pe_code = 0x3 124 }, 125 {PMC_EV_PPC970_GROUP_DISPATCH, 126 .pe_flags = PMC_FLAG_PMC2, 127 .pe_code = 0x4 128 }, 129 {PMC_EV_PPC970_BR_MARKED_INSTR_FINISH, 130 .pe_flags = PMC_FLAG_PMC2, 131 .pe_code = 0x5 132 }, 133 {PMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULL, 134 .pe_flags = PMC_FLAG_PMC2, 135 .pe_code = 0xb 136 }, 137 {PMC_EV_PPC970_STOP_COMPLETION, 138 .pe_flags = PMC_FLAG_PMC3, 139 .pe_code = 0x1 140 }, 141 {PMC_EV_PPC970_LSU_EMPTY, 142 .pe_flags = PMC_FLAG_PMC3, 143 .pe_code = 0x2 144 }, 145 {PMC_EV_PPC970_MARKED_STORE_WITH_INTR, 146 .pe_flags = PMC_FLAG_PMC3, 147 .pe_code = 0x3 148 }, 149 {PMC_EV_PPC970_CYCLES_IN_SUPER, 150 .pe_flags = PMC_FLAG_PMC3, 151 .pe_code = 0x4 152 }, 153 {PMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETED, 154 .pe_flags = PMC_FLAG_PMC3, 155 .pe_code = 0x5 156 }, 157 {PMC_EV_PPC970_FXU0_IDLE_FXU1_BUSY, 158 .pe_flags = PMC_FLAG_PMC4, 159 .pe_code = 0x2 160 }, 161 {PMC_EV_PPC970_SRQ_EMPTY, 162 .pe_flags = PMC_FLAG_PMC4, 163 .pe_code = 0x3 164 }, 165 {PMC_EV_PPC970_MARKED_GROUP_COMPLETED, 166 .pe_flags = PMC_FLAG_PMC4, 167 .pe_code = 0x4 168 }, 169 {PMC_EV_PPC970_CR_MARKED_INSTR_FINISH, 170 .pe_flags = PMC_FLAG_PMC4, 171 .pe_code = 0x5 172 }, 173 {PMC_EV_PPC970_DISPATCH_SUCCESS, 174 .pe_flags = PMC_FLAG_PMC5, 175 .pe_code = 0x1 176 }, 177 {PMC_EV_PPC970_FXU0_IDLE_FXU1_IDLE, 178 .pe_flags = PMC_FLAG_PMC5, 179 .pe_code = 0x2 180 }, 181 {PMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETED, 182 .pe_flags = PMC_FLAG_PMC5, 183 .pe_code = 0x3 184 }, 185 {PMC_EV_PPC970_GROUP_MARKED_IDU, 186 .pe_flags = PMC_FLAG_PMC5, 187 .pe_code = 0x4 188 }, 189 {PMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUT, 190 .pe_flags = PMC_FLAG_PMC5, 191 .pe_code = 0x5 192 }, 193 {PMC_EV_PPC970_FXU0_BUSY_FXU1_BUSY, 194 .pe_flags = PMC_FLAG_PMC6, 195 .pe_code = 0x2 196 }, 197 {PMC_EV_PPC970_MARKED_STORE_SENT_TO_STS, 198 .pe_flags = PMC_FLAG_PMC6, 199 .pe_code = 0x3 200 }, 201 {PMC_EV_PPC970_FXU_MARKED_INSTR_FINISHED, 202 .pe_flags = PMC_FLAG_PMC6, 203 .pe_code = 0x4 204 }, 205 {PMC_EV_PPC970_MARKED_GROUP_ISSUED, 206 .pe_flags = PMC_FLAG_PMC6, 207 .pe_code = 0x5 208 }, 209 {PMC_EV_PPC970_FXU0_BUSY_FXU1_IDLE, 210 .pe_flags = PMC_FLAG_PMC7, 211 .pe_code = 0x2 212 }, 213 {PMC_EV_PPC970_GROUP_COMPLETED, 214 .pe_flags = PMC_FLAG_PMC7, 215 .pe_code = 0x3 216 }, 217 {PMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETED, 218 .pe_flags = PMC_FLAG_PMC7, 219 .pe_code = 0x4 220 }, 221 {PMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNIT, 222 .pe_flags = PMC_FLAG_PMC7, 223 .pe_code = 0x5 224 }, 225 {PMC_EV_PPC970_EXTERNAL_INTERRUPT, 226 .pe_flags = PMC_FLAG_PMC8, 227 .pe_code = 0x2 228 }, 229 {PMC_EV_PPC970_GROUP_DISPATCH_REJECT, 230 .pe_flags = PMC_FLAG_PMC8, 231 .pe_code = 0x3 232 }, 233 {PMC_EV_PPC970_LSU_MARKED_INSTR_FINISH, 234 .pe_flags = PMC_FLAG_PMC8, 235 .pe_code = 0x4 236 }, 237 {PMC_EV_PPC970_TIMEBASE_EVENT, 238 .pe_flags = PMC_FLAG_PMC8, 239 .pe_code = 0x5 240 }, 241 #if 0 242 {PMC_EV_PPC970_LSU_COMPLETION_STALL, }, 243 {PMC_EV_PPC970_FXU_COMPLETION_STALL, }, 244 {PMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALL, }, 245 {PMC_EV_PPC970_FPU_COMPLETION_STALL, }, 246 {PMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALL, }, 247 {PMC_EV_PPC970_REJECT_COMPLETION_STALL, }, 248 {PMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALL, }, 249 {PMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISS, }, 250 {PMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISS, }, 251 {PMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICT, }, 252 #endif 253 }; 254 static size_t ppc970_event_codes_size = nitems(ppc970_event_codes); 255 256 static void 257 ppc970_set_pmc(int cpu, int ri, int config) 258 { 259 register_t pmc_mmcr; 260 int config_mask; 261 262 if (config == PMCN_NONE) 263 config = PMC970N_NONE; 264 265 /* 266 * The mask is inverted (enable is 1) compared to the flags in MMCR0, 267 * which are Freeze flags. 268 */ 269 config_mask = ~config & POWERPC_PMC_ENABLE; 270 config &= ~POWERPC_PMC_ENABLE; 271 272 /* 273 * Disable the PMCs. 274 */ 275 switch (ri) { 276 case 0: 277 case 1: 278 pmc_mmcr = mfspr(SPR_MMCR0); 279 pmc_mmcr = PPC970_SET_MMCR0_PMCSEL(pmc_mmcr, config, ri); 280 mtspr(SPR_MMCR0, pmc_mmcr); 281 break; 282 case 2: 283 case 3: 284 case 4: 285 case 5: 286 case 6: 287 case 7: 288 pmc_mmcr = mfspr(SPR_MMCR1); 289 pmc_mmcr = PPC970_SET_MMCR1_PMCSEL(pmc_mmcr, config, ri); 290 mtspr(SPR_MMCR1, pmc_mmcr); 291 break; 292 } 293 294 if (config != PMC970N_NONE) { 295 pmc_mmcr = mfspr(SPR_MMCR0); 296 pmc_mmcr &= ~SPR_MMCR0_FC; 297 pmc_mmcr |= config_mask; 298 mtspr(SPR_MMCR0, pmc_mmcr); 299 } 300 } 301 302 static int 303 ppc970_pcpu_init(struct pmc_mdep *md, int cpu) 304 { 305 powerpc_pcpu_init(md, cpu); 306 307 /* Clear the MMCRs, and set FC, to disable all PMCs. */ 308 /* 970 PMC is not counted when set to 0x08 */ 309 mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE | 310 SPR_MMCR0_FCECE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE | 311 SPR_MMCR0_PMC1SEL(0x8) | SPR_MMCR0_PMC2SEL(0x8)); 312 mtspr(SPR_MMCR1, 0x4218420); 313 314 return (0); 315 } 316 317 static int 318 ppc970_pcpu_fini(struct pmc_mdep *md, int cpu) 319 { 320 register_t mmcr0; 321 322 /* Freeze counters, disable interrupts */ 323 mmcr0 = mfspr(SPR_MMCR0); 324 mmcr0 &= ~SPR_MMCR0_PMXE; 325 mmcr0 |= SPR_MMCR0_FC; 326 mtspr(SPR_MMCR0, mmcr0); 327 328 return (powerpc_pcpu_fini(md, cpu)); 329 } 330 331 static void 332 ppc970_resume_pmc(bool ie) 333 { 334 register_t mmcr0; 335 336 /* Unfreeze counters and re-enable PERF exceptions if requested. */ 337 mmcr0 = mfspr(SPR_MMCR0); 338 mmcr0 &= ~(SPR_MMCR0_FC | SPR_MMCR0_PMXE); 339 if (ie) 340 mmcr0 |= SPR_MMCR0_PMXE; 341 mtspr(SPR_MMCR0, mmcr0); 342 } 343 344 int 345 pmc_ppc970_initialize(struct pmc_mdep *pmc_mdep) 346 { 347 struct pmc_classdep *pcd; 348 349 pmc_mdep->pmd_cputype = PMC_CPU_PPC_970; 350 351 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC]; 352 pcd->pcd_caps = POWERPC_PMC_CAPS; 353 pcd->pcd_class = PMC_CLASS_PPC970; 354 pcd->pcd_num = PPC970_MAX_PMCS; 355 pcd->pcd_ri = pmc_mdep->pmd_npmc; 356 pcd->pcd_width = 32; 357 358 pcd->pcd_allocate_pmc = powerpc_allocate_pmc; 359 pcd->pcd_config_pmc = powerpc_config_pmc; 360 pcd->pcd_pcpu_fini = ppc970_pcpu_fini; 361 pcd->pcd_pcpu_init = ppc970_pcpu_init; 362 pcd->pcd_describe = powerpc_describe; 363 pcd->pcd_get_config = powerpc_get_config; 364 pcd->pcd_read_pmc = powerpc_read_pmc; 365 pcd->pcd_release_pmc = powerpc_release_pmc; 366 pcd->pcd_start_pmc = powerpc_start_pmc; 367 pcd->pcd_stop_pmc = powerpc_stop_pmc; 368 pcd->pcd_write_pmc = powerpc_write_pmc; 369 370 pmc_mdep->pmd_npmc += PPC970_MAX_PMCS; 371 pmc_mdep->pmd_intr = powerpc_pmc_intr; 372 373 ppc_event_codes = ppc970_event_codes; 374 ppc_event_codes_size = ppc970_event_codes_size; 375 ppc_event_first = PMC_EV_PPC970_FIRST; 376 ppc_event_last = PMC_EV_PPC970_LAST; 377 ppc_max_pmcs = PPC970_MAX_PMCS; 378 ppc_class = pcd->pcd_class; 379 380 powerpc_set_pmc = ppc970_set_pmc; 381 powerpc_pmcn_read = powerpc_pmcn_read_default; 382 powerpc_pmcn_write = powerpc_pmcn_write_default; 383 powerpc_resume_pmc = ppc970_resume_pmc; 384 385 return (0); 386 } 387