1 /* 2 * Copyright (c) 2026 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: BSD-2-Clause 5 * 6 * AMD/Intel MPERF/APERF and AMD-only IRPERF MSR counters exposed as an 7 * hwpmc(4) PMC class. 8 * 9 * Read-only, system-scope (PMC_MODE_SC), 64-bit counters reporting 10 * MPERF/APERF and IRPERF MSR values. 11 */ 12 13 #include <sys/param.h> 14 #include <sys/pmc.h> 15 #include <sys/pmckern.h> 16 #include <sys/priv.h> 17 18 #include <machine/specialreg.h> 19 20 #define PERF_CAPS PMC_CAP_READ 21 22 static int perf_npmcs = 0; 23 24 struct perf_descr { 25 struct pmc_descr pm_descr; /* "base class" */ 26 enum pmc_event pm_ev; 27 u_int pm_msr; 28 }; 29 30 static struct perf_descr perf_pmcdesc[PERF_NPMCS_TOTAL]; 31 32 struct perf_cpu { 33 struct pmc_hw tc_hw[PERF_NPMCS_TOTAL]; 34 }; 35 36 static struct perf_cpu **perf_pcpu; 37 static int perf_classindex; 38 39 static int 40 perf_allocate_pmc(int cpu __diagused, int ri __diagused, 41 struct pmc *pm __unused, const struct pmc_op_pmcallocate *a) 42 { 43 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 44 ("[perf,%d] illegal CPU value %d", __LINE__, cpu)); 45 KASSERT(ri >= 0 && ri < perf_npmcs, 46 ("[perf,%d] illegal row index %d", __LINE__, ri)); 47 48 if (a->pm_class != PMC_CLASS_PERF) 49 return (EINVAL); 50 51 if ((a->pm_ev < PMC_EV_PERF_FIRST || a->pm_ev > PMC_EV_PERF_LAST) || 52 a->pm_mode != PMC_MODE_SC) 53 return (EINVAL); 54 55 /* 56 * Allows the PERF class to be accessed only by privileged users. 57 * Frequency is an indirect power proxy and could be abused by 58 * attacks like Hertzbleed. 59 */ 60 if (priv_check(curthread, PRIV_PMC_SYSTEM) != 0) 61 return (EPERM); 62 63 if ((a->pm_caps & PERF_CAPS) == 0) 64 return (EINVAL); 65 if ((a->pm_caps & ~PERF_CAPS) != 0) 66 return (EPERM); 67 68 if (a->pm_ev != perf_pmcdesc[ri].pm_ev) 69 return (EINVAL); 70 71 return (0); 72 } 73 74 static int 75 perf_config_pmc(int cpu, int ri, struct pmc *pm) 76 { 77 struct pmc_hw *phw; 78 79 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 80 81 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 82 ("[perf,%d] illegal CPU value %d", __LINE__, cpu)); 83 KASSERT(ri >= 0 && ri < perf_npmcs, ("[perf,%d] illegal row-index %d", 84 __LINE__, ri)); 85 86 phw = &perf_pcpu[cpu]->tc_hw[ri]; 87 88 KASSERT(pm == NULL || phw->phw_pmc == NULL, 89 ("[perf,%d] pm=%p phw->pm=%p hwpmc not unconfigured", __LINE__, 90 pm, phw->phw_pmc)); 91 92 phw->phw_pmc = pm; 93 94 return (0); 95 } 96 97 static int 98 perf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 99 { 100 const struct perf_descr *pd; 101 struct pmc_hw *phw; 102 103 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 104 ("[perf,%d] illegal CPU %d", __LINE__, cpu)); 105 KASSERT(ri >= 0 && ri < perf_npmcs, ("[perf,%d] illegal row-index %d", 106 __LINE__, ri)); 107 108 phw = &perf_pcpu[cpu]->tc_hw[ri]; 109 pd = &perf_pmcdesc[ri]; 110 111 strlcpy(pi->pm_name, pd->pm_descr.pd_name, sizeof(pi->pm_name)); 112 pi->pm_class = pd->pm_descr.pd_class; 113 114 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 115 pi->pm_enabled = TRUE; 116 *ppmc = phw->phw_pmc; 117 } else { 118 pi->pm_enabled = FALSE; 119 *ppmc = NULL; 120 } 121 122 return (0); 123 } 124 125 static int 126 perf_get_config(int cpu, int ri, struct pmc **ppm) 127 { 128 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 129 ("[perf,%d] illegal CPU %d", __LINE__, cpu)); 130 KASSERT(ri >= 0 && ri < perf_npmcs, ("[perf,%d] illegal row-index %d", 131 __LINE__, ri)); 132 133 *ppm = perf_pcpu[cpu]->tc_hw[ri].phw_pmc; 134 135 return (0); 136 } 137 138 static int 139 perf_get_msr(int ri __diagused, uint32_t *msr __unused) 140 { 141 KASSERT(ri >= 0 && ri < perf_npmcs, 142 ("[perf,%d] ri %d out of range", __LINE__, ri)); 143 144 return (EINVAL); 145 } 146 147 static int 148 perf_pcpu_fini(struct pmc_mdep *md, int cpu) 149 { 150 int i, ri; 151 struct pmc_cpu *pc; 152 153 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 154 ("[perf,%d] illegal cpu %d", __LINE__, cpu)); 155 KASSERT(perf_pcpu[cpu] != NULL, ("[perf,%d] null pcpu", __LINE__)); 156 157 free(perf_pcpu[cpu], M_PMC); 158 perf_pcpu[cpu] = NULL; 159 160 ri = md->pmd_classdep[perf_classindex].pcd_ri; 161 pc = pmc_pcpu[cpu]; 162 163 for (i = 0; i < perf_npmcs; i++) { 164 pc->pc_hwpmcs[i + ri] = NULL; 165 } 166 167 return (0); 168 } 169 170 static int 171 perf_pcpu_init(struct pmc_mdep *md, int cpu) 172 { 173 int i, ri; 174 struct pmc_cpu *pc; 175 struct perf_cpu *perf_pc; 176 177 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 178 ("[perf,%d] illegal cpu %d", __LINE__, cpu)); 179 KASSERT(perf_pcpu, ("[perf,%d] null pcpu", __LINE__)); 180 KASSERT(perf_pcpu[cpu] == NULL, ("[perf,%d] non-null per-cpu", 181 __LINE__)); 182 183 perf_pc = malloc(sizeof(struct perf_cpu), M_PMC, M_WAITOK | M_ZERO); 184 185 perf_pcpu[cpu] = perf_pc; 186 187 ri = md->pmd_classdep[perf_classindex].pcd_ri; 188 189 KASSERT(pmc_pcpu, ("[perf,%d] null generic pcpu", __LINE__)); 190 191 pc = pmc_pcpu[cpu]; 192 193 KASSERT(pc, ("[perf,%d] null generic per-cpu", __LINE__)); 194 195 for (i = 0; i < perf_npmcs; i++) { 196 perf_pc->tc_hw[i].phw_state = PMC_PHW_FLAG_IS_ENABLED | 197 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i) | 198 PMC_PHW_FLAG_IS_SHAREABLE; 199 pc->pc_hwpmcs[i + ri] = &perf_pc->tc_hw[i]; 200 } 201 202 return (0); 203 } 204 205 static int 206 perf_read_pmc(int cpu __diagused, int ri, struct pmc *pm, pmc_value_t *v) 207 { 208 enum pmc_mode mode __diagused; 209 210 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 211 ("[perf,%d] illegal CPU value %d", __LINE__, cpu)); 212 KASSERT(ri >= 0 && ri < perf_npmcs, ("[perf,%d] illegal ri %d", 213 __LINE__, ri)); 214 215 mode = PMC_TO_MODE(pm); 216 217 KASSERT(mode == PMC_MODE_SC, 218 ("[perf,%d] illegal pmc mode %d", __LINE__, mode)); 219 220 PMCDBG1(MDP, REA, 1, "perf-read id=%d", ri); 221 222 *v = rdmsr(perf_pmcdesc[ri].pm_msr); 223 224 return (0); 225 } 226 227 static int 228 perf_write_pmc(int cpu __diagused, int ri __diagused, struct pmc *pm __unused, 229 pmc_value_t v __unused) 230 { 231 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 232 ("[perf,%d] illegal CPU value %d", __LINE__, cpu)); 233 KASSERT(ri >= 0 && ri < perf_npmcs, ("[perf,%d] illegal row-index %d", 234 __LINE__, ri)); 235 236 return (0); 237 } 238 239 static int 240 perf_release_pmc(int cpu __diagused, int ri __diagused, struct pmc *pmc __unused) 241 { 242 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 243 ("[perf,%d] illegal CPU value %d", __LINE__, cpu)); 244 KASSERT(ri >= 0 && ri < perf_npmcs, 245 ("[perf,%d] illegal row-index %d", __LINE__, ri)); 246 KASSERT(perf_pcpu[cpu]->tc_hw[ri].phw_pmc == NULL, 247 ("[perf,%d] PHW pmc non-NULL", __LINE__)); 248 249 return (0); 250 } 251 252 static int 253 perf_start_pmc(int cpu __diagused, int ri __diagused, struct pmc *pm __unused) 254 { 255 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 256 ("[perf,%d] illegal CPU value %d", __LINE__, cpu)); 257 KASSERT(ri >= 0 && ri < perf_npmcs, ("[perf,%d] illegal row-index %d", 258 __LINE__, ri)); 259 260 return (0); 261 } 262 263 static int 264 perf_stop_pmc(int cpu __diagused, int ri __diagused, struct pmc *pm __unused) 265 { 266 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 267 ("[perf,%d] illegal CPU value %d", __LINE__, cpu)); 268 KASSERT(ri >= 0 && ri < perf_npmcs, ("[perf,%d] illegal row-index %d", 269 __LINE__, ri)); 270 271 return (0); 272 } 273 274 int 275 pmc_perf_initialize(struct pmc_mdep *md, int maxcpu, int classindex) 276 { 277 struct pmc_classdep *pcd; 278 279 KASSERT(md != NULL, ("[perf,%d] md is NULL", __LINE__)); 280 KASSERT(md->pmd_nclass >= 1, ("[perf,%d] dubious md->nclass %d", 281 __LINE__, md->pmd_nclass)); 282 283 if ((cpu_power_ecx & CPUID_PERF_STAT) && (tsc_perf_stat == 1)) { 284 strlcpy(perf_pmcdesc[perf_npmcs].pm_descr.pd_name, "MPERF", 285 PMC_NAME_MAX); 286 287 perf_pmcdesc[perf_npmcs].pm_descr.pd_class = PMC_CLASS_PERF; 288 perf_pmcdesc[perf_npmcs].pm_descr.pd_caps = PERF_CAPS; 289 perf_pmcdesc[perf_npmcs].pm_descr.pd_width = 64; 290 perf_pmcdesc[perf_npmcs].pm_msr = MSR_MPERF; 291 perf_pmcdesc[perf_npmcs].pm_ev = PMC_EV_PERF_MPERF; 292 perf_npmcs++; 293 294 strlcpy(perf_pmcdesc[perf_npmcs].pm_descr.pd_name, "APERF", 295 PMC_NAME_MAX); 296 297 perf_pmcdesc[perf_npmcs].pm_descr.pd_class = PMC_CLASS_PERF; 298 perf_pmcdesc[perf_npmcs].pm_descr.pd_caps = PERF_CAPS; 299 perf_pmcdesc[perf_npmcs].pm_descr.pd_width = 64; 300 perf_pmcdesc[perf_npmcs].pm_msr = MSR_APERF; 301 perf_pmcdesc[perf_npmcs].pm_ev = PMC_EV_PERF_APERF; 302 perf_npmcs++; 303 } 304 305 /* 306 * The IRPERF MSR is supported only for AMD CPUs. The feature is 307 * enabled during the boot on each CPU available if AMDFEID_IRPERF 308 * is set on amd_extended_feature_extensions. 309 */ 310 if ((amd_extended_feature_extensions & AMDFEID_IRPERF) && 311 (rdmsr(MSR_HWCR) & HWCR_IRPERFEN)) { 312 strlcpy(perf_pmcdesc[perf_npmcs].pm_descr.pd_name, "IRPERF", 313 PMC_NAME_MAX); 314 315 perf_pmcdesc[perf_npmcs].pm_descr.pd_class = PMC_CLASS_PERF; 316 perf_pmcdesc[perf_npmcs].pm_descr.pd_caps = PERF_CAPS; 317 perf_pmcdesc[perf_npmcs].pm_descr.pd_width = 64; 318 perf_pmcdesc[perf_npmcs].pm_msr = MSR_IRPERF; 319 perf_pmcdesc[perf_npmcs].pm_ev = PMC_EV_PERF_IRPERF; 320 perf_npmcs++; 321 } 322 323 if (perf_npmcs) { 324 325 perf_pcpu = malloc(sizeof(struct perf_cpu *) * maxcpu, M_PMC, 326 M_ZERO | M_WAITOK); 327 328 perf_classindex = classindex; 329 pcd = &md->pmd_classdep[classindex]; 330 331 pcd->pcd_caps = PERF_CAPS; 332 pcd->pcd_class = PMC_CLASS_PERF; 333 pcd->pcd_num = perf_npmcs; 334 pcd->pcd_ri = md->pmd_npmc; 335 pcd->pcd_width = 64; 336 337 pcd->pcd_allocate_pmc = perf_allocate_pmc; 338 pcd->pcd_config_pmc = perf_config_pmc; 339 pcd->pcd_describe = perf_describe; 340 pcd->pcd_get_config = perf_get_config; 341 pcd->pcd_get_msr = perf_get_msr; 342 pcd->pcd_pcpu_init = perf_pcpu_init; 343 pcd->pcd_pcpu_fini = perf_pcpu_fini; 344 pcd->pcd_read_pmc = perf_read_pmc; 345 pcd->pcd_write_pmc = perf_write_pmc; 346 pcd->pcd_release_pmc = perf_release_pmc; 347 pcd->pcd_start_pmc = perf_start_pmc; 348 pcd->pcd_stop_pmc = perf_stop_pmc; 349 350 md->pmd_npmc += perf_npmcs; 351 } 352 353 return (0); 354 } 355 356 void pmc_perf_finalize(struct pmc_mdep *md) 357 { 358 PMCDBG0(MDP, INI, 1, "perf-finalize"); 359 360 if (perf_pcpu != NULL) { 361 for (int i = 0; i < pmc_cpu_max(); i++) 362 KASSERT(perf_pcpu[i] == NULL, 363 ("[perf,%d] non-null pcpu cpu %d", __LINE__, i)); 364 365 free(perf_pcpu, M_PMC); 366 perf_pcpu = NULL; 367 } 368 } 369