1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Common code for handling Intel CPUs. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/pmc.h> 38 #include <sys/pmckern.h> 39 #include <sys/systm.h> 40 41 #include <machine/cpu.h> 42 #include <machine/cputypes.h> 43 #include <machine/md_var.h> 44 #include <machine/specialreg.h> 45 46 static int 47 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 48 { 49 (void) pc; 50 51 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 52 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 53 54 /* allow the RDPMC instruction if needed */ 55 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 56 load_cr4(rcr4() | CR4_PCE); 57 58 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 59 60 return 0; 61 } 62 63 static int 64 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 65 { 66 (void) pc; 67 (void) pp; /* can be NULL */ 68 69 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 70 (uintmax_t) rcr4()); 71 72 /* always turn off the RDPMC instruction */ 73 load_cr4(rcr4() & ~CR4_PCE); 74 75 return 0; 76 } 77 78 struct pmc_mdep * 79 pmc_intel_initialize(void) 80 { 81 struct pmc_mdep *pmc_mdep; 82 enum pmc_cputype cputype; 83 int error, family, model, nclasses, ncpus, stepping, verov; 84 85 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 86 ("[intel,%d] Initializing non-intel processor", __LINE__)); 87 88 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 89 90 cputype = -1; 91 nclasses = 2; 92 error = 0; 93 verov = 0; 94 family = CPUID_TO_FAMILY(cpu_id); 95 model = CPUID_TO_MODEL(cpu_id); 96 stepping = CPUID_TO_STEPPING(cpu_id); 97 98 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "GenuineIntel-%d-%02X-%X", 99 family, model, stepping); 100 101 switch (cpu_id & 0xF00) { 102 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 103 switch (model) { 104 case 0xE: 105 cputype = PMC_CPU_INTEL_CORE; 106 break; 107 case 0xF: 108 /* Per Intel document 315338-020. */ 109 if (stepping == 0x7) { 110 cputype = PMC_CPU_INTEL_CORE; 111 verov = 1; 112 } else { 113 cputype = PMC_CPU_INTEL_CORE2; 114 nclasses = 3; 115 } 116 break; 117 case 0x17: 118 cputype = PMC_CPU_INTEL_CORE2EXTREME; 119 nclasses = 3; 120 break; 121 case 0x1C: /* Per Intel document 320047-002. */ 122 cputype = PMC_CPU_INTEL_ATOM; 123 nclasses = 3; 124 break; 125 case 0x1A: 126 case 0x1E: /* 127 * Per Intel document 253669-032 9/2009, 128 * pages A-2 and A-57 129 */ 130 case 0x1F: /* 131 * Per Intel document 253669-032 9/2009, 132 * pages A-2 and A-57 133 */ 134 cputype = PMC_CPU_INTEL_COREI7; 135 nclasses = 5; 136 break; 137 case 0x2E: 138 cputype = PMC_CPU_INTEL_NEHALEM_EX; 139 nclasses = 3; 140 break; 141 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 142 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 143 cputype = PMC_CPU_INTEL_WESTMERE; 144 nclasses = 5; 145 break; 146 case 0x2F: /* Westmere-EX, seen in wild */ 147 cputype = PMC_CPU_INTEL_WESTMERE_EX; 148 nclasses = 3; 149 break; 150 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 151 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 152 nclasses = 5; 153 break; 154 case 0x2D: /* Per Intel document 253669-044US 08/2012. */ 155 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; 156 nclasses = 3; 157 break; 158 case 0x3A: /* Per Intel document 253669-043US 05/2012. */ 159 cputype = PMC_CPU_INTEL_IVYBRIDGE; 160 nclasses = 3; 161 break; 162 case 0x3E: /* Per Intel document 325462-045US 01/2013. */ 163 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; 164 nclasses = 3; 165 break; 166 /* Skylake */ 167 case 0x4e: 168 case 0x5e: 169 /* Kabylake */ 170 case 0x8E: /* Per Intel document 325462-063US July 2017. */ 171 case 0x9E: /* Per Intel document 325462-063US July 2017. */ 172 cputype = PMC_CPU_INTEL_SKYLAKE; 173 nclasses = 3; 174 break; 175 case 0x55: /* SDM rev 63 */ 176 cputype = PMC_CPU_INTEL_SKYLAKE_XEON; 177 nclasses = 3; 178 break; 179 case 0x3D: 180 case 0x47: 181 cputype = PMC_CPU_INTEL_BROADWELL; 182 nclasses = 3; 183 break; 184 case 0x4f: 185 case 0x56: 186 cputype = PMC_CPU_INTEL_BROADWELL_XEON; 187 nclasses = 3; 188 break; 189 case 0x3F: /* Per Intel document 325462-045US 09/2014. */ 190 case 0x46: /* Per Intel document 325462-045US 09/2014. */ 191 /* Should 46 be XEON. probably its own? */ 192 cputype = PMC_CPU_INTEL_HASWELL_XEON; 193 nclasses = 3; 194 break; 195 case 0x3C: /* Per Intel document 325462-045US 01/2013. */ 196 case 0x45: /* Per Intel document 325462-045US 09/2014. */ 197 cputype = PMC_CPU_INTEL_HASWELL; 198 nclasses = 5; 199 break; 200 case 0x37: 201 case 0x4A: 202 case 0x4D: /* Per Intel document 330061-001 01/2014. */ 203 case 0x5A: 204 case 0x5D: 205 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT; 206 nclasses = 3; 207 break; 208 case 0x5C: /* Per Intel document 325462-071US 10/2019. */ 209 case 0x5F: 210 cputype = PMC_CPU_INTEL_ATOM_GOLDMONT; 211 nclasses = 3; 212 break; 213 } 214 break; 215 } 216 217 218 if ((int) cputype == -1) { 219 printf("pmc: Unknown Intel CPU.\n"); 220 return (NULL); 221 } 222 223 /* Allocate base class and initialize machine dependent struct */ 224 pmc_mdep = pmc_mdep_alloc(nclasses); 225 226 pmc_mdep->pmd_cputype = cputype; 227 pmc_mdep->pmd_switch_in = intel_switch_in; 228 pmc_mdep->pmd_switch_out = intel_switch_out; 229 230 ncpus = pmc_cpu_max(); 231 error = pmc_tsc_initialize(pmc_mdep, ncpus); 232 if (error) 233 goto error; 234 switch (cputype) { 235 /* 236 * Intel Core, Core 2 and Atom processors. 237 */ 238 case PMC_CPU_INTEL_ATOM: 239 case PMC_CPU_INTEL_ATOM_SILVERMONT: 240 case PMC_CPU_INTEL_ATOM_GOLDMONT: 241 case PMC_CPU_INTEL_BROADWELL: 242 case PMC_CPU_INTEL_BROADWELL_XEON: 243 case PMC_CPU_INTEL_SKYLAKE_XEON: 244 case PMC_CPU_INTEL_SKYLAKE: 245 case PMC_CPU_INTEL_CORE: 246 case PMC_CPU_INTEL_CORE2: 247 case PMC_CPU_INTEL_CORE2EXTREME: 248 case PMC_CPU_INTEL_COREI7: 249 case PMC_CPU_INTEL_NEHALEM_EX: 250 case PMC_CPU_INTEL_IVYBRIDGE: 251 case PMC_CPU_INTEL_SANDYBRIDGE: 252 case PMC_CPU_INTEL_WESTMERE: 253 case PMC_CPU_INTEL_WESTMERE_EX: 254 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 255 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 256 case PMC_CPU_INTEL_HASWELL: 257 case PMC_CPU_INTEL_HASWELL_XEON: 258 error = pmc_core_initialize(pmc_mdep, ncpus, verov); 259 break; 260 261 default: 262 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 263 } 264 265 if (error) { 266 pmc_tsc_finalize(pmc_mdep); 267 goto error; 268 } 269 270 /* 271 * Init the uncore class. 272 */ 273 switch (cputype) { 274 /* 275 * Intel Corei7 and Westmere processors. 276 */ 277 case PMC_CPU_INTEL_COREI7: 278 case PMC_CPU_INTEL_HASWELL: 279 case PMC_CPU_INTEL_SANDYBRIDGE: 280 case PMC_CPU_INTEL_WESTMERE: 281 case PMC_CPU_INTEL_BROADWELL: 282 error = pmc_uncore_initialize(pmc_mdep, ncpus); 283 break; 284 default: 285 break; 286 } 287 error: 288 if (error) { 289 pmc_mdep_free(pmc_mdep); 290 pmc_mdep = NULL; 291 } 292 293 return (pmc_mdep); 294 } 295 296 void 297 pmc_intel_finalize(struct pmc_mdep *md) 298 { 299 pmc_tsc_finalize(md); 300 301 switch (md->pmd_cputype) { 302 case PMC_CPU_INTEL_ATOM: 303 case PMC_CPU_INTEL_ATOM_SILVERMONT: 304 case PMC_CPU_INTEL_ATOM_GOLDMONT: 305 case PMC_CPU_INTEL_BROADWELL: 306 case PMC_CPU_INTEL_BROADWELL_XEON: 307 case PMC_CPU_INTEL_SKYLAKE_XEON: 308 case PMC_CPU_INTEL_SKYLAKE: 309 case PMC_CPU_INTEL_CORE: 310 case PMC_CPU_INTEL_CORE2: 311 case PMC_CPU_INTEL_CORE2EXTREME: 312 case PMC_CPU_INTEL_COREI7: 313 case PMC_CPU_INTEL_NEHALEM_EX: 314 case PMC_CPU_INTEL_HASWELL: 315 case PMC_CPU_INTEL_HASWELL_XEON: 316 case PMC_CPU_INTEL_IVYBRIDGE: 317 case PMC_CPU_INTEL_SANDYBRIDGE: 318 case PMC_CPU_INTEL_WESTMERE: 319 case PMC_CPU_INTEL_WESTMERE_EX: 320 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 321 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 322 pmc_core_finalize(md); 323 break; 324 default: 325 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 326 } 327 328 /* 329 * Uncore. 330 */ 331 switch (md->pmd_cputype) { 332 case PMC_CPU_INTEL_BROADWELL: 333 case PMC_CPU_INTEL_COREI7: 334 case PMC_CPU_INTEL_HASWELL: 335 case PMC_CPU_INTEL_SANDYBRIDGE: 336 case PMC_CPU_INTEL_WESTMERE: 337 pmc_uncore_finalize(md); 338 break; 339 default: 340 break; 341 } 342 } 343