1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Common code for handling Intel CPUs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/pmc.h> 36 #include <sys/pmckern.h> 37 #include <sys/systm.h> 38 39 #include <machine/cpu.h> 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/specialreg.h> 43 44 static int 45 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 46 { 47 (void) pc; 48 49 PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 51 52 /* allow the RDPMC instruction if needed */ 53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 54 load_cr4(rcr4() | CR4_PCE); 55 56 PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 57 58 return 0; 59 } 60 61 static int 62 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 63 { 64 (void) pc; 65 (void) pp; /* can be NULL */ 66 67 PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 68 (uintmax_t) rcr4()); 69 70 /* always turn off the RDPMC instruction */ 71 load_cr4(rcr4() & ~CR4_PCE); 72 73 return 0; 74 } 75 76 struct pmc_mdep * 77 pmc_intel_initialize(void) 78 { 79 struct pmc_mdep *pmc_mdep; 80 enum pmc_cputype cputype; 81 int error, model, nclasses, ncpus; 82 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 91 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 92 93 switch (cpu_id & 0xF00) { 94 #if defined(__i386__) 95 case 0x500: /* Pentium family processors */ 96 cputype = PMC_CPU_INTEL_P5; 97 break; 98 #endif 99 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 100 switch (model) { 101 #if defined(__i386__) 102 case 0x1: 103 cputype = PMC_CPU_INTEL_P6; 104 break; 105 case 0x3: case 0x5: 106 cputype = PMC_CPU_INTEL_PII; 107 break; 108 case 0x6: case 0x16: 109 cputype = PMC_CPU_INTEL_CL; 110 break; 111 case 0x7: case 0x8: case 0xA: case 0xB: 112 cputype = PMC_CPU_INTEL_PIII; 113 break; 114 case 0x9: case 0xD: 115 cputype = PMC_CPU_INTEL_PM; 116 break; 117 #endif 118 case 0xE: 119 cputype = PMC_CPU_INTEL_CORE; 120 break; 121 case 0xF: 122 cputype = PMC_CPU_INTEL_CORE2; 123 nclasses = 3; 124 break; 125 case 0x17: 126 cputype = PMC_CPU_INTEL_CORE2EXTREME; 127 nclasses = 3; 128 break; 129 case 0x1C: /* Per Intel document 320047-002. */ 130 cputype = PMC_CPU_INTEL_ATOM; 131 nclasses = 3; 132 break; 133 case 0x1A: 134 case 0x1E: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */ 135 case 0x1F: /* Per Intel document 253669-032 9/2009, pages A-2 and A-57 */ 136 case 0x2E: 137 cputype = PMC_CPU_INTEL_COREI7; 138 nclasses = 5; 139 break; 140 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 141 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 142 cputype = PMC_CPU_INTEL_WESTMERE; 143 nclasses = 5; 144 break; 145 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 146 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 147 nclasses = 5; 148 break; 149 case 0x3A: /* Per Intel document 253669-043US 05/2012. */ 150 cputype = PMC_CPU_INTEL_IVYBRIDGE; 151 nclasses = 3; 152 break; 153 } 154 break; 155 #if defined(__i386__) || defined(__amd64__) 156 case 0xF00: /* P4 */ 157 if (model >= 0 && model <= 6) /* known models */ 158 cputype = PMC_CPU_INTEL_PIV; 159 break; 160 } 161 #endif 162 163 if ((int) cputype == -1) { 164 printf("pmc: Unknown Intel CPU.\n"); 165 return (NULL); 166 } 167 168 /* Allocate base class and initialize machine dependent struct */ 169 pmc_mdep = pmc_mdep_alloc(nclasses); 170 171 pmc_mdep->pmd_cputype = cputype; 172 pmc_mdep->pmd_switch_in = intel_switch_in; 173 pmc_mdep->pmd_switch_out = intel_switch_out; 174 175 ncpus = pmc_cpu_max(); 176 177 error = pmc_tsc_initialize(pmc_mdep, ncpus); 178 if (error) 179 goto error; 180 181 switch (cputype) { 182 #if defined(__i386__) || defined(__amd64__) 183 /* 184 * Intel Core, Core 2 and Atom processors. 185 */ 186 case PMC_CPU_INTEL_ATOM: 187 case PMC_CPU_INTEL_CORE: 188 case PMC_CPU_INTEL_CORE2: 189 case PMC_CPU_INTEL_CORE2EXTREME: 190 case PMC_CPU_INTEL_COREI7: 191 case PMC_CPU_INTEL_IVYBRIDGE: 192 case PMC_CPU_INTEL_SANDYBRIDGE: 193 case PMC_CPU_INTEL_WESTMERE: 194 error = pmc_core_initialize(pmc_mdep, ncpus); 195 break; 196 197 /* 198 * Intel Pentium 4 Processors, and P4/EMT64 processors. 199 */ 200 201 case PMC_CPU_INTEL_PIV: 202 error = pmc_p4_initialize(pmc_mdep, ncpus); 203 break; 204 #endif 205 206 #if defined(__i386__) 207 /* 208 * P6 Family Processors 209 */ 210 211 case PMC_CPU_INTEL_P6: 212 case PMC_CPU_INTEL_CL: 213 case PMC_CPU_INTEL_PII: 214 case PMC_CPU_INTEL_PIII: 215 case PMC_CPU_INTEL_PM: 216 error = pmc_p6_initialize(pmc_mdep, ncpus); 217 break; 218 219 /* 220 * Intel Pentium PMCs. 221 */ 222 223 case PMC_CPU_INTEL_P5: 224 error = pmc_p5_initialize(pmc_mdep, ncpus); 225 break; 226 #endif 227 228 default: 229 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 230 } 231 232 if (error) 233 goto error; 234 235 /* 236 * Init the uncore class. 237 */ 238 #if defined(__i386__) || defined(__amd64__) 239 switch (cputype) { 240 /* 241 * Intel Corei7 and Westmere processors. 242 */ 243 case PMC_CPU_INTEL_COREI7: 244 case PMC_CPU_INTEL_SANDYBRIDGE: 245 case PMC_CPU_INTEL_WESTMERE: 246 error = pmc_uncore_initialize(pmc_mdep, ncpus); 247 break; 248 default: 249 break; 250 } 251 #endif 252 253 error: 254 if (error) { 255 free(pmc_mdep, M_PMC); 256 pmc_mdep = NULL; 257 } 258 259 return (pmc_mdep); 260 } 261 262 void 263 pmc_intel_finalize(struct pmc_mdep *md) 264 { 265 pmc_tsc_finalize(md); 266 267 switch (md->pmd_cputype) { 268 #if defined(__i386__) || defined(__amd64__) 269 case PMC_CPU_INTEL_ATOM: 270 case PMC_CPU_INTEL_CORE: 271 case PMC_CPU_INTEL_CORE2: 272 case PMC_CPU_INTEL_CORE2EXTREME: 273 case PMC_CPU_INTEL_COREI7: 274 case PMC_CPU_INTEL_IVYBRIDGE: 275 case PMC_CPU_INTEL_SANDYBRIDGE: 276 case PMC_CPU_INTEL_WESTMERE: 277 pmc_core_finalize(md); 278 break; 279 280 case PMC_CPU_INTEL_PIV: 281 pmc_p4_finalize(md); 282 break; 283 #endif 284 #if defined(__i386__) 285 case PMC_CPU_INTEL_P6: 286 case PMC_CPU_INTEL_CL: 287 case PMC_CPU_INTEL_PII: 288 case PMC_CPU_INTEL_PIII: 289 case PMC_CPU_INTEL_PM: 290 pmc_p6_finalize(md); 291 break; 292 case PMC_CPU_INTEL_P5: 293 pmc_p5_finalize(md); 294 break; 295 #endif 296 default: 297 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 298 } 299 300 /* 301 * Uncore. 302 */ 303 #if defined(__i386__) || defined(__amd64__) 304 switch (md->pmd_cputype) { 305 case PMC_CPU_INTEL_COREI7: 306 case PMC_CPU_INTEL_SANDYBRIDGE: 307 case PMC_CPU_INTEL_WESTMERE: 308 pmc_uncore_finalize(md); 309 break; 310 default: 311 break; 312 } 313 #endif 314 } 315