1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Common code for handling Intel CPUs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/pmc.h> 36 #include <sys/pmckern.h> 37 #include <sys/systm.h> 38 39 #include <machine/cpu.h> 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/specialreg.h> 43 44 static int 45 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 46 { 47 (void) pc; 48 49 PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 51 52 /* allow the RDPMC instruction if needed */ 53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 54 load_cr4(rcr4() | CR4_PCE); 55 56 PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 57 58 return 0; 59 } 60 61 static int 62 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 63 { 64 (void) pc; 65 (void) pp; /* can be NULL */ 66 67 PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 68 (uintmax_t) rcr4()); 69 70 /* always turn off the RDPMC instruction */ 71 load_cr4(rcr4() & ~CR4_PCE); 72 73 return 0; 74 } 75 76 struct pmc_mdep * 77 pmc_intel_initialize(void) 78 { 79 struct pmc_mdep *pmc_mdep; 80 enum pmc_cputype cputype; 81 int error, model, nclasses, ncpus, stepping, verov; 82 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 error = 0; 91 verov = 0; 92 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 93 stepping = cpu_id & 0xF; 94 95 switch (cpu_id & 0xF00) { 96 #if defined(__i386__) 97 case 0x500: /* Pentium family processors */ 98 cputype = PMC_CPU_INTEL_P5; 99 break; 100 #endif 101 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 102 switch (model) { 103 #if defined(__i386__) 104 case 0x1: 105 cputype = PMC_CPU_INTEL_P6; 106 break; 107 case 0x3: case 0x5: 108 cputype = PMC_CPU_INTEL_PII; 109 break; 110 case 0x6: case 0x16: 111 cputype = PMC_CPU_INTEL_CL; 112 break; 113 case 0x7: case 0x8: case 0xA: case 0xB: 114 cputype = PMC_CPU_INTEL_PIII; 115 break; 116 case 0x9: case 0xD: 117 cputype = PMC_CPU_INTEL_PM; 118 break; 119 #endif 120 case 0xE: 121 cputype = PMC_CPU_INTEL_CORE; 122 break; 123 case 0xF: 124 /* Per Intel document 315338-020. */ 125 if (stepping == 0x7) { 126 cputype = PMC_CPU_INTEL_CORE; 127 verov = 1; 128 } else { 129 cputype = PMC_CPU_INTEL_CORE2; 130 nclasses = 3; 131 } 132 break; 133 case 0x17: 134 cputype = PMC_CPU_INTEL_CORE2EXTREME; 135 nclasses = 3; 136 break; 137 case 0x1C: /* Per Intel document 320047-002. */ 138 cputype = PMC_CPU_INTEL_ATOM; 139 nclasses = 3; 140 break; 141 case 0x1A: 142 case 0x1E: /* 143 * Per Intel document 253669-032 9/2009, 144 * pages A-2 and A-57 145 */ 146 case 0x1F: /* 147 * Per Intel document 253669-032 9/2009, 148 * pages A-2 and A-57 149 */ 150 case 0x2E: 151 cputype = PMC_CPU_INTEL_COREI7; 152 nclasses = 5; 153 break; 154 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 155 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 156 cputype = PMC_CPU_INTEL_WESTMERE; 157 nclasses = 5; 158 break; 159 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 160 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 161 nclasses = 5; 162 break; 163 case 0x2D: /* Per Intel document 253669-044US 08/2012. */ 164 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; 165 nclasses = 3; 166 break; 167 case 0x3A: /* Per Intel document 253669-043US 05/2012. */ 168 cputype = PMC_CPU_INTEL_IVYBRIDGE; 169 nclasses = 3; 170 break; 171 case 0x3E: /* Per Intel document 325462-045US 01/2013. */ 172 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; 173 nclasses = 3; 174 break; 175 case 0x3C: /* Per Intel document 325462-045US 01/2013. */ 176 case 0x45: 177 cputype = PMC_CPU_INTEL_HASWELL; 178 nclasses = 5; 179 break; 180 } 181 break; 182 #if defined(__i386__) || defined(__amd64__) 183 case 0xF00: /* P4 */ 184 if (model >= 0 && model <= 6) /* known models */ 185 cputype = PMC_CPU_INTEL_PIV; 186 break; 187 } 188 #endif 189 190 if ((int) cputype == -1) { 191 printf("pmc: Unknown Intel CPU.\n"); 192 return (NULL); 193 } 194 195 /* Allocate base class and initialize machine dependent struct */ 196 pmc_mdep = pmc_mdep_alloc(nclasses); 197 198 pmc_mdep->pmd_cputype = cputype; 199 pmc_mdep->pmd_switch_in = intel_switch_in; 200 pmc_mdep->pmd_switch_out = intel_switch_out; 201 202 ncpus = pmc_cpu_max(); 203 error = pmc_tsc_initialize(pmc_mdep, ncpus); 204 if (error) 205 goto error; 206 switch (cputype) { 207 #if defined(__i386__) || defined(__amd64__) 208 /* 209 * Intel Core, Core 2 and Atom processors. 210 */ 211 case PMC_CPU_INTEL_ATOM: 212 case PMC_CPU_INTEL_CORE: 213 case PMC_CPU_INTEL_CORE2: 214 case PMC_CPU_INTEL_CORE2EXTREME: 215 case PMC_CPU_INTEL_COREI7: 216 case PMC_CPU_INTEL_IVYBRIDGE: 217 case PMC_CPU_INTEL_SANDYBRIDGE: 218 case PMC_CPU_INTEL_WESTMERE: 219 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 220 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 221 case PMC_CPU_INTEL_HASWELL: 222 error = pmc_core_initialize(pmc_mdep, ncpus, verov); 223 break; 224 225 /* 226 * Intel Pentium 4 Processors, and P4/EMT64 processors. 227 */ 228 229 case PMC_CPU_INTEL_PIV: 230 error = pmc_p4_initialize(pmc_mdep, ncpus); 231 break; 232 #endif 233 234 #if defined(__i386__) 235 /* 236 * P6 Family Processors 237 */ 238 239 case PMC_CPU_INTEL_P6: 240 case PMC_CPU_INTEL_CL: 241 case PMC_CPU_INTEL_PII: 242 case PMC_CPU_INTEL_PIII: 243 case PMC_CPU_INTEL_PM: 244 error = pmc_p6_initialize(pmc_mdep, ncpus); 245 break; 246 247 /* 248 * Intel Pentium PMCs. 249 */ 250 251 case PMC_CPU_INTEL_P5: 252 error = pmc_p5_initialize(pmc_mdep, ncpus); 253 break; 254 #endif 255 256 default: 257 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 258 } 259 260 if (error) { 261 pmc_tsc_finalize(pmc_mdep); 262 goto error; 263 } 264 265 /* 266 * Init the uncore class. 267 */ 268 #if defined(__i386__) || defined(__amd64__) 269 switch (cputype) { 270 /* 271 * Intel Corei7 and Westmere processors. 272 */ 273 case PMC_CPU_INTEL_COREI7: 274 case PMC_CPU_INTEL_HASWELL: 275 case PMC_CPU_INTEL_SANDYBRIDGE: 276 case PMC_CPU_INTEL_WESTMERE: 277 error = pmc_uncore_initialize(pmc_mdep, ncpus); 278 break; 279 default: 280 break; 281 } 282 #endif 283 error: 284 if (error) { 285 pmc_mdep_free(pmc_mdep); 286 pmc_mdep = NULL; 287 } 288 289 return (pmc_mdep); 290 } 291 292 void 293 pmc_intel_finalize(struct pmc_mdep *md) 294 { 295 pmc_tsc_finalize(md); 296 297 switch (md->pmd_cputype) { 298 #if defined(__i386__) || defined(__amd64__) 299 case PMC_CPU_INTEL_ATOM: 300 case PMC_CPU_INTEL_CORE: 301 case PMC_CPU_INTEL_CORE2: 302 case PMC_CPU_INTEL_CORE2EXTREME: 303 case PMC_CPU_INTEL_COREI7: 304 case PMC_CPU_INTEL_HASWELL: 305 case PMC_CPU_INTEL_IVYBRIDGE: 306 case PMC_CPU_INTEL_SANDYBRIDGE: 307 case PMC_CPU_INTEL_WESTMERE: 308 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 309 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 310 pmc_core_finalize(md); 311 break; 312 313 case PMC_CPU_INTEL_PIV: 314 pmc_p4_finalize(md); 315 break; 316 #endif 317 #if defined(__i386__) 318 case PMC_CPU_INTEL_P6: 319 case PMC_CPU_INTEL_CL: 320 case PMC_CPU_INTEL_PII: 321 case PMC_CPU_INTEL_PIII: 322 case PMC_CPU_INTEL_PM: 323 pmc_p6_finalize(md); 324 break; 325 case PMC_CPU_INTEL_P5: 326 pmc_p5_finalize(md); 327 break; 328 #endif 329 default: 330 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 331 } 332 333 /* 334 * Uncore. 335 */ 336 #if defined(__i386__) || defined(__amd64__) 337 switch (md->pmd_cputype) { 338 case PMC_CPU_INTEL_COREI7: 339 case PMC_CPU_INTEL_HASWELL: 340 case PMC_CPU_INTEL_SANDYBRIDGE: 341 case PMC_CPU_INTEL_WESTMERE: 342 pmc_uncore_finalize(md); 343 break; 344 default: 345 break; 346 } 347 #endif 348 } 349