1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Common code for handling Intel CPUs. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/pmc.h> 38 #include <sys/pmckern.h> 39 #include <sys/systm.h> 40 41 #include <machine/cpu.h> 42 #include <machine/cputypes.h> 43 #include <machine/md_var.h> 44 #include <machine/specialreg.h> 45 46 static int 47 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 48 { 49 (void) pc; 50 51 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 52 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 53 54 /* allow the RDPMC instruction if needed */ 55 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 56 load_cr4(rcr4() | CR4_PCE); 57 58 PMCDBG1(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 59 60 return 0; 61 } 62 63 static int 64 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 65 { 66 (void) pc; 67 (void) pp; /* can be NULL */ 68 69 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 70 (uintmax_t) rcr4()); 71 72 /* always turn off the RDPMC instruction */ 73 load_cr4(rcr4() & ~CR4_PCE); 74 75 return 0; 76 } 77 78 struct pmc_mdep * 79 pmc_intel_initialize(void) 80 { 81 struct pmc_mdep *pmc_mdep; 82 enum pmc_cputype cputype; 83 int error, model, nclasses, ncpus, stepping, verov; 84 85 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 86 ("[intel,%d] Initializing non-intel processor", __LINE__)); 87 88 PMCDBG1(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 89 90 cputype = -1; 91 nclasses = 2; 92 error = 0; 93 verov = 0; 94 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 95 stepping = cpu_id & 0xF; 96 97 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "GenuineIntel-%d-%02X", 98 (cpu_id & 0xF00) >> 8, model); 99 switch (cpu_id & 0xF00) { 100 #if defined(__i386__) 101 case 0x500: /* Pentium family processors */ 102 cputype = PMC_CPU_INTEL_P5; 103 break; 104 #endif 105 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 106 switch (model) { 107 #if defined(__i386__) 108 case 0x1: 109 cputype = PMC_CPU_INTEL_P6; 110 break; 111 case 0x3: case 0x5: 112 cputype = PMC_CPU_INTEL_PII; 113 break; 114 case 0x6: case 0x16: 115 cputype = PMC_CPU_INTEL_CL; 116 break; 117 case 0x7: case 0x8: case 0xA: case 0xB: 118 cputype = PMC_CPU_INTEL_PIII; 119 break; 120 case 0x9: case 0xD: 121 cputype = PMC_CPU_INTEL_PM; 122 break; 123 #endif 124 case 0xE: 125 cputype = PMC_CPU_INTEL_CORE; 126 break; 127 case 0xF: 128 /* Per Intel document 315338-020. */ 129 if (stepping == 0x7) { 130 cputype = PMC_CPU_INTEL_CORE; 131 verov = 1; 132 } else { 133 cputype = PMC_CPU_INTEL_CORE2; 134 nclasses = 3; 135 } 136 break; 137 case 0x17: 138 cputype = PMC_CPU_INTEL_CORE2EXTREME; 139 nclasses = 3; 140 break; 141 case 0x1C: /* Per Intel document 320047-002. */ 142 cputype = PMC_CPU_INTEL_ATOM; 143 nclasses = 3; 144 break; 145 case 0x1A: 146 case 0x1E: /* 147 * Per Intel document 253669-032 9/2009, 148 * pages A-2 and A-57 149 */ 150 case 0x1F: /* 151 * Per Intel document 253669-032 9/2009, 152 * pages A-2 and A-57 153 */ 154 cputype = PMC_CPU_INTEL_COREI7; 155 nclasses = 5; 156 break; 157 case 0x2E: 158 cputype = PMC_CPU_INTEL_NEHALEM_EX; 159 nclasses = 3; 160 break; 161 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 162 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 163 cputype = PMC_CPU_INTEL_WESTMERE; 164 nclasses = 5; 165 break; 166 case 0x2F: /* Westmere-EX, seen in wild */ 167 cputype = PMC_CPU_INTEL_WESTMERE_EX; 168 nclasses = 3; 169 break; 170 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 171 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 172 nclasses = 5; 173 break; 174 case 0x2D: /* Per Intel document 253669-044US 08/2012. */ 175 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; 176 nclasses = 3; 177 break; 178 case 0x3A: /* Per Intel document 253669-043US 05/2012. */ 179 cputype = PMC_CPU_INTEL_IVYBRIDGE; 180 nclasses = 3; 181 break; 182 case 0x3E: /* Per Intel document 325462-045US 01/2013. */ 183 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; 184 nclasses = 3; 185 break; 186 /* Skylake */ 187 case 0x4e: 188 case 0x5e: 189 /* Kabylake */ 190 case 0x8E: /* Per Intel document 325462-063US July 2017. */ 191 case 0x9E: /* Per Intel document 325462-063US July 2017. */ 192 cputype = PMC_CPU_INTEL_SKYLAKE; 193 nclasses = 3; 194 break; 195 case 0x55: /* SDM rev 63 */ 196 cputype = PMC_CPU_INTEL_SKYLAKE_XEON; 197 nclasses = 3; 198 break; 199 case 0x3D: 200 case 0x47: 201 cputype = PMC_CPU_INTEL_BROADWELL; 202 nclasses = 3; 203 break; 204 case 0x4f: 205 case 0x56: 206 cputype = PMC_CPU_INTEL_BROADWELL_XEON; 207 nclasses = 3; 208 break; 209 case 0x3F: /* Per Intel document 325462-045US 09/2014. */ 210 case 0x46: /* Per Intel document 325462-045US 09/2014. */ 211 /* Should 46 be XEON. probably its own? */ 212 cputype = PMC_CPU_INTEL_HASWELL_XEON; 213 nclasses = 3; 214 break; 215 case 0x3C: /* Per Intel document 325462-045US 01/2013. */ 216 case 0x45: /* Per Intel document 325462-045US 09/2014. */ 217 cputype = PMC_CPU_INTEL_HASWELL; 218 nclasses = 5; 219 break; 220 case 0x4D: /* Per Intel document 330061-001 01/2014. */ 221 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT; 222 nclasses = 3; 223 break; 224 } 225 break; 226 #if defined(__i386__) || defined(__amd64__) 227 case 0xF00: /* P4 */ 228 if (model >= 0 && model <= 6) /* known models */ 229 cputype = PMC_CPU_INTEL_PIV; 230 break; 231 } 232 #endif 233 234 if ((int) cputype == -1) { 235 printf("pmc: Unknown Intel CPU.\n"); 236 return (NULL); 237 } 238 239 /* Allocate base class and initialize machine dependent struct */ 240 pmc_mdep = pmc_mdep_alloc(nclasses); 241 242 pmc_mdep->pmd_cputype = cputype; 243 pmc_mdep->pmd_switch_in = intel_switch_in; 244 pmc_mdep->pmd_switch_out = intel_switch_out; 245 246 ncpus = pmc_cpu_max(); 247 error = pmc_tsc_initialize(pmc_mdep, ncpus); 248 if (error) 249 goto error; 250 switch (cputype) { 251 #if defined(__i386__) || defined(__amd64__) 252 /* 253 * Intel Core, Core 2 and Atom processors. 254 */ 255 case PMC_CPU_INTEL_ATOM: 256 case PMC_CPU_INTEL_ATOM_SILVERMONT: 257 case PMC_CPU_INTEL_BROADWELL: 258 case PMC_CPU_INTEL_BROADWELL_XEON: 259 case PMC_CPU_INTEL_SKYLAKE_XEON: 260 case PMC_CPU_INTEL_SKYLAKE: 261 case PMC_CPU_INTEL_CORE: 262 case PMC_CPU_INTEL_CORE2: 263 case PMC_CPU_INTEL_CORE2EXTREME: 264 case PMC_CPU_INTEL_COREI7: 265 case PMC_CPU_INTEL_NEHALEM_EX: 266 case PMC_CPU_INTEL_IVYBRIDGE: 267 case PMC_CPU_INTEL_SANDYBRIDGE: 268 case PMC_CPU_INTEL_WESTMERE: 269 case PMC_CPU_INTEL_WESTMERE_EX: 270 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 271 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 272 case PMC_CPU_INTEL_HASWELL: 273 case PMC_CPU_INTEL_HASWELL_XEON: 274 error = pmc_core_initialize(pmc_mdep, ncpus, verov); 275 break; 276 277 /* 278 * Intel Pentium 4 Processors, and P4/EMT64 processors. 279 */ 280 281 case PMC_CPU_INTEL_PIV: 282 error = pmc_p4_initialize(pmc_mdep, ncpus); 283 break; 284 #endif 285 286 #if defined(__i386__) 287 /* 288 * P6 Family Processors 289 */ 290 291 case PMC_CPU_INTEL_P6: 292 case PMC_CPU_INTEL_CL: 293 case PMC_CPU_INTEL_PII: 294 case PMC_CPU_INTEL_PIII: 295 case PMC_CPU_INTEL_PM: 296 error = pmc_p6_initialize(pmc_mdep, ncpus); 297 break; 298 299 /* 300 * Intel Pentium PMCs. 301 */ 302 303 case PMC_CPU_INTEL_P5: 304 error = pmc_p5_initialize(pmc_mdep, ncpus); 305 break; 306 #endif 307 308 default: 309 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 310 } 311 312 if (error) { 313 pmc_tsc_finalize(pmc_mdep); 314 goto error; 315 } 316 317 /* 318 * Init the uncore class. 319 */ 320 #if defined(__i386__) || defined(__amd64__) 321 switch (cputype) { 322 /* 323 * Intel Corei7 and Westmere processors. 324 */ 325 case PMC_CPU_INTEL_COREI7: 326 case PMC_CPU_INTEL_HASWELL: 327 case PMC_CPU_INTEL_SANDYBRIDGE: 328 case PMC_CPU_INTEL_WESTMERE: 329 case PMC_CPU_INTEL_BROADWELL: 330 error = pmc_uncore_initialize(pmc_mdep, ncpus); 331 break; 332 default: 333 break; 334 } 335 #endif 336 error: 337 if (error) { 338 pmc_mdep_free(pmc_mdep); 339 pmc_mdep = NULL; 340 } 341 342 return (pmc_mdep); 343 } 344 345 void 346 pmc_intel_finalize(struct pmc_mdep *md) 347 { 348 pmc_tsc_finalize(md); 349 350 switch (md->pmd_cputype) { 351 #if defined(__i386__) || defined(__amd64__) 352 case PMC_CPU_INTEL_ATOM: 353 case PMC_CPU_INTEL_ATOM_SILVERMONT: 354 case PMC_CPU_INTEL_BROADWELL: 355 case PMC_CPU_INTEL_BROADWELL_XEON: 356 case PMC_CPU_INTEL_SKYLAKE_XEON: 357 case PMC_CPU_INTEL_SKYLAKE: 358 case PMC_CPU_INTEL_CORE: 359 case PMC_CPU_INTEL_CORE2: 360 case PMC_CPU_INTEL_CORE2EXTREME: 361 case PMC_CPU_INTEL_COREI7: 362 case PMC_CPU_INTEL_NEHALEM_EX: 363 case PMC_CPU_INTEL_HASWELL: 364 case PMC_CPU_INTEL_HASWELL_XEON: 365 case PMC_CPU_INTEL_IVYBRIDGE: 366 case PMC_CPU_INTEL_SANDYBRIDGE: 367 case PMC_CPU_INTEL_WESTMERE: 368 case PMC_CPU_INTEL_WESTMERE_EX: 369 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 370 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 371 pmc_core_finalize(md); 372 break; 373 374 case PMC_CPU_INTEL_PIV: 375 pmc_p4_finalize(md); 376 break; 377 #endif 378 #if defined(__i386__) 379 case PMC_CPU_INTEL_P6: 380 case PMC_CPU_INTEL_CL: 381 case PMC_CPU_INTEL_PII: 382 case PMC_CPU_INTEL_PIII: 383 case PMC_CPU_INTEL_PM: 384 pmc_p6_finalize(md); 385 break; 386 case PMC_CPU_INTEL_P5: 387 pmc_p5_finalize(md); 388 break; 389 #endif 390 default: 391 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 392 } 393 394 /* 395 * Uncore. 396 */ 397 #if defined(__i386__) || defined(__amd64__) 398 switch (md->pmd_cputype) { 399 case PMC_CPU_INTEL_BROADWELL: 400 case PMC_CPU_INTEL_COREI7: 401 case PMC_CPU_INTEL_HASWELL: 402 case PMC_CPU_INTEL_SANDYBRIDGE: 403 case PMC_CPU_INTEL_WESTMERE: 404 pmc_uncore_finalize(md); 405 break; 406 default: 407 break; 408 } 409 #endif 410 } 411