1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Common code for handling Intel CPUs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/pmc.h> 36 #include <sys/pmckern.h> 37 #include <sys/systm.h> 38 39 #include <machine/cpu.h> 40 #include <machine/cputypes.h> 41 #include <machine/md_var.h> 42 #include <machine/specialreg.h> 43 44 static int 45 intel_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 46 { 47 (void) pc; 48 49 PMCDBG(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 50 pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS); 51 52 /* allow the RDPMC instruction if needed */ 53 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 54 load_cr4(rcr4() | CR4_PCE); 55 56 PMCDBG(MDP,SWI,1, "cr4=0x%jx", (uintmax_t) rcr4()); 57 58 return 0; 59 } 60 61 static int 62 intel_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 63 { 64 (void) pc; 65 (void) pp; /* can be NULL */ 66 67 PMCDBG(MDP,SWO,1, "pc=%p pp=%p cr4=0x%jx", pc, pp, 68 (uintmax_t) rcr4()); 69 70 /* always turn off the RDPMC instruction */ 71 load_cr4(rcr4() & ~CR4_PCE); 72 73 return 0; 74 } 75 76 struct pmc_mdep * 77 pmc_intel_initialize(void) 78 { 79 struct pmc_mdep *pmc_mdep; 80 enum pmc_cputype cputype; 81 int error, model, nclasses, ncpus, stepping, verov; 82 83 KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL, 84 ("[intel,%d] Initializing non-intel processor", __LINE__)); 85 86 PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id); 87 88 cputype = -1; 89 nclasses = 2; 90 error = 0; 91 verov = 0; 92 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 93 stepping = cpu_id & 0xF; 94 95 switch (cpu_id & 0xF00) { 96 #if defined(__i386__) 97 case 0x500: /* Pentium family processors */ 98 cputype = PMC_CPU_INTEL_P5; 99 break; 100 #endif 101 case 0x600: /* Pentium Pro, Celeron, Pentium II & III */ 102 switch (model) { 103 #if defined(__i386__) 104 case 0x1: 105 cputype = PMC_CPU_INTEL_P6; 106 break; 107 case 0x3: case 0x5: 108 cputype = PMC_CPU_INTEL_PII; 109 break; 110 case 0x6: case 0x16: 111 cputype = PMC_CPU_INTEL_CL; 112 break; 113 case 0x7: case 0x8: case 0xA: case 0xB: 114 cputype = PMC_CPU_INTEL_PIII; 115 break; 116 case 0x9: case 0xD: 117 cputype = PMC_CPU_INTEL_PM; 118 break; 119 #endif 120 case 0xE: 121 cputype = PMC_CPU_INTEL_CORE; 122 break; 123 case 0xF: 124 /* Per Intel document 315338-020. */ 125 if (stepping == 0x7) { 126 cputype = PMC_CPU_INTEL_CORE; 127 verov = 1; 128 } else { 129 cputype = PMC_CPU_INTEL_CORE2; 130 nclasses = 3; 131 } 132 break; 133 case 0x17: 134 cputype = PMC_CPU_INTEL_CORE2EXTREME; 135 nclasses = 3; 136 break; 137 case 0x1C: /* Per Intel document 320047-002. */ 138 cputype = PMC_CPU_INTEL_ATOM; 139 nclasses = 3; 140 break; 141 case 0x1A: 142 case 0x1E: /* 143 * Per Intel document 253669-032 9/2009, 144 * pages A-2 and A-57 145 */ 146 case 0x1F: /* 147 * Per Intel document 253669-032 9/2009, 148 * pages A-2 and A-57 149 */ 150 cputype = PMC_CPU_INTEL_COREI7; 151 nclasses = 5; 152 break; 153 case 0x2E: 154 cputype = PMC_CPU_INTEL_NEHALEM_EX; 155 nclasses = 3; 156 break; 157 case 0x25: /* Per Intel document 253669-033US 12/2009. */ 158 case 0x2C: /* Per Intel document 253669-033US 12/2009. */ 159 cputype = PMC_CPU_INTEL_WESTMERE; 160 nclasses = 5; 161 break; 162 case 0x2F: /* Westmere-EX, seen in wild */ 163 cputype = PMC_CPU_INTEL_WESTMERE_EX; 164 nclasses = 3; 165 break; 166 case 0x2A: /* Per Intel document 253669-039US 05/2011. */ 167 cputype = PMC_CPU_INTEL_SANDYBRIDGE; 168 nclasses = 5; 169 break; 170 case 0x2D: /* Per Intel document 253669-044US 08/2012. */ 171 cputype = PMC_CPU_INTEL_SANDYBRIDGE_XEON; 172 nclasses = 3; 173 break; 174 case 0x3A: /* Per Intel document 253669-043US 05/2012. */ 175 cputype = PMC_CPU_INTEL_IVYBRIDGE; 176 nclasses = 3; 177 break; 178 case 0x3E: /* Per Intel document 325462-045US 01/2013. */ 179 cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; 180 nclasses = 3; 181 break; 182 case 0x3C: /* Per Intel document 325462-045US 01/2013. */ 183 case 0x45: 184 cputype = PMC_CPU_INTEL_HASWELL; 185 nclasses = 5; 186 break; 187 case 0x4D: /* Per Intel document 330061-001 01/2014. */ 188 cputype = PMC_CPU_INTEL_ATOM_SILVERMONT; 189 nclasses = 3; 190 break; 191 } 192 break; 193 #if defined(__i386__) || defined(__amd64__) 194 case 0xF00: /* P4 */ 195 if (model >= 0 && model <= 6) /* known models */ 196 cputype = PMC_CPU_INTEL_PIV; 197 break; 198 } 199 #endif 200 201 if ((int) cputype == -1) { 202 printf("pmc: Unknown Intel CPU.\n"); 203 return (NULL); 204 } 205 206 /* Allocate base class and initialize machine dependent struct */ 207 pmc_mdep = pmc_mdep_alloc(nclasses); 208 209 pmc_mdep->pmd_cputype = cputype; 210 pmc_mdep->pmd_switch_in = intel_switch_in; 211 pmc_mdep->pmd_switch_out = intel_switch_out; 212 213 ncpus = pmc_cpu_max(); 214 error = pmc_tsc_initialize(pmc_mdep, ncpus); 215 if (error) 216 goto error; 217 switch (cputype) { 218 #if defined(__i386__) || defined(__amd64__) 219 /* 220 * Intel Core, Core 2 and Atom processors. 221 */ 222 case PMC_CPU_INTEL_ATOM: 223 case PMC_CPU_INTEL_ATOM_SILVERMONT: 224 case PMC_CPU_INTEL_CORE: 225 case PMC_CPU_INTEL_CORE2: 226 case PMC_CPU_INTEL_CORE2EXTREME: 227 case PMC_CPU_INTEL_COREI7: 228 case PMC_CPU_INTEL_NEHALEM_EX: 229 case PMC_CPU_INTEL_IVYBRIDGE: 230 case PMC_CPU_INTEL_SANDYBRIDGE: 231 case PMC_CPU_INTEL_WESTMERE: 232 case PMC_CPU_INTEL_WESTMERE_EX: 233 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 234 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 235 case PMC_CPU_INTEL_HASWELL: 236 error = pmc_core_initialize(pmc_mdep, ncpus, verov); 237 break; 238 239 /* 240 * Intel Pentium 4 Processors, and P4/EMT64 processors. 241 */ 242 243 case PMC_CPU_INTEL_PIV: 244 error = pmc_p4_initialize(pmc_mdep, ncpus); 245 break; 246 #endif 247 248 #if defined(__i386__) 249 /* 250 * P6 Family Processors 251 */ 252 253 case PMC_CPU_INTEL_P6: 254 case PMC_CPU_INTEL_CL: 255 case PMC_CPU_INTEL_PII: 256 case PMC_CPU_INTEL_PIII: 257 case PMC_CPU_INTEL_PM: 258 error = pmc_p6_initialize(pmc_mdep, ncpus); 259 break; 260 261 /* 262 * Intel Pentium PMCs. 263 */ 264 265 case PMC_CPU_INTEL_P5: 266 error = pmc_p5_initialize(pmc_mdep, ncpus); 267 break; 268 #endif 269 270 default: 271 KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); 272 } 273 274 if (error) { 275 pmc_tsc_finalize(pmc_mdep); 276 goto error; 277 } 278 279 /* 280 * Init the uncore class. 281 */ 282 #if defined(__i386__) || defined(__amd64__) 283 switch (cputype) { 284 /* 285 * Intel Corei7 and Westmere processors. 286 */ 287 case PMC_CPU_INTEL_COREI7: 288 case PMC_CPU_INTEL_HASWELL: 289 case PMC_CPU_INTEL_SANDYBRIDGE: 290 case PMC_CPU_INTEL_WESTMERE: 291 error = pmc_uncore_initialize(pmc_mdep, ncpus); 292 break; 293 default: 294 break; 295 } 296 #endif 297 error: 298 if (error) { 299 pmc_mdep_free(pmc_mdep); 300 pmc_mdep = NULL; 301 } 302 303 return (pmc_mdep); 304 } 305 306 void 307 pmc_intel_finalize(struct pmc_mdep *md) 308 { 309 pmc_tsc_finalize(md); 310 311 switch (md->pmd_cputype) { 312 #if defined(__i386__) || defined(__amd64__) 313 case PMC_CPU_INTEL_ATOM: 314 case PMC_CPU_INTEL_ATOM_SILVERMONT: 315 case PMC_CPU_INTEL_CORE: 316 case PMC_CPU_INTEL_CORE2: 317 case PMC_CPU_INTEL_CORE2EXTREME: 318 case PMC_CPU_INTEL_COREI7: 319 case PMC_CPU_INTEL_NEHALEM_EX: 320 case PMC_CPU_INTEL_HASWELL: 321 case PMC_CPU_INTEL_IVYBRIDGE: 322 case PMC_CPU_INTEL_SANDYBRIDGE: 323 case PMC_CPU_INTEL_WESTMERE: 324 case PMC_CPU_INTEL_WESTMERE_EX: 325 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 326 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 327 pmc_core_finalize(md); 328 break; 329 330 case PMC_CPU_INTEL_PIV: 331 pmc_p4_finalize(md); 332 break; 333 #endif 334 #if defined(__i386__) 335 case PMC_CPU_INTEL_P6: 336 case PMC_CPU_INTEL_CL: 337 case PMC_CPU_INTEL_PII: 338 case PMC_CPU_INTEL_PIII: 339 case PMC_CPU_INTEL_PM: 340 pmc_p6_finalize(md); 341 break; 342 case PMC_CPU_INTEL_P5: 343 pmc_p5_finalize(md); 344 break; 345 #endif 346 default: 347 KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); 348 } 349 350 /* 351 * Uncore. 352 */ 353 #if defined(__i386__) || defined(__amd64__) 354 switch (md->pmd_cputype) { 355 case PMC_CPU_INTEL_COREI7: 356 case PMC_CPU_INTEL_HASWELL: 357 case PMC_CPU_INTEL_SANDYBRIDGE: 358 case PMC_CPU_INTEL_WESTMERE: 359 pmc_uncore_finalize(md); 360 break; 361 default: 362 break; 363 } 364 #endif 365 } 366