1 /*- 2 * Copyright (c) 2015 Justin Hibbits 3 * Copyright (c) 2005, Joseph Koshy 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/pmc.h> 32 #include <sys/pmckern.h> 33 #include <sys/systm.h> 34 35 #include <machine/pmc_mdep.h> 36 #include <machine/cpu.h> 37 38 #include <ddb/ddb.h> 39 40 #include "hwpmc_powerpc.h" 41 42 struct e500_event_code_map { 43 enum pmc_event pe_ev; /* enum value */ 44 uint8_t pe_counter_mask; /* Which counter this can be counted in. */ 45 uint8_t pe_code; /* numeric code */ 46 uint8_t pe_cpu; /* e500 core (v1,v2,mc), mask */ 47 }; 48 49 #define E500_MAX_PMCS 4 50 #define PMC_PPC_MASK0 0 51 #define PMC_PPC_MASK1 1 52 #define PMC_PPC_MASK2 2 53 #define PMC_PPC_MASK3 3 54 #define PMC_PPC_MASK_ALL 0x0f 55 #define PMC_PPC_E500V1 1 56 #define PMC_PPC_E500V2 2 57 #define PMC_PPC_E500MC 4 58 #define PMC_PPC_E500_ANY 7 59 #define PMC_E500_EVENT(id, mask, number, core) \ 60 [PMC_EV_E500_##id - PMC_EV_E500_FIRST] = \ 61 { .pe_ev = PMC_EV_E500_##id, .pe_counter_mask = mask, \ 62 .pe_code = number, .pe_cpu = core } 63 #define PMC_E500MC_ONLY(id, number) \ 64 PMC_E500_EVENT(id, PMC_PPC_MASK_ALL, number, PMC_PPC_E500MC) 65 #define PMC_E500_COMMON(id, number) \ 66 PMC_E500_EVENT(id, PMC_PPC_MASK_ALL, number, PMC_PPC_E500_ANY) 67 68 static struct e500_event_code_map e500_event_codes[] = { 69 PMC_E500_COMMON(CYCLES, 1), 70 PMC_E500_COMMON(INSTR_COMPLETED, 2), 71 PMC_E500_COMMON(UOPS_COMPLETED, 3), 72 PMC_E500_COMMON(INSTR_FETCHED, 4), 73 PMC_E500_COMMON(UOPS_DECODED, 5), 74 PMC_E500_COMMON(PM_EVENT_TRANSITIONS, 6), 75 PMC_E500_COMMON(PM_EVENT_CYCLES, 7), 76 PMC_E500_COMMON(BRANCH_INSTRS_COMPLETED, 8), 77 PMC_E500_COMMON(LOAD_UOPS_COMPLETED, 9), 78 PMC_E500_COMMON(STORE_UOPS_COMPLETED, 10), 79 PMC_E500_COMMON(CQ_REDIRECTS, 11), 80 PMC_E500_COMMON(BRANCHES_FINISHED, 12), 81 PMC_E500_COMMON(TAKEN_BRANCHES_FINISHED, 13), 82 PMC_E500_COMMON(FINISHED_UNCOND_BRANCHES_MISS_BTB, 14), 83 PMC_E500_COMMON(BRANCH_MISPRED, 15), 84 PMC_E500_COMMON(BTB_BRANCH_MISPRED_FROM_DIRECTION, 16), 85 PMC_E500_COMMON(BTB_HITS_PSEUDO_HITS, 17), 86 PMC_E500_COMMON(CYCLES_DECODE_STALLED, 18), 87 PMC_E500_COMMON(CYCLES_ISSUE_STALLED, 19), 88 PMC_E500_COMMON(CYCLES_BRANCH_ISSUE_STALLED, 20), 89 PMC_E500_COMMON(CYCLES_SU1_SCHED_STALLED, 21), 90 PMC_E500_COMMON(CYCLES_SU2_SCHED_STALLED, 22), 91 PMC_E500_COMMON(CYCLES_MU_SCHED_STALLED, 23), 92 PMC_E500_COMMON(CYCLES_LRU_SCHED_STALLED, 24), 93 PMC_E500_COMMON(CYCLES_BU_SCHED_STALLED, 25), 94 PMC_E500_COMMON(TOTAL_TRANSLATED, 26), 95 PMC_E500_COMMON(LOADS_TRANSLATED, 27), 96 PMC_E500_COMMON(STORES_TRANSLATED, 28), 97 PMC_E500_COMMON(TOUCHES_TRANSLATED, 29), 98 PMC_E500_COMMON(CACHEOPS_TRANSLATED, 30), 99 PMC_E500_COMMON(CACHE_INHIBITED_ACCESS_TRANSLATED, 31), 100 PMC_E500_COMMON(GUARDED_LOADS_TRANSLATED, 32), 101 PMC_E500_COMMON(WRITE_THROUGH_STORES_TRANSLATED, 33), 102 PMC_E500_COMMON(MISALIGNED_LOAD_STORE_ACCESS_TRANSLATED, 34), 103 PMC_E500_COMMON(TOTAL_ALLOCATED_TO_DLFB, 35), 104 PMC_E500_COMMON(LOADS_TRANSLATED_ALLOCATED_TO_DLFB, 36), 105 PMC_E500_COMMON(STORES_COMPLETED_ALLOCATED_TO_DLFB, 37), 106 PMC_E500_COMMON(TOUCHES_TRANSLATED_ALLOCATED_TO_DLFB, 38), 107 PMC_E500_COMMON(STORES_COMPLETED, 39), 108 PMC_E500_COMMON(DATA_L1_CACHE_LOCKS, 40), 109 PMC_E500_COMMON(DATA_L1_CACHE_RELOADS, 41), 110 PMC_E500_COMMON(DATA_L1_CACHE_CASTOUTS, 42), 111 PMC_E500_COMMON(LOAD_MISS_DLFB_FULL, 43), 112 PMC_E500_COMMON(LOAD_MISS_LDQ_FULL, 44), 113 PMC_E500_COMMON(LOAD_GUARDED_MISS, 45), 114 PMC_E500_COMMON(STORE_TRANSLATE_WHEN_QUEUE_FULL, 46), 115 PMC_E500_COMMON(ADDRESS_COLLISION, 47), 116 PMC_E500_COMMON(DATA_MMU_MISS, 48), 117 PMC_E500_COMMON(DATA_MMU_BUSY, 49), 118 PMC_E500_COMMON(PART2_MISALIGNED_CACHE_ACCESS, 50), 119 PMC_E500_COMMON(LOAD_MISS_DLFB_FULL_CYCLES, 51), 120 PMC_E500_COMMON(LOAD_MISS_LDQ_FULL_CYCLES, 52), 121 PMC_E500_COMMON(LOAD_GUARDED_MISS_CYCLES, 53), 122 PMC_E500_COMMON(STORE_TRANSLATE_WHEN_QUEUE_FULL_CYCLES, 54), 123 PMC_E500_COMMON(ADDRESS_COLLISION_CYCLES, 55), 124 PMC_E500_COMMON(DATA_MMU_MISS_CYCLES, 56), 125 PMC_E500_COMMON(DATA_MMU_BUSY_CYCLES, 57), 126 PMC_E500_COMMON(PART2_MISALIGNED_CACHE_ACCESS_CYCLES, 58), 127 PMC_E500_COMMON(INSTR_L1_CACHE_LOCKS, 59), 128 PMC_E500_COMMON(INSTR_L1_CACHE_RELOADS, 60), 129 PMC_E500_COMMON(INSTR_L1_CACHE_FETCHES, 61), 130 PMC_E500_COMMON(INSTR_MMU_TLB4K_RELOADS, 62), 131 PMC_E500_COMMON(INSTR_MMU_VSP_RELOADS, 63), 132 PMC_E500_COMMON(DATA_MMU_TLB4K_RELOADS, 64), 133 PMC_E500_COMMON(DATA_MMU_VSP_RELOADS, 65), 134 PMC_E500_COMMON(L2MMU_MISSES, 66), 135 PMC_E500_COMMON(BIU_MASTER_REQUESTS, 67), 136 PMC_E500_COMMON(BIU_MASTER_INSTR_SIDE_REQUESTS, 68), 137 PMC_E500_COMMON(BIU_MASTER_DATA_SIDE_REQUESTS, 69), 138 PMC_E500_COMMON(BIU_MASTER_DATA_SIDE_CASTOUT_REQUESTS, 70), 139 PMC_E500_COMMON(BIU_MASTER_RETRIES, 71), 140 PMC_E500_COMMON(SNOOP_REQUESTS, 72), 141 PMC_E500_COMMON(SNOOP_HITS, 73), 142 PMC_E500_COMMON(SNOOP_PUSHES, 74), 143 PMC_E500_COMMON(SNOOP_RETRIES, 75), 144 PMC_E500_EVENT(DLFB_LOAD_MISS_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1, 145 76, PMC_PPC_E500_ANY), 146 PMC_E500_EVENT(ILFB_FETCH_MISS_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1, 147 77, PMC_PPC_E500_ANY), 148 PMC_E500_EVENT(EXT_INPU_INTR_LATENCY_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1, 149 78, PMC_PPC_E500_ANY), 150 PMC_E500_EVENT(CRIT_INPUT_INTR_LATENCY_CYCLES, PMC_PPC_MASK0|PMC_PPC_MASK1, 151 79, PMC_PPC_E500_ANY), 152 PMC_E500_EVENT(EXT_INPUT_INTR_PENDING_LATENCY_CYCLES, 153 PMC_PPC_MASK0|PMC_PPC_MASK1, 80, PMC_PPC_E500_ANY), 154 PMC_E500_EVENT(CRIT_INPUT_INTR_PENDING_LATENCY_CYCLES, 155 PMC_PPC_MASK0|PMC_PPC_MASK1, 81, PMC_PPC_E500_ANY), 156 PMC_E500_COMMON(PMC0_OVERFLOW, 82), 157 PMC_E500_COMMON(PMC1_OVERFLOW, 83), 158 PMC_E500_COMMON(PMC2_OVERFLOW, 84), 159 PMC_E500_COMMON(PMC3_OVERFLOW, 85), 160 PMC_E500_COMMON(INTERRUPTS_TAKEN, 86), 161 PMC_E500_COMMON(EXT_INPUT_INTR_TAKEN, 87), 162 PMC_E500_COMMON(CRIT_INPUT_INTR_TAKEN, 88), 163 PMC_E500_COMMON(SYSCALL_TRAP_INTR, 89), 164 PMC_E500_EVENT(TLB_BIT_TRANSITIONS, PMC_PPC_MASK_ALL, 90, 165 PMC_PPC_E500V2 | PMC_PPC_E500MC), 166 PMC_E500MC_ONLY(L2_LINEFILL_BUFFER, 91), 167 PMC_E500MC_ONLY(LV2_VS, 92), 168 PMC_E500MC_ONLY(CASTOUTS_RELEASED, 93), 169 PMC_E500MC_ONLY(INTV_ALLOCATIONS, 94), 170 PMC_E500MC_ONLY(DLFB_RETRIES_TO_MBAR, 95), 171 PMC_E500MC_ONLY(STORE_RETRIES, 96), 172 PMC_E500MC_ONLY(STASH_L1_HITS, 97), 173 PMC_E500MC_ONLY(STASH_L2_HITS, 98), 174 PMC_E500MC_ONLY(STASH_BUSY_1, 99), 175 PMC_E500MC_ONLY(STASH_BUSY_2, 100), 176 PMC_E500MC_ONLY(STASH_BUSY_3, 101), 177 PMC_E500MC_ONLY(STASH_HITS, 102), 178 PMC_E500MC_ONLY(STASH_HIT_DLFB, 103), 179 PMC_E500MC_ONLY(STASH_REQUESTS, 106), 180 PMC_E500MC_ONLY(STASH_REQUESTS_L1, 107), 181 PMC_E500MC_ONLY(STASH_REQUESTS_L2, 108), 182 PMC_E500MC_ONLY(STALLS_NO_CAQ_OR_COB, 109), 183 PMC_E500MC_ONLY(L2_CACHE_ACCESSES, 110), 184 PMC_E500MC_ONLY(L2_HIT_CACHE_ACCESSES, 111), 185 PMC_E500MC_ONLY(L2_CACHE_DATA_ACCESSES, 112), 186 PMC_E500MC_ONLY(L2_CACHE_DATA_HITS, 113), 187 PMC_E500MC_ONLY(L2_CACHE_INSTR_ACCESSES, 114), 188 PMC_E500MC_ONLY(L2_CACHE_INSTR_HITS, 115), 189 PMC_E500MC_ONLY(L2_CACHE_ALLOCATIONS, 116), 190 PMC_E500MC_ONLY(L2_CACHE_DATA_ALLOCATIONS, 117), 191 PMC_E500MC_ONLY(L2_CACHE_DIRTY_DATA_ALLOCATIONS, 118), 192 PMC_E500MC_ONLY(L2_CACHE_INSTR_ALLOCATIONS, 119), 193 PMC_E500MC_ONLY(L2_CACHE_UPDATES, 120), 194 PMC_E500MC_ONLY(L2_CACHE_CLEAN_UPDATES, 121), 195 PMC_E500MC_ONLY(L2_CACHE_DIRTY_UPDATES, 122), 196 PMC_E500MC_ONLY(L2_CACHE_CLEAN_REDUNDANT_UPDATES, 123), 197 PMC_E500MC_ONLY(L2_CACHE_DIRTY_REDUNDANT_UPDATES, 124), 198 PMC_E500MC_ONLY(L2_CACHE_LOCKS, 125), 199 PMC_E500MC_ONLY(L2_CACHE_CASTOUTS, 126), 200 PMC_E500MC_ONLY(L2_CACHE_DATA_DIRTY_HITS, 127), 201 PMC_E500MC_ONLY(INSTR_LFB_WENT_HIGH_PRIORITY, 128), 202 PMC_E500MC_ONLY(SNOOP_THROTTLING_TURNED_ON, 129), 203 PMC_E500MC_ONLY(L2_CLEAN_LINE_INVALIDATIONS, 130), 204 PMC_E500MC_ONLY(L2_INCOHERENT_LINE_INVALIDATIONS, 131), 205 PMC_E500MC_ONLY(L2_COHERENT_LINE_INVALIDATIONS, 132), 206 PMC_E500MC_ONLY(COHERENT_LOOKUP_MISS_DUE_TO_VALID_BUT_INCOHERENT_MATCHES, 133), 207 PMC_E500MC_ONLY(IAC1S_DETECTED, 140), 208 PMC_E500MC_ONLY(IAC2S_DETECTED, 141), 209 PMC_E500MC_ONLY(DAC1S_DTECTED, 144), 210 PMC_E500MC_ONLY(DAC2S_DTECTED, 145), 211 PMC_E500MC_ONLY(DVT0_DETECTED, 148), 212 PMC_E500MC_ONLY(DVT1_DETECTED, 149), 213 PMC_E500MC_ONLY(DVT2_DETECTED, 150), 214 PMC_E500MC_ONLY(DVT3_DETECTED, 151), 215 PMC_E500MC_ONLY(DVT4_DETECTED, 152), 216 PMC_E500MC_ONLY(DVT5_DETECTED, 153), 217 PMC_E500MC_ONLY(DVT6_DETECTED, 154), 218 PMC_E500MC_ONLY(DVT7_DETECTED, 155), 219 PMC_E500MC_ONLY(CYCLES_COMPLETION_STALLED_NEXUS_FIFO_FULL, 156), 220 PMC_E500MC_ONLY(FPU_DOUBLE_PUMP, 160), 221 PMC_E500MC_ONLY(FPU_FINISH, 161), 222 PMC_E500MC_ONLY(FPU_DIVIDE_CYCLES, 162), 223 PMC_E500MC_ONLY(FPU_DENORM_INPUT_CYCLES, 163), 224 PMC_E500MC_ONLY(FPU_RESULT_STALL_CYCLES, 164), 225 PMC_E500MC_ONLY(FPU_FPSCR_FULL_STALL, 165), 226 PMC_E500MC_ONLY(FPU_PIPE_SYNC_STALLS, 166), 227 PMC_E500MC_ONLY(FPU_INPUT_DATA_STALLS, 167), 228 PMC_E500MC_ONLY(DECORATED_LOADS, 176), 229 PMC_E500MC_ONLY(DECORATED_STORES, 177), 230 PMC_E500MC_ONLY(LOAD_RETRIES, 178), 231 PMC_E500MC_ONLY(STWCX_SUCCESSES, 179), 232 PMC_E500MC_ONLY(STWCX_FAILURES, 180), 233 }; 234 235 static pmc_value_t 236 e500_pmcn_read(unsigned int pmc) 237 { 238 switch (pmc) { 239 case 0: 240 return (mfpmr(PMR_PMC0)); 241 case 1: 242 return (mfpmr(PMR_PMC1)); 243 case 2: 244 return (mfpmr(PMR_PMC2)); 245 case 3: 246 return (mfpmr(PMR_PMC3)); 247 default: 248 panic("Invalid PMC number: %d\n", pmc); 249 } 250 } 251 252 static void 253 e500_pmcn_write(unsigned int pmc, uint32_t val) 254 { 255 switch (pmc) { 256 case 0: 257 mtpmr(PMR_PMC0, val); 258 break; 259 case 1: 260 mtpmr(PMR_PMC1, val); 261 break; 262 case 2: 263 mtpmr(PMR_PMC2, val); 264 break; 265 case 3: 266 mtpmr(PMR_PMC3, val); 267 break; 268 default: 269 panic("Invalid PMC number: %d\n", pmc); 270 } 271 } 272 273 static void 274 e500_set_pmc(int cpu, int ri, int config) 275 { 276 struct pmc *pm; 277 struct pmc_hw *phw; 278 register_t pmc_pmlc; 279 280 phw = &powerpc_pcpu[cpu]->pc_ppcpmcs[ri]; 281 pm = phw->phw_pmc; 282 config &= ~POWERPC_PMC_ENABLE; 283 284 if (config != PMCN_NONE) { 285 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 286 config |= PMLCax_CE; 287 288 /* Enable the PMC. */ 289 switch (ri) { 290 case 0: 291 mtpmr(PMR_PMLCa0, config); 292 break; 293 case 1: 294 mtpmr(PMR_PMLCa1, config); 295 break; 296 case 2: 297 mtpmr(PMR_PMLCa2, config); 298 break; 299 case 3: 300 mtpmr(PMR_PMLCa3, config); 301 break; 302 } 303 } else { 304 /* Disable the PMC. */ 305 switch (ri) { 306 case 0: 307 pmc_pmlc = mfpmr(PMR_PMLCa0); 308 pmc_pmlc |= PMLCax_FC; 309 mtpmr(PMR_PMLCa0, pmc_pmlc); 310 break; 311 case 1: 312 pmc_pmlc = mfpmr(PMR_PMLCa1); 313 pmc_pmlc |= PMLCax_FC; 314 mtpmr(PMR_PMLCa1, pmc_pmlc); 315 break; 316 case 2: 317 pmc_pmlc = mfpmr(PMR_PMLCa2); 318 pmc_pmlc |= PMLCax_FC; 319 mtpmr(PMR_PMLCa2, pmc_pmlc); 320 break; 321 case 3: 322 pmc_pmlc = mfpmr(PMR_PMLCa3); 323 pmc_pmlc |= PMLCax_FC; 324 mtpmr(PMR_PMLCa3, pmc_pmlc); 325 break; 326 } 327 } 328 } 329 330 static int 331 e500_pcpu_init(struct pmc_mdep *md, int cpu) 332 { 333 int i; 334 335 powerpc_pcpu_init(md, cpu); 336 337 /* Freeze all counters. */ 338 mtpmr(PMR_PMGC0, PMGC_FAC | PMGC_PMIE | PMGC_FCECE); 339 340 for (i = 0; i < E500_MAX_PMCS; i++) 341 /* Initialize the PMC to stopped */ 342 e500_set_pmc(cpu, i, PMCN_NONE); 343 344 /* Unfreeze global register. */ 345 mtpmr(PMR_PMGC0, PMGC_PMIE | PMGC_FCECE); 346 347 return (0); 348 } 349 350 static int 351 e500_pcpu_fini(struct pmc_mdep *md, int cpu) 352 { 353 uint32_t pmgc0 = mfpmr(PMR_PMGC0); 354 355 pmgc0 |= PMGC_FAC; 356 mtpmr(PMR_PMGC0, pmgc0); 357 mtmsr(mfmsr() & ~PSL_PMM); 358 359 return (powerpc_pcpu_fini(md, cpu)); 360 } 361 362 static int 363 e500_allocate_pmc(int cpu, int ri, struct pmc *pm, 364 const struct pmc_op_pmcallocate *a) 365 { 366 enum pmc_event pe; 367 uint32_t caps, config, counter; 368 struct e500_event_code_map *ev; 369 uint16_t vers; 370 uint8_t pe_cpu_mask; 371 372 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 373 ("[powerpc,%d] illegal CPU value %d", __LINE__, cpu)); 374 KASSERT(ri >= 0 && ri < E500_MAX_PMCS, 375 ("[powerpc,%d] illegal row index %d", __LINE__, ri)); 376 377 if (a->pm_class != PMC_CLASS_E500) 378 return (EINVAL); 379 380 caps = a->pm_caps; 381 382 pe = a->pm_ev; 383 config = PMLCax_FCS | PMLCax_FCU | 384 PMLCax_FCM1 | PMLCax_FCM1; 385 386 if (pe < PMC_EV_E500_FIRST || pe > PMC_EV_E500_LAST) 387 return (EINVAL); 388 389 ev = &e500_event_codes[pe-PMC_EV_E500_FIRST]; 390 if (ev->pe_code == 0) 391 return (EINVAL); 392 393 vers = mfpvr() >> 16; 394 switch (vers) { 395 case FSL_E500v1: 396 pe_cpu_mask = ev->pe_cpu & PMC_PPC_E500V1; 397 break; 398 case FSL_E500v2: 399 pe_cpu_mask = ev->pe_cpu & PMC_PPC_E500V2; 400 break; 401 case FSL_E500mc: 402 case FSL_E5500: 403 pe_cpu_mask = ev->pe_cpu & PMC_PPC_E500MC; 404 break; 405 } 406 if (pe_cpu_mask == 0) 407 return (EINVAL); 408 409 config |= PMLCax_EVENT(ev->pe_code); 410 counter = ev->pe_counter_mask; 411 if ((counter & (1 << ri)) == 0) 412 return (EINVAL); 413 414 if (caps & PMC_CAP_SYSTEM) 415 config &= ~PMLCax_FCS; 416 if (caps & PMC_CAP_USER) 417 config &= ~PMLCax_FCU; 418 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 419 config &= ~(PMLCax_FCS|PMLCax_FCU); 420 421 pm->pm_md.pm_powerpc.pm_powerpc_evsel = config; 422 423 PMCDBG2(MDP,ALL,2,"powerpc-allocate ri=%d -> config=0x%x", ri, config); 424 425 return 0; 426 } 427 428 static void 429 e500_resume_pmc(bool ie) 430 { 431 /* Re-enable PERF exceptions. */ 432 if (ie) 433 mtpmr(PMR_PMGC0, (mfpmr(PMR_PMGC0) & ~PMGC_FAC) | PMGC_PMIE); 434 } 435 436 int 437 pmc_e500_initialize(struct pmc_mdep *pmc_mdep) 438 { 439 struct pmc_classdep *pcd; 440 441 pmc_mdep->pmd_cputype = PMC_CPU_PPC_E500; 442 443 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC]; 444 pcd->pcd_caps = POWERPC_PMC_CAPS; 445 pcd->pcd_class = PMC_CLASS_E500; 446 pcd->pcd_num = E500_MAX_PMCS; 447 pcd->pcd_ri = pmc_mdep->pmd_npmc; 448 pcd->pcd_width = 32; 449 450 pcd->pcd_allocate_pmc = e500_allocate_pmc; 451 pcd->pcd_config_pmc = powerpc_config_pmc; 452 pcd->pcd_pcpu_fini = e500_pcpu_fini; 453 pcd->pcd_pcpu_init = e500_pcpu_init; 454 pcd->pcd_describe = powerpc_describe; 455 pcd->pcd_get_config = powerpc_get_config; 456 pcd->pcd_read_pmc = powerpc_read_pmc; 457 pcd->pcd_release_pmc = powerpc_release_pmc; 458 pcd->pcd_start_pmc = powerpc_start_pmc; 459 pcd->pcd_stop_pmc = powerpc_stop_pmc; 460 pcd->pcd_write_pmc = powerpc_write_pmc; 461 462 pmc_mdep->pmd_npmc += E500_MAX_PMCS; 463 pmc_mdep->pmd_intr = powerpc_pmc_intr; 464 465 ppc_max_pmcs = E500_MAX_PMCS; 466 467 powerpc_set_pmc = e500_set_pmc; 468 powerpc_pmcn_read = e500_pmcn_read; 469 powerpc_pmcn_write = e500_pmcn_write; 470 powerpc_resume_pmc = e500_resume_pmc; 471 472 return (0); 473 } 474