1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _DEV_HWPMC_CORE_H_ 30 #define _DEV_HWPMC_CORE_H_ 1 31 32 /* 33 * Fixed-function PMCs. 34 */ 35 struct pmc_md_iaf_op_pmcallocate { 36 uint16_t pm_iaf_flags; /* additional flags */ 37 }; 38 39 #define IAF_OS 0x1 40 #define IAF_USR 0x2 41 #define IAF_ANY 0x4 42 #define IAF_PMI 0x8 43 44 /* 45 * Programmable PMCs. 46 */ 47 struct pmc_md_iap_op_pmcallocate { 48 uint32_t pm_iap_config; 49 uint64_t pm_iap_rsp; 50 }; 51 52 #define IAP_EVSEL(C) ((C) & 0xFF) 53 #define IAP_UMASK(C) ((C) & 0xFF00) 54 #define IAP_USR (1 << 16) 55 #define IAP_OS (1 << 17) 56 #define IAP_EDGE (1 << 18) 57 #define IAP_INT (1 << 20) 58 #define IAP_ANY (1 << 21) 59 #define IAP_EN (1 << 22) 60 #define IAP_INV (1 << 23) 61 #define IAP_CMASK(C) (((C) & 0xFF) << 24) 62 63 #define IA_OFFCORE_RSP_MASK_I7WM 0x000000F7FF 64 #define IA_OFFCORE_RSP_MASK_SBIB 0x3F807F8FFF 65 66 #ifdef _KERNEL 67 68 /* 69 * Fixed-function counters. 70 */ 71 72 #define IAF_MASK 0xF 73 74 #define IAF_COUNTER_MASK 0x0000ffffffffffff 75 #define IAF_CTR0 0x309 76 #define IAF_CTR1 0x30A 77 #define IAF_CTR2 0x30B 78 79 /* 80 * The IAF_CTRL MSR is laid out in the following way. 81 * 82 * Bit Position Use 83 * 63 - 12 Reserved (do not touch) 84 * 11 Ctr 2 PMI 85 * 10 Reserved (do not touch) 86 * 9-8 Ctr 2 Enable 87 * 7 Ctr 1 PMI 88 * 6 Reserved (do not touch) 89 * 5-4 Ctr 1 Enable 90 * 3 Ctr 0 PMI 91 * 2 Reserved (do not touch) 92 * 1-0 Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable) 93 */ 94 95 #define IAF_OFFSET 32 96 #define IAF_CTRL 0x38D 97 #define IAF_CTRL_MASK 0x0000000000000bbb 98 99 /* 100 * Programmable counters. 101 */ 102 103 #define IAP_PMC0 0x0C1 104 105 /* 106 * IAP_EVSEL(n) is laid out in the following way. 107 * 108 * Bit Position Use 109 * 63-31 Reserved (do not touch) 110 * 31-24 Counter Mask 111 * 23 Invert 112 * 22 Enable 113 * 21 Reserved (do not touch) 114 * 20 APIC Interrupt Enable 115 * 19 Pin Control 116 * 18 Edge Detect 117 * 17 OS 118 * 16 User 119 * 15-8 Unit Mask 120 * 7-0 Event Select 121 */ 122 123 #define IAP_EVSEL_MASK 0x00000000ffdfffff 124 #define IAP_EVSEL0 0x186 125 126 /* 127 * Simplified programming interface in Intel Performance Architecture 128 * v2 and later. 129 */ 130 131 #define IA_GLOBAL_STATUS 0x38E 132 #define IA_GLOBAL_CTRL 0x38F 133 134 /* 135 * IA_GLOBAL_CTRL is layed out in the following way. 136 * 137 * Bit Position Use 138 * 63-35 Reserved (do not touch) 139 * 34 IAF Counter 2 Enable 140 * 33 IAF Counter 1 Enable 141 * 32 IAF Counter 0 Enable 142 * 31-0 Depends on programmable counters 143 */ 144 145 /* The mask is only for the fixed porttion of the register. */ 146 #define IAF_GLOBAL_CTRL_MASK 0x0000000700000000 147 148 /* The mask is only for the programmable porttion of the register. */ 149 #define IAP_GLOBAL_CTRL_MASK 0x00000000ffffffff 150 151 /* The mask is for both the fixed and programmable porttions of the register. */ 152 #define IA_GLOBAL_CTRL_MASK 0x00000007ffffffff 153 154 #define IA_GLOBAL_OVF_CTRL 0x390 155 156 #define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63) 157 #define IA_GLOBAL_STATUS_FLAG_OVFBUF (1ULL << 62) 158 159 /* 160 * Offcore response configuration. 161 */ 162 #define IA_OFFCORE_RSP0 0x1A6 163 #define IA_OFFCORE_RSP1 0x1A7 164 165 struct pmc_md_iaf_pmc { 166 uint64_t pm_iaf_ctrl; 167 }; 168 169 struct pmc_md_iap_pmc { 170 uint32_t pm_iap_evsel; 171 uint64_t pm_iap_rsp; 172 }; 173 174 /* 175 * Prototypes. 176 */ 177 178 int pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu, 179 int _version_override); 180 void pmc_core_finalize(struct pmc_mdep *_md); 181 182 int pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width); 183 void pmc_iaf_finalize(struct pmc_mdep *_md); 184 185 int pmc_iap_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width, 186 int _flags); 187 void pmc_iap_finalize(struct pmc_mdep *_md); 188 189 #endif /* _KERNEL */ 190 #endif /* _DEV_HWPMC_CORE_H */ 191