1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _DEV_HWPMC_CORE_H_ 32 #define _DEV_HWPMC_CORE_H_ 1 33 34 #define IA32_PERF_CAPABILITIES 0x345 35 #define PERFCAP_LBR_FORMAT 0x003f 36 #define PERFCAP_PEBS_TRAP 0x0040 37 #define PERFCAP_PEBS_SAVEARCH 0x0080 38 #define PERFCAP_PEBS_RECFORMAT 0x0f00 39 #define PERFCAP_SMM_FREEZE 0x1000 40 #define PERFCAP_FW_WRITE 0x2000 /* full width write aliases */ 41 42 /* 43 * Fixed-function PMCs. 44 */ 45 struct pmc_md_iaf_op_pmcallocate { 46 uint16_t pm_iaf_flags; /* additional flags */ 47 }; 48 49 #define IAF_OS 0x1 50 #define IAF_USR 0x2 51 #define IAF_ANY 0x4 52 #define IAF_PMI 0x8 53 54 /* 55 * Programmable PMCs. 56 */ 57 struct pmc_md_iap_op_pmcallocate { 58 uint32_t pm_iap_config; 59 uint64_t pm_iap_rsp; 60 }; 61 62 #define IAP_EVSEL(C) ((C) & 0xFF) 63 #define IAP_UMASK(C) (((C) & 0xFF) << 8) 64 #define IAP_USR (1 << 16) 65 #define IAP_OS (1 << 17) 66 #define IAP_EDGE (1 << 18) 67 #define IAP_INT (1 << 20) 68 #define IAP_ANY (1 << 21) 69 #define IAP_EN (1 << 22) 70 #define IAP_INV (1 << 23) 71 #define IAP_CMASK(C) (((C) & 0xFF) << 24) 72 73 #define IAP_EVSEL_GET(C) ((C) & 0xFF) 74 #define IAP_UMASK_GET(C) (((C) & 0xFF00) >> 8) 75 76 #define IA_OFFCORE_RSP_MASK_I7WM 0x000000F7FF 77 #define IA_OFFCORE_RSP_MASK_SBIB 0x3F807F8FFF 78 79 #ifdef _KERNEL 80 81 /* 82 * Fixed-function counters. 83 */ 84 85 #define IAF_MASK 0xF 86 87 #define IAF_COUNTER_MASK 0x0000ffffffffffff 88 #define IAF_CTR0 0x309 89 #define IAF_CTR1 0x30A 90 #define IAF_CTR2 0x30B 91 92 /* 93 * The IAF_CTRL MSR is laid out in the following way. 94 * 95 * Bit Position Use 96 * 63 - 12 Reserved (do not touch) 97 * 11 Ctr 2 PMI 98 * 10 Reserved (do not touch) 99 * 9-8 Ctr 2 Enable 100 * 7 Ctr 1 PMI 101 * 6 Reserved (do not touch) 102 * 5-4 Ctr 1 Enable 103 * 3 Ctr 0 PMI 104 * 2 Reserved (do not touch) 105 * 1-0 Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable) 106 */ 107 108 #define IAF_OFFSET 32 109 #define IAF_CTRL 0x38D 110 #define IAF_CTRL_MASK 0x0000000000000bbb 111 112 /* 113 * Programmable counters. 114 */ 115 116 #define IAP_PMC0 0x0C1 117 #define IAP_A_PMC0 0x4C1 118 119 /* 120 * IAP_EVSEL(n) is laid out in the following way. 121 * 122 * Bit Position Use 123 * 63-31 Reserved (do not touch) 124 * 31-24 Counter Mask 125 * 23 Invert 126 * 22 Enable 127 * 21 Reserved (do not touch) 128 * 20 APIC Interrupt Enable 129 * 19 Pin Control 130 * 18 Edge Detect 131 * 17 OS 132 * 16 User 133 * 15-8 Unit Mask 134 * 7-0 Event Select 135 */ 136 137 #define IAP_EVSEL_MASK 0x00000000ffdfffff 138 #define IAP_EVSEL0 0x186 139 140 /* 141 * Simplified programming interface in Intel Performance Architecture 142 * v2 and later. 143 */ 144 145 #define IA_GLOBAL_STATUS 0x38E 146 #define IA_GLOBAL_CTRL 0x38F 147 148 /* 149 * IA_GLOBAL_CTRL is laid out in the following way. 150 * 151 * Bit Position Use 152 * 63-35 Reserved (do not touch) 153 * 34 IAF Counter 2 Enable 154 * 33 IAF Counter 1 Enable 155 * 32 IAF Counter 0 Enable 156 * 31-0 Depends on programmable counters 157 */ 158 159 /* The mask is only for the fixed porttion of the register. */ 160 #define IAF_GLOBAL_CTRL_MASK 0x0000000700000000 161 162 /* The mask is only for the programmable porttion of the register. */ 163 #define IAP_GLOBAL_CTRL_MASK 0x00000000ffffffff 164 165 /* The mask is for both the fixed and programmable porttions of the register. */ 166 #define IA_GLOBAL_CTRL_MASK 0x00000007ffffffff 167 168 #define IA_GLOBAL_OVF_CTRL 0x390 169 170 #define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63) 171 #define IA_GLOBAL_STATUS_FLAG_OVFBUF (1ULL << 62) 172 173 /* 174 * Offcore response configuration. 175 */ 176 #define IA_OFFCORE_RSP0 0x1A6 177 #define IA_OFFCORE_RSP1 0x1A7 178 179 struct pmc_md_iaf_pmc { 180 uint64_t pm_iaf_ctrl; 181 }; 182 183 struct pmc_md_iap_pmc { 184 uint32_t pm_iap_evsel; 185 uint64_t pm_iap_rsp; 186 }; 187 188 /* 189 * Prototypes. 190 */ 191 192 int pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu, 193 int _version_override); 194 void pmc_core_finalize(struct pmc_mdep *_md); 195 196 int pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width); 197 void pmc_iaf_finalize(struct pmc_mdep *_md); 198 199 int pmc_iap_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width, 200 int _flags); 201 void pmc_iap_finalize(struct pmc_mdep *_md); 202 203 #endif /* _KERNEL */ 204 #endif /* _DEV_HWPMC_CORE_H */ 205