1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _DEV_HWPMC_CORE_H_ 30 #define _DEV_HWPMC_CORE_H_ 1 31 32 #define IA32_PERF_CAPABILITIES 0x345 33 #define PERFCAP_LBR_FORMAT 0x003f 34 #define PERFCAP_PEBS_TRAP 0x0040 35 #define PERFCAP_PEBS_SAVEARCH 0x0080 36 #define PERFCAP_PEBS_RECFORMAT 0x0f00 37 #define PERFCAP_SMM_FREEZE 0x1000 38 #define PERFCAP_FW_WRITE 0x2000 /* full width write aliases */ 39 40 /* 41 * Fixed-function PMCs. 42 */ 43 struct pmc_md_iaf_op_pmcallocate { 44 uint16_t pm_iaf_flags; /* additional flags */ 45 }; 46 47 #define IAF_OS 0x1 48 #define IAF_USR 0x2 49 #define IAF_ANY 0x4 50 #define IAF_PMI 0x8 51 52 /* 53 * Programmable PMCs. 54 */ 55 struct pmc_md_iap_op_pmcallocate { 56 uint32_t pm_iap_config; 57 uint64_t pm_iap_rsp; 58 }; 59 60 #define IAP_EVSEL(C) ((C) & 0xFF) 61 #define IAP_UMASK(C) ((C) & 0xFF00) 62 #define IAP_USR (1 << 16) 63 #define IAP_OS (1 << 17) 64 #define IAP_EDGE (1 << 18) 65 #define IAP_INT (1 << 20) 66 #define IAP_ANY (1 << 21) 67 #define IAP_EN (1 << 22) 68 #define IAP_INV (1 << 23) 69 #define IAP_CMASK(C) (((C) & 0xFF) << 24) 70 71 #define IA_OFFCORE_RSP_MASK_I7WM 0x000000F7FF 72 #define IA_OFFCORE_RSP_MASK_SBIB 0x3F807F8FFF 73 74 #ifdef _KERNEL 75 76 /* 77 * Fixed-function counters. 78 */ 79 80 #define IAF_MASK 0xF 81 82 #define IAF_COUNTER_MASK 0x0000ffffffffffff 83 #define IAF_CTR0 0x309 84 #define IAF_CTR1 0x30A 85 #define IAF_CTR2 0x30B 86 87 /* 88 * The IAF_CTRL MSR is laid out in the following way. 89 * 90 * Bit Position Use 91 * 63 - 12 Reserved (do not touch) 92 * 11 Ctr 2 PMI 93 * 10 Reserved (do not touch) 94 * 9-8 Ctr 2 Enable 95 * 7 Ctr 1 PMI 96 * 6 Reserved (do not touch) 97 * 5-4 Ctr 1 Enable 98 * 3 Ctr 0 PMI 99 * 2 Reserved (do not touch) 100 * 1-0 Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable) 101 */ 102 103 #define IAF_OFFSET 32 104 #define IAF_CTRL 0x38D 105 #define IAF_CTRL_MASK 0x0000000000000bbb 106 107 /* 108 * Programmable counters. 109 */ 110 111 #define IAP_PMC0 0x0C1 112 #define IAP_A_PMC0 0x4C1 113 114 /* 115 * IAP_EVSEL(n) is laid out in the following way. 116 * 117 * Bit Position Use 118 * 63-31 Reserved (do not touch) 119 * 31-24 Counter Mask 120 * 23 Invert 121 * 22 Enable 122 * 21 Reserved (do not touch) 123 * 20 APIC Interrupt Enable 124 * 19 Pin Control 125 * 18 Edge Detect 126 * 17 OS 127 * 16 User 128 * 15-8 Unit Mask 129 * 7-0 Event Select 130 */ 131 132 #define IAP_EVSEL_MASK 0x00000000ffdfffff 133 #define IAP_EVSEL0 0x186 134 135 /* 136 * Simplified programming interface in Intel Performance Architecture 137 * v2 and later. 138 */ 139 140 #define IA_GLOBAL_STATUS 0x38E 141 #define IA_GLOBAL_CTRL 0x38F 142 143 /* 144 * IA_GLOBAL_CTRL is laid out in the following way. 145 * 146 * Bit Position Use 147 * 63-35 Reserved (do not touch) 148 * 34 IAF Counter 2 Enable 149 * 33 IAF Counter 1 Enable 150 * 32 IAF Counter 0 Enable 151 * 31-0 Depends on programmable counters 152 */ 153 154 /* The mask is only for the fixed porttion of the register. */ 155 #define IAF_GLOBAL_CTRL_MASK 0x0000000700000000 156 157 /* The mask is only for the programmable porttion of the register. */ 158 #define IAP_GLOBAL_CTRL_MASK 0x00000000ffffffff 159 160 /* The mask is for both the fixed and programmable porttions of the register. */ 161 #define IA_GLOBAL_CTRL_MASK 0x00000007ffffffff 162 163 #define IA_GLOBAL_OVF_CTRL 0x390 164 165 #define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63) 166 #define IA_GLOBAL_STATUS_FLAG_OVFBUF (1ULL << 62) 167 168 /* 169 * Offcore response configuration. 170 */ 171 #define IA_OFFCORE_RSP0 0x1A6 172 #define IA_OFFCORE_RSP1 0x1A7 173 174 struct pmc_md_iaf_pmc { 175 uint64_t pm_iaf_ctrl; 176 }; 177 178 struct pmc_md_iap_pmc { 179 uint32_t pm_iap_evsel; 180 uint64_t pm_iap_rsp; 181 }; 182 183 /* 184 * Prototypes. 185 */ 186 187 int pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu, 188 int _version_override); 189 void pmc_core_finalize(struct pmc_mdep *_md); 190 191 int pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width); 192 void pmc_iaf_finalize(struct pmc_mdep *_md); 193 194 int pmc_iap_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width, 195 int _flags); 196 void pmc_iap_finalize(struct pmc_mdep *_md); 197 198 #endif /* _KERNEL */ 199 #endif /* _DEV_HWPMC_CORE_H */ 200