1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _DEV_HWPMC_CORE_H_ 30 #define _DEV_HWPMC_CORE_H_ 1 31 32 /* 33 * Fixed-function PMCs. 34 */ 35 struct pmc_md_iaf_op_pmcallocate { 36 uint16_t pm_iaf_flags; /* additional flags */ 37 }; 38 39 #define IAF_OS 0x1 40 #define IAF_USR 0x2 41 #define IAF_ANY 0x4 42 #define IAF_PMI 0x8 43 44 /* 45 * Programmable PMCs. 46 */ 47 struct pmc_md_iap_op_pmcallocate { 48 uint32_t pm_iap_config; 49 uint32_t pm_iap_rsp; 50 }; 51 52 #define IAP_EVSEL(C) ((C) & 0xFF) 53 #define IAP_UMASK(C) ((C) & 0xFF00) 54 #define IAP_USR (1 << 16) 55 #define IAP_OS (1 << 17) 56 #define IAP_EDGE (1 << 18) 57 #define IAP_INT (1 << 20) 58 #define IAP_ANY (1 << 21) 59 #define IAP_EN (1 << 22) 60 #define IAP_INV (1 << 23) 61 #define IAP_CMASK(C) (((C) & 0xFF) << 24) 62 63 #define IA_OFFCORE_RSP_MASK 0xF7FF 64 65 #ifdef _KERNEL 66 67 /* 68 * Fixed-function counters. 69 */ 70 71 #define IAF_MASK 0xF 72 73 #define IAF_COUNTER_MASK 0x0000ffffffffffff 74 #define IAF_CTR0 0x309 75 #define IAF_CTR1 0x30A 76 #define IAF_CTR2 0x30B 77 78 /* 79 * The IAF_CTRL MSR is laid out in the following way. 80 * 81 * Bit Position Use 82 * 63 - 12 Reserved (do not touch) 83 * 11 Ctr 2 PMI 84 * 10 Reserved (do not touch) 85 * 9-8 Ctr 2 Enable 86 * 7 Ctr 1 PMI 87 * 6 Reserved (do not touch) 88 * 5-4 Ctr 1 Enable 89 * 3 Ctr 0 PMI 90 * 2 Reserved (do not touch) 91 * 1-0 Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable) 92 */ 93 94 #define IAF_OFFSET 32 95 #define IAF_CTRL 0x38D 96 #define IAF_CTRL_MASK 0x0000000000000bbb 97 98 /* 99 * Programmable counters. 100 */ 101 102 #define IAP_PMC0 0x0C1 103 104 /* 105 * IAP_EVSEL(n) is laid out in the following way. 106 * 107 * Bit Position Use 108 * 63-31 Reserved (do not touch) 109 * 31-24 Counter Mask 110 * 23 Invert 111 * 22 Enable 112 * 21 Reserved (do not touch) 113 * 20 APIC Interrupt Enable 114 * 19 Pin Control 115 * 18 Edge Detect 116 * 17 OS 117 * 16 User 118 * 15-8 Unit Mask 119 * 7-0 Event Select 120 */ 121 122 #define IAP_EVSEL_MASK 0x00000000ffdfffff 123 #define IAP_EVSEL0 0x186 124 125 /* 126 * Simplified programming interface in Intel Performance Architecture 127 * v2 and later. 128 */ 129 130 #define IA_GLOBAL_STATUS 0x38E 131 #define IA_GLOBAL_CTRL 0x38F 132 133 /* 134 * IA_GLOBAL_CTRL is layed out in the following way. 135 * 136 * Bit Position Use 137 * 63-35 Reserved (do not touch) 138 * 34 IAF Counter 2 Enable 139 * 33 IAF Counter 1 Enable 140 * 32 IAF Counter 0 Enable 141 * 31-0 Depends on programmable counters 142 */ 143 144 /* The mask is only for the fixed porttion of the register. */ 145 #define IAF_GLOBAL_CTRL_MASK 0x0000000700000000 146 147 /* The mask is only for the programmable porttion of the register. */ 148 #define IAP_GLOBAL_CTRL_MASK 0x00000000ffffffff 149 150 /* The mask is for both the fixed and programmable porttions of the register. */ 151 #define IA_GLOBAL_CTRL_MASK 0x00000007ffffffff 152 153 #define IA_GLOBAL_OVF_CTRL 0x390 154 155 #define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63) 156 #define IA_GLOBAL_STATUS_FLAG_OVFBUF (1ULL << 62) 157 158 /* 159 * Offcore response configuration. 160 */ 161 #define IA_OFFCORE_RSP0 0x1A6 162 #define IA_OFFCORE_RSP1 0x1A7 163 164 struct pmc_md_iaf_pmc { 165 uint64_t pm_iaf_ctrl; 166 }; 167 168 struct pmc_md_iap_pmc { 169 uint32_t pm_iap_evsel; 170 uint32_t pm_iap_rsp; 171 }; 172 173 /* 174 * Prototypes. 175 */ 176 177 int pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu); 178 void pmc_core_finalize(struct pmc_mdep *_md); 179 180 void pmc_core_mark_started(int _cpu, int _pmc); 181 182 int pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width); 183 void pmc_iaf_finalize(struct pmc_mdep *_md); 184 185 int pmc_iap_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width, 186 int _flags); 187 void pmc_iap_finalize(struct pmc_mdep *_md); 188 189 #endif /* _KERNEL */ 190 #endif /* _DEV_HWPMC_CORE_H */ 191