1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel Core PMCs. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/pmc.h> 39 #include <sys/pmckern.h> 40 #include <sys/smp.h> 41 #include <sys/systm.h> 42 43 #include <machine/intr_machdep.h> 44 #include <x86/apicvar.h> 45 #include <machine/cpu.h> 46 #include <machine/cpufunc.h> 47 #include <machine/md_var.h> 48 #include <machine/specialreg.h> 49 50 #define CORE_CPUID_REQUEST 0xA 51 #define CORE_CPUID_REQUEST_SIZE 0x4 52 #define CORE_CPUID_EAX 0x0 53 #define CORE_CPUID_EBX 0x1 54 #define CORE_CPUID_ECX 0x2 55 #define CORE_CPUID_EDX 0x3 56 57 #define IAF_PMC_CAPS \ 58 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 59 PMC_CAP_USER | PMC_CAP_SYSTEM) 60 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 61 62 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 63 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 64 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 65 66 #define EV_IS_NOTARCH 0 67 #define EV_IS_ARCH_SUPP 1 68 #define EV_IS_ARCH_NOTSUPP -1 69 70 /* 71 * "Architectural" events defined by Intel. The values of these 72 * symbols correspond to positions in the bitmask returned by 73 * the CPUID.0AH instruction. 74 */ 75 enum core_arch_events { 76 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 77 CORE_AE_BRANCH_MISSES_RETIRED = 6, 78 CORE_AE_INSTRUCTION_RETIRED = 1, 79 CORE_AE_LLC_MISSES = 4, 80 CORE_AE_LLC_REFERENCE = 3, 81 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 82 CORE_AE_UNHALTED_CORE_CYCLES = 0 83 }; 84 85 static enum pmc_cputype core_cputype; 86 87 struct core_cpu { 88 volatile uint32_t pc_resync; 89 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 90 volatile uint64_t pc_globalctrl; /* Global control register. */ 91 struct pmc_hw pc_corepmcs[]; 92 }; 93 94 static struct core_cpu **core_pcpu; 95 96 static uint32_t core_architectural_events; 97 static uint64_t core_pmcmask; 98 99 static int core_iaf_ri; /* relative index of fixed counters */ 100 static int core_iaf_width; 101 static int core_iaf_npmc; 102 103 static int core_iap_width; 104 static int core_iap_npmc; 105 static int core_iap_wroffset; 106 107 static u_int pmc_alloc_refs; 108 static bool pmc_tsx_force_abort_set; 109 110 static int 111 core_pcpu_noop(struct pmc_mdep *md, int cpu) 112 { 113 (void) md; 114 (void) cpu; 115 return (0); 116 } 117 118 static int 119 core_pcpu_init(struct pmc_mdep *md, int cpu) 120 { 121 struct pmc_cpu *pc; 122 struct core_cpu *cc; 123 struct pmc_hw *phw; 124 int core_ri, n, npmc; 125 126 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 127 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 128 129 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu); 130 131 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 132 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 133 134 if (core_cputype != PMC_CPU_INTEL_CORE) 135 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 136 137 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 138 M_PMC, M_WAITOK | M_ZERO); 139 140 core_pcpu[cpu] = cc; 141 pc = pmc_pcpu[cpu]; 142 143 KASSERT(pc != NULL && cc != NULL, 144 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 145 146 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 147 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 148 PMC_PHW_CPU_TO_STATE(cpu) | 149 PMC_PHW_INDEX_TO_STATE(n + core_ri); 150 phw->phw_pmc = NULL; 151 pc->pc_hwpmcs[n + core_ri] = phw; 152 } 153 154 return (0); 155 } 156 157 static int 158 core_pcpu_fini(struct pmc_mdep *md, int cpu) 159 { 160 int core_ri, n, npmc; 161 struct pmc_cpu *pc; 162 struct core_cpu *cc; 163 uint64_t msr = 0; 164 165 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 166 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 167 168 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 169 170 if ((cc = core_pcpu[cpu]) == NULL) 171 return (0); 172 173 core_pcpu[cpu] = NULL; 174 175 pc = pmc_pcpu[cpu]; 176 177 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 178 cpu)); 179 180 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 181 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 182 183 for (n = 0; n < npmc; n++) { 184 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 185 wrmsr(IAP_EVSEL0 + n, msr); 186 } 187 188 if (core_cputype != PMC_CPU_INTEL_CORE) { 189 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 190 wrmsr(IAF_CTRL, msr); 191 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 192 } 193 194 for (n = 0; n < npmc; n++) 195 pc->pc_hwpmcs[n + core_ri] = NULL; 196 197 free(cc, M_PMC); 198 199 return (0); 200 } 201 202 /* 203 * Fixed function counters. 204 */ 205 206 static pmc_value_t 207 iaf_perfctr_value_to_reload_count(pmc_value_t v) 208 { 209 210 /* If the PMC has overflowed, return a reload count of zero. */ 211 if ((v & (1ULL << (core_iaf_width - 1))) == 0) 212 return (0); 213 v &= (1ULL << core_iaf_width) - 1; 214 return (1ULL << core_iaf_width) - v; 215 } 216 217 static pmc_value_t 218 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 219 { 220 return (1ULL << core_iaf_width) - rlc; 221 } 222 223 static int 224 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 225 const struct pmc_op_pmcallocate *a) 226 { 227 uint8_t ev, umask; 228 uint32_t caps, flags, config; 229 const struct pmc_md_iap_op_pmcallocate *iap; 230 231 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 232 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 233 234 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 235 236 if (ri < 0 || ri > core_iaf_npmc) 237 return (EINVAL); 238 239 if (a->pm_class != PMC_CLASS_IAF) 240 return (EINVAL); 241 242 iap = &a->pm_md.pm_iap; 243 config = iap->pm_iap_config; 244 ev = IAP_EVSEL_GET(config); 245 umask = IAP_UMASK_GET(config); 246 247 /* INST_RETIRED.ANY */ 248 if (ev == 0xC0 && ri != 0) 249 return (EINVAL); 250 /* CPU_CLK_UNHALTED.THREAD */ 251 if (ev == 0x3C && ri != 1) 252 return (EINVAL); 253 /* CPU_CLK_UNHALTED.REF */ 254 if (ev == 0x0 && umask == 0x3 && ri != 2) 255 return (EINVAL); 256 257 pmc_alloc_refs++; 258 if ((cpu_stdext_feature3 & CPUID_STDEXT3_TSXFA) != 0 && 259 !pmc_tsx_force_abort_set) { 260 pmc_tsx_force_abort_set = true; 261 x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS_ALL | 262 MSR_OP_WRITE, 1, NULL); 263 } 264 265 flags = 0; 266 if (config & IAP_OS) 267 flags |= IAF_OS; 268 if (config & IAP_USR) 269 flags |= IAF_USR; 270 if (config & IAP_ANY) 271 flags |= IAF_ANY; 272 if (config & IAP_INT) 273 flags |= IAF_PMI; 274 275 caps = a->pm_caps; 276 if (caps & PMC_CAP_INTERRUPT) 277 flags |= IAF_PMI; 278 if (caps & PMC_CAP_SYSTEM) 279 flags |= IAF_OS; 280 if (caps & PMC_CAP_USER) 281 flags |= IAF_USR; 282 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 283 flags |= (IAF_OS | IAF_USR); 284 285 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 286 287 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx", 288 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 289 290 return (0); 291 } 292 293 static int 294 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 295 { 296 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 297 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 298 299 KASSERT(ri >= 0 && ri < core_iaf_npmc, 300 ("[core,%d] illegal row-index %d", __LINE__, ri)); 301 302 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 303 304 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 305 cpu)); 306 307 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 308 309 return (0); 310 } 311 312 static int 313 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 314 { 315 int error; 316 struct pmc_hw *phw; 317 char iaf_name[PMC_NAME_MAX]; 318 319 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 320 321 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 322 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 323 NULL)) != 0) 324 return (error); 325 326 pi->pm_class = PMC_CLASS_IAF; 327 328 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 329 pi->pm_enabled = TRUE; 330 *ppmc = phw->phw_pmc; 331 } else { 332 pi->pm_enabled = FALSE; 333 *ppmc = NULL; 334 } 335 336 return (0); 337 } 338 339 static int 340 iaf_get_config(int cpu, int ri, struct pmc **ppm) 341 { 342 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 343 344 return (0); 345 } 346 347 static int 348 iaf_get_msr(int ri, uint32_t *msr) 349 { 350 KASSERT(ri >= 0 && ri < core_iaf_npmc, 351 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 352 353 *msr = IAF_RI_TO_MSR(ri); 354 355 return (0); 356 } 357 358 static int 359 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 360 { 361 struct pmc *pm; 362 pmc_value_t tmp; 363 364 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 365 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 366 KASSERT(ri >= 0 && ri < core_iaf_npmc, 367 ("[core,%d] illegal row-index %d", __LINE__, ri)); 368 369 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 370 371 KASSERT(pm, 372 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 373 ri, ri + core_iaf_ri)); 374 375 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 376 377 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 378 *v = iaf_perfctr_value_to_reload_count(tmp); 379 else 380 *v = tmp & ((1ULL << core_iaf_width) - 1); 381 382 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 383 IAF_RI_TO_MSR(ri), *v); 384 385 return (0); 386 } 387 388 static int 389 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 390 { 391 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 392 393 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 394 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 395 KASSERT(ri >= 0 && ri < core_iaf_npmc, 396 ("[core,%d] illegal row-index %d", __LINE__, ri)); 397 398 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 399 ("[core,%d] PHW pmc non-NULL", __LINE__)); 400 401 MPASS(pmc_alloc_refs > 0); 402 if (pmc_alloc_refs-- == 1 && pmc_tsx_force_abort_set) { 403 pmc_tsx_force_abort_set = false; 404 x86_msr_op(MSR_TSX_FORCE_ABORT, MSR_OP_RENDEZVOUS_ALL | 405 MSR_OP_WRITE, 0, NULL); 406 } 407 408 return (0); 409 } 410 411 static int 412 iaf_start_pmc(int cpu, int ri) 413 { 414 struct pmc *pm; 415 struct core_cpu *iafc; 416 uint64_t msr = 0; 417 418 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 419 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 420 KASSERT(ri >= 0 && ri < core_iaf_npmc, 421 ("[core,%d] illegal row-index %d", __LINE__, ri)); 422 423 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 424 425 iafc = core_pcpu[cpu]; 426 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 427 428 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 429 430 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 431 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 432 433 do { 434 iafc->pc_resync = 0; 435 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 436 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 437 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 438 IAF_GLOBAL_CTRL_MASK)); 439 } while (iafc->pc_resync != 0); 440 441 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 442 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 443 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 444 445 return (0); 446 } 447 448 static int 449 iaf_stop_pmc(int cpu, int ri) 450 { 451 uint32_t fc; 452 struct core_cpu *iafc; 453 uint64_t msr = 0; 454 455 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 456 457 iafc = core_pcpu[cpu]; 458 459 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 460 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 461 KASSERT(ri >= 0 && ri < core_iaf_npmc, 462 ("[core,%d] illegal row-index %d", __LINE__, ri)); 463 464 fc = (IAF_MASK << (ri * 4)); 465 466 iafc->pc_iafctrl &= ~fc; 467 468 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 469 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 470 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 471 472 do { 473 iafc->pc_resync = 0; 474 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 475 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 476 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 477 IAF_GLOBAL_CTRL_MASK)); 478 } while (iafc->pc_resync != 0); 479 480 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 481 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 482 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 483 484 return (0); 485 } 486 487 static int 488 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 489 { 490 struct core_cpu *cc; 491 struct pmc *pm; 492 uint64_t msr; 493 494 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 495 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 496 KASSERT(ri >= 0 && ri < core_iaf_npmc, 497 ("[core,%d] illegal row-index %d", __LINE__, ri)); 498 499 cc = core_pcpu[cpu]; 500 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 501 502 KASSERT(pm, 503 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 504 505 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 506 v = iaf_reload_count_to_perfctr_value(v); 507 508 /* Turn off fixed counters */ 509 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 510 wrmsr(IAF_CTRL, msr); 511 512 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 513 514 /* Turn on fixed counters */ 515 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 516 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 517 518 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 519 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 520 (uintmax_t) rdmsr(IAF_CTRL), 521 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 522 523 return (0); 524 } 525 526 527 static void 528 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 529 { 530 struct pmc_classdep *pcd; 531 532 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 533 534 PMCDBG0(MDP,INI,1, "iaf-initialize"); 535 536 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 537 538 pcd->pcd_caps = IAF_PMC_CAPS; 539 pcd->pcd_class = PMC_CLASS_IAF; 540 pcd->pcd_num = npmc; 541 pcd->pcd_ri = md->pmd_npmc; 542 pcd->pcd_width = pmcwidth; 543 544 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 545 pcd->pcd_config_pmc = iaf_config_pmc; 546 pcd->pcd_describe = iaf_describe; 547 pcd->pcd_get_config = iaf_get_config; 548 pcd->pcd_get_msr = iaf_get_msr; 549 pcd->pcd_pcpu_fini = core_pcpu_noop; 550 pcd->pcd_pcpu_init = core_pcpu_noop; 551 pcd->pcd_read_pmc = iaf_read_pmc; 552 pcd->pcd_release_pmc = iaf_release_pmc; 553 pcd->pcd_start_pmc = iaf_start_pmc; 554 pcd->pcd_stop_pmc = iaf_stop_pmc; 555 pcd->pcd_write_pmc = iaf_write_pmc; 556 557 md->pmd_npmc += npmc; 558 } 559 560 /* 561 * Intel programmable PMCs. 562 */ 563 564 /* Sub fields of UMASK that this event supports. */ 565 #define IAP_M_CORE (1 << 0) /* Core specificity */ 566 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 567 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 568 #define IAP_M_MESI (1 << 3) /* MESI */ 569 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 570 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 571 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 572 573 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 574 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 575 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 576 #define IAP_F_MESI (0xF << 8) /* MESI */ 577 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 578 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 579 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 580 581 #define IAP_PREFETCH_RESERVED (0x2 << 12) 582 #define IAP_CORE_THIS (0x1 << 14) 583 #define IAP_CORE_ALL (0x3 << 14) 584 #define IAP_F_CMASK 0xFF000000 585 586 static pmc_value_t 587 iap_perfctr_value_to_reload_count(pmc_value_t v) 588 { 589 590 /* If the PMC has overflowed, return a reload count of zero. */ 591 if ((v & (1ULL << (core_iap_width - 1))) == 0) 592 return (0); 593 v &= (1ULL << core_iap_width) - 1; 594 return (1ULL << core_iap_width) - v; 595 } 596 597 static pmc_value_t 598 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 599 { 600 return (1ULL << core_iap_width) - rlc; 601 } 602 603 static int 604 iap_pmc_has_overflowed(int ri) 605 { 606 uint64_t v; 607 608 /* 609 * We treat a Core (i.e., Intel architecture v1) PMC as has 610 * having overflowed if its MSB is zero. 611 */ 612 v = rdpmc(ri); 613 return ((v & (1ULL << (core_iap_width - 1))) == 0); 614 } 615 616 static int 617 iap_event_corei7_ok_on_counter(uint8_t evsel, int ri) 618 { 619 uint32_t mask; 620 621 switch (evsel) { 622 /* 623 * Events valid only on counter 0, 1. 624 */ 625 case 0x40: 626 case 0x41: 627 case 0x42: 628 case 0x43: 629 case 0x51: 630 case 0x63: 631 mask = 0x3; 632 break; 633 634 default: 635 mask = ~0; /* Any row index is ok. */ 636 } 637 638 return (mask & (1 << ri)); 639 } 640 641 static int 642 iap_event_westmere_ok_on_counter(uint8_t evsel, int ri) 643 { 644 uint32_t mask; 645 646 switch (evsel) { 647 /* 648 * Events valid only on counter 0. 649 */ 650 case 0x60: 651 case 0xB3: 652 mask = 0x1; 653 break; 654 655 /* 656 * Events valid only on counter 0, 1. 657 */ 658 case 0x4C: 659 case 0x4E: 660 case 0x51: 661 case 0x63: 662 mask = 0x3; 663 break; 664 665 default: 666 mask = ~0; /* Any row index is ok. */ 667 } 668 669 return (mask & (1 << ri)); 670 } 671 672 static int 673 iap_event_sb_sbx_ib_ibx_ok_on_counter(uint8_t evsel, int ri) 674 { 675 uint32_t mask; 676 677 switch (evsel) { 678 /* Events valid only on counter 0. */ 679 case 0xB7: 680 mask = 0x1; 681 break; 682 /* Events valid only on counter 1. */ 683 case 0xC0: 684 mask = 0x2; 685 break; 686 /* Events valid only on counter 2. */ 687 case 0x48: 688 case 0xA2: 689 case 0xA3: 690 mask = 0x4; 691 break; 692 /* Events valid only on counter 3. */ 693 case 0xBB: 694 case 0xCD: 695 mask = 0x8; 696 break; 697 default: 698 mask = ~0; /* Any row index is ok. */ 699 } 700 701 return (mask & (1 << ri)); 702 } 703 704 static int 705 iap_event_ok_on_counter(uint8_t evsel, int ri) 706 { 707 uint32_t mask; 708 709 switch (evsel) { 710 /* 711 * Events valid only on counter 0. 712 */ 713 case 0x10: 714 case 0x14: 715 case 0x18: 716 case 0xB3: 717 case 0xC1: 718 case 0xCB: 719 mask = (1 << 0); 720 break; 721 722 /* 723 * Events valid only on counter 1. 724 */ 725 case 0x11: 726 case 0x12: 727 case 0x13: 728 mask = (1 << 1); 729 break; 730 731 default: 732 mask = ~0; /* Any row index is ok. */ 733 } 734 735 return (mask & (1 << ri)); 736 } 737 738 static int 739 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 740 const struct pmc_op_pmcallocate *a) 741 { 742 uint8_t ev; 743 const struct pmc_md_iap_op_pmcallocate *iap; 744 745 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 746 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 747 KASSERT(ri >= 0 && ri < core_iap_npmc, 748 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 749 750 if (a->pm_class != PMC_CLASS_IAP) 751 return (EINVAL); 752 753 iap = &a->pm_md.pm_iap; 754 ev = IAP_EVSEL_GET(iap->pm_iap_config); 755 756 switch (core_cputype) { 757 case PMC_CPU_INTEL_COREI7: 758 case PMC_CPU_INTEL_NEHALEM_EX: 759 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 760 return (EINVAL); 761 break; 762 case PMC_CPU_INTEL_SKYLAKE: 763 case PMC_CPU_INTEL_SKYLAKE_XEON: 764 case PMC_CPU_INTEL_ICELAKE: 765 case PMC_CPU_INTEL_ICELAKE_XEON: 766 case PMC_CPU_INTEL_BROADWELL: 767 case PMC_CPU_INTEL_BROADWELL_XEON: 768 case PMC_CPU_INTEL_SANDYBRIDGE: 769 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 770 case PMC_CPU_INTEL_IVYBRIDGE: 771 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 772 case PMC_CPU_INTEL_HASWELL: 773 case PMC_CPU_INTEL_HASWELL_XEON: 774 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 775 return (EINVAL); 776 break; 777 case PMC_CPU_INTEL_WESTMERE: 778 case PMC_CPU_INTEL_WESTMERE_EX: 779 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 780 return (EINVAL); 781 break; 782 default: 783 if (iap_event_ok_on_counter(ev, ri) == 0) 784 return (EINVAL); 785 } 786 787 pm->pm_md.pm_iap.pm_iap_evsel = iap->pm_iap_config; 788 return (0); 789 } 790 791 static int 792 iap_config_pmc(int cpu, int ri, struct pmc *pm) 793 { 794 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 795 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 796 797 KASSERT(ri >= 0 && ri < core_iap_npmc, 798 ("[core,%d] illegal row-index %d", __LINE__, ri)); 799 800 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 801 802 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 803 cpu)); 804 805 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 806 807 return (0); 808 } 809 810 static int 811 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 812 { 813 int error; 814 struct pmc_hw *phw; 815 char iap_name[PMC_NAME_MAX]; 816 817 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 818 819 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 820 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 821 NULL)) != 0) 822 return (error); 823 824 pi->pm_class = PMC_CLASS_IAP; 825 826 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 827 pi->pm_enabled = TRUE; 828 *ppmc = phw->phw_pmc; 829 } else { 830 pi->pm_enabled = FALSE; 831 *ppmc = NULL; 832 } 833 834 return (0); 835 } 836 837 static int 838 iap_get_config(int cpu, int ri, struct pmc **ppm) 839 { 840 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 841 842 return (0); 843 } 844 845 static int 846 iap_get_msr(int ri, uint32_t *msr) 847 { 848 KASSERT(ri >= 0 && ri < core_iap_npmc, 849 ("[iap,%d] ri %d out of range", __LINE__, ri)); 850 851 *msr = ri; 852 853 return (0); 854 } 855 856 static int 857 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 858 { 859 struct pmc *pm; 860 pmc_value_t tmp; 861 862 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 863 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 864 KASSERT(ri >= 0 && ri < core_iap_npmc, 865 ("[core,%d] illegal row-index %d", __LINE__, ri)); 866 867 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 868 869 KASSERT(pm, 870 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 871 ri)); 872 873 tmp = rdpmc(ri); 874 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 875 *v = iap_perfctr_value_to_reload_count(tmp); 876 else 877 *v = tmp & ((1ULL << core_iap_width) - 1); 878 879 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 880 IAP_PMC0 + ri, *v); 881 882 return (0); 883 } 884 885 static int 886 iap_release_pmc(int cpu, int ri, struct pmc *pm) 887 { 888 (void) pm; 889 890 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 891 pm); 892 893 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 894 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 895 KASSERT(ri >= 0 && ri < core_iap_npmc, 896 ("[core,%d] illegal row-index %d", __LINE__, ri)); 897 898 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 899 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 900 901 return (0); 902 } 903 904 static int 905 iap_start_pmc(int cpu, int ri) 906 { 907 struct pmc *pm; 908 uint32_t evsel; 909 struct core_cpu *cc; 910 911 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 912 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 913 KASSERT(ri >= 0 && ri < core_iap_npmc, 914 ("[core,%d] illegal row-index %d", __LINE__, ri)); 915 916 cc = core_pcpu[cpu]; 917 pm = cc->pc_corepmcs[ri].phw_pmc; 918 919 KASSERT(pm, 920 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 921 __LINE__, cpu, ri)); 922 923 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 924 925 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 926 927 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 928 cpu, ri, IAP_EVSEL0 + ri, evsel); 929 930 /* Event specific configuration. */ 931 932 switch (IAP_EVSEL_GET(evsel)) { 933 case 0xB7: 934 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 935 break; 936 case 0xBB: 937 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 938 break; 939 default: 940 break; 941 } 942 943 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 944 945 if (core_cputype == PMC_CPU_INTEL_CORE) 946 return (0); 947 948 do { 949 cc->pc_resync = 0; 950 cc->pc_globalctrl |= (1ULL << ri); 951 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 952 } while (cc->pc_resync != 0); 953 954 return (0); 955 } 956 957 static int 958 iap_stop_pmc(int cpu, int ri) 959 { 960 struct pmc *pm __diagused; 961 struct core_cpu *cc; 962 uint64_t msr; 963 964 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 965 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 966 KASSERT(ri >= 0 && ri < core_iap_npmc, 967 ("[core,%d] illegal row index %d", __LINE__, ri)); 968 969 cc = core_pcpu[cpu]; 970 pm = cc->pc_corepmcs[ri].phw_pmc; 971 972 KASSERT(pm, 973 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 974 cpu, ri)); 975 976 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 977 978 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 979 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 980 981 if (core_cputype == PMC_CPU_INTEL_CORE) 982 return (0); 983 984 do { 985 cc->pc_resync = 0; 986 cc->pc_globalctrl &= ~(1ULL << ri); 987 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 988 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 989 } while (cc->pc_resync != 0); 990 991 return (0); 992 } 993 994 static int 995 iap_write_pmc(int cpu, int ri, pmc_value_t v) 996 { 997 struct pmc *pm; 998 struct core_cpu *cc; 999 1000 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1001 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1002 KASSERT(ri >= 0 && ri < core_iap_npmc, 1003 ("[core,%d] illegal row index %d", __LINE__, ri)); 1004 1005 cc = core_pcpu[cpu]; 1006 pm = cc->pc_corepmcs[ri].phw_pmc; 1007 1008 KASSERT(pm, 1009 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1010 cpu, ri)); 1011 1012 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1013 v = iap_reload_count_to_perfctr_value(v); 1014 1015 v &= (1ULL << core_iap_width) - 1; 1016 1017 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1018 IAP_PMC0 + ri, v); 1019 1020 /* 1021 * Write the new value to the counter (or it's alias). The 1022 * counter will be in a stopped state when the pcd_write() 1023 * entry point is called. 1024 */ 1025 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 1026 return (0); 1027 } 1028 1029 1030 static void 1031 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 1032 int flags) 1033 { 1034 struct pmc_classdep *pcd; 1035 1036 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 1037 1038 PMCDBG0(MDP,INI,1, "iap-initialize"); 1039 1040 /* Remember the set of architectural events supported. */ 1041 core_architectural_events = ~flags; 1042 1043 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 1044 1045 pcd->pcd_caps = IAP_PMC_CAPS; 1046 pcd->pcd_class = PMC_CLASS_IAP; 1047 pcd->pcd_num = npmc; 1048 pcd->pcd_ri = md->pmd_npmc; 1049 pcd->pcd_width = pmcwidth; 1050 1051 pcd->pcd_allocate_pmc = iap_allocate_pmc; 1052 pcd->pcd_config_pmc = iap_config_pmc; 1053 pcd->pcd_describe = iap_describe; 1054 pcd->pcd_get_config = iap_get_config; 1055 pcd->pcd_get_msr = iap_get_msr; 1056 pcd->pcd_pcpu_fini = core_pcpu_fini; 1057 pcd->pcd_pcpu_init = core_pcpu_init; 1058 pcd->pcd_read_pmc = iap_read_pmc; 1059 pcd->pcd_release_pmc = iap_release_pmc; 1060 pcd->pcd_start_pmc = iap_start_pmc; 1061 pcd->pcd_stop_pmc = iap_stop_pmc; 1062 pcd->pcd_write_pmc = iap_write_pmc; 1063 1064 md->pmd_npmc += npmc; 1065 } 1066 1067 static int 1068 core_intr(struct trapframe *tf) 1069 { 1070 pmc_value_t v; 1071 struct pmc *pm; 1072 struct core_cpu *cc; 1073 int error, found_interrupt, ri; 1074 uint64_t msr; 1075 1076 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", curcpu, (void *) tf, 1077 TRAPF_USERMODE(tf)); 1078 1079 found_interrupt = 0; 1080 cc = core_pcpu[curcpu]; 1081 1082 for (ri = 0; ri < core_iap_npmc; ri++) { 1083 1084 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 1085 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1086 continue; 1087 1088 if (!iap_pmc_has_overflowed(ri)) 1089 continue; 1090 1091 found_interrupt = 1; 1092 1093 if (pm->pm_state != PMC_STATE_RUNNING) 1094 continue; 1095 1096 error = pmc_process_interrupt(PMC_HR, pm, tf); 1097 1098 v = pm->pm_sc.pm_reloadcount; 1099 v = iap_reload_count_to_perfctr_value(v); 1100 1101 /* 1102 * Stop the counter, reload it but only restart it if 1103 * the PMC is not stalled. 1104 */ 1105 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 1106 wrmsr(IAP_EVSEL0 + ri, msr); 1107 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 1108 1109 if (error) 1110 continue; 1111 1112 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 1113 IAP_EN)); 1114 } 1115 1116 if (found_interrupt) 1117 lapic_reenable_pmc(); 1118 1119 if (found_interrupt) 1120 counter_u64_add(pmc_stats.pm_intr_processed, 1); 1121 else 1122 counter_u64_add(pmc_stats.pm_intr_ignored, 1); 1123 1124 return (found_interrupt); 1125 } 1126 1127 static int 1128 core2_intr(struct trapframe *tf) 1129 { 1130 int error, found_interrupt, n, cpu; 1131 uint64_t flag, intrstatus, intrenable, msr; 1132 struct pmc *pm; 1133 struct core_cpu *cc; 1134 pmc_value_t v; 1135 1136 cpu = curcpu; 1137 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 1138 TRAPF_USERMODE(tf)); 1139 1140 /* 1141 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 1142 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 1143 * the current set of interrupting PMCs and process these 1144 * after stopping them. 1145 */ 1146 intrstatus = rdmsr(IA_GLOBAL_STATUS); 1147 intrenable = intrstatus & core_pmcmask; 1148 1149 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 1150 (uintmax_t) intrstatus); 1151 1152 found_interrupt = 0; 1153 cc = core_pcpu[cpu]; 1154 1155 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 1156 1157 cc->pc_globalctrl &= ~intrenable; 1158 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 1159 1160 /* 1161 * Stop PMCs and clear overflow status bits. 1162 */ 1163 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 1164 wrmsr(IA_GLOBAL_CTRL, msr); 1165 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 1166 IA_GLOBAL_STATUS_FLAG_OVFBUF | 1167 IA_GLOBAL_STATUS_FLAG_CONDCHG); 1168 1169 /* 1170 * Look for interrupts from fixed function PMCs. 1171 */ 1172 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 1173 n++, flag <<= 1) { 1174 1175 if ((intrstatus & flag) == 0) 1176 continue; 1177 1178 found_interrupt = 1; 1179 1180 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 1181 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 1182 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1183 continue; 1184 1185 error = pmc_process_interrupt(PMC_HR, pm, tf); 1186 1187 if (error) 1188 intrenable &= ~flag; 1189 1190 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 1191 1192 /* Reload sampling count. */ 1193 wrmsr(IAF_CTR0 + n, v); 1194 1195 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", curcpu, 1196 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 1197 } 1198 1199 /* 1200 * Process interrupts from the programmable counters. 1201 */ 1202 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 1203 if ((intrstatus & flag) == 0) 1204 continue; 1205 1206 found_interrupt = 1; 1207 1208 pm = cc->pc_corepmcs[n].phw_pmc; 1209 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 1210 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1211 continue; 1212 1213 error = pmc_process_interrupt(PMC_HR, pm, tf); 1214 if (error) 1215 intrenable &= ~flag; 1216 1217 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 1218 1219 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 1220 (uintmax_t) v); 1221 1222 /* Reload sampling count. */ 1223 wrmsr(core_iap_wroffset + IAP_PMC0 + n, v); 1224 } 1225 1226 /* 1227 * Reenable all non-stalled PMCs. 1228 */ 1229 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 1230 (uintmax_t) intrenable); 1231 1232 cc->pc_globalctrl |= intrenable; 1233 1234 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 1235 1236 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 1237 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 1238 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 1239 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 1240 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 1241 1242 if (found_interrupt) 1243 lapic_reenable_pmc(); 1244 1245 if (found_interrupt) 1246 counter_u64_add(pmc_stats.pm_intr_processed, 1); 1247 else 1248 counter_u64_add(pmc_stats.pm_intr_ignored, 1); 1249 1250 return (found_interrupt); 1251 } 1252 1253 int 1254 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 1255 { 1256 int cpuid[CORE_CPUID_REQUEST_SIZE]; 1257 int ipa_version, flags, nflags; 1258 1259 do_cpuid(CORE_CPUID_REQUEST, cpuid); 1260 1261 ipa_version = (version_override > 0) ? version_override : 1262 cpuid[CORE_CPUID_EAX] & 0xFF; 1263 core_cputype = md->pmd_cputype; 1264 1265 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 1266 core_cputype, maxcpu, ipa_version); 1267 1268 if (ipa_version < 1 || ipa_version > 5 || 1269 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 1270 /* Unknown PMC architecture. */ 1271 printf("hwpc_core: unknown PMC architecture: %d\n", 1272 ipa_version); 1273 return (EPROGMISMATCH); 1274 } 1275 1276 core_iap_wroffset = 0; 1277 if (cpu_feature2 & CPUID2_PDCM) { 1278 if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) { 1279 PMCDBG0(MDP, INI, 1, 1280 "core-init full-width write supported"); 1281 core_iap_wroffset = IAP_A_PMC0 - IAP_PMC0; 1282 } else 1283 PMCDBG0(MDP, INI, 1, 1284 "core-init full-width write NOT supported"); 1285 } else 1286 PMCDBG0(MDP, INI, 1, "core-init pdcm not supported"); 1287 1288 core_pmcmask = 0; 1289 1290 /* 1291 * Initialize programmable counters. 1292 */ 1293 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 1294 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 1295 1296 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 1297 1298 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 1299 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 1300 1301 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 1302 1303 /* 1304 * Initialize fixed function counters, if present. 1305 */ 1306 if (core_cputype != PMC_CPU_INTEL_CORE) { 1307 core_iaf_ri = core_iap_npmc; 1308 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 1309 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 1310 1311 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 1312 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 1313 } 1314 1315 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 1316 core_iaf_ri); 1317 1318 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 1319 M_ZERO | M_WAITOK); 1320 1321 /* 1322 * Choose the appropriate interrupt handler. 1323 */ 1324 if (ipa_version == 1) 1325 md->pmd_intr = core_intr; 1326 else 1327 md->pmd_intr = core2_intr; 1328 1329 md->pmd_pcpu_fini = NULL; 1330 md->pmd_pcpu_init = NULL; 1331 1332 return (0); 1333 } 1334 1335 void 1336 pmc_core_finalize(struct pmc_mdep *md) 1337 { 1338 PMCDBG0(MDP,INI,1, "core-finalize"); 1339 1340 free(core_pcpu, M_PMC); 1341 core_pcpu = NULL; 1342 } 1343