1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Intel Core PMCs. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/pmc.h> 39 #include <sys/pmckern.h> 40 #include <sys/systm.h> 41 42 #include <machine/intr_machdep.h> 43 #if (__FreeBSD_version >= 1100000) 44 #include <x86/apicvar.h> 45 #else 46 #include <machine/apicvar.h> 47 #endif 48 #include <machine/cpu.h> 49 #include <machine/cpufunc.h> 50 #include <machine/md_var.h> 51 #include <machine/specialreg.h> 52 53 #define CORE_CPUID_REQUEST 0xA 54 #define CORE_CPUID_REQUEST_SIZE 0x4 55 #define CORE_CPUID_EAX 0x0 56 #define CORE_CPUID_EBX 0x1 57 #define CORE_CPUID_ECX 0x2 58 #define CORE_CPUID_EDX 0x3 59 60 #define IAF_PMC_CAPS \ 61 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 62 PMC_CAP_USER | PMC_CAP_SYSTEM) 63 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 64 65 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 66 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 67 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 68 69 #define EV_IS_NOTARCH 0 70 #define EV_IS_ARCH_SUPP 1 71 #define EV_IS_ARCH_NOTSUPP -1 72 73 /* 74 * "Architectural" events defined by Intel. The values of these 75 * symbols correspond to positions in the bitmask returned by 76 * the CPUID.0AH instruction. 77 */ 78 enum core_arch_events { 79 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 80 CORE_AE_BRANCH_MISSES_RETIRED = 6, 81 CORE_AE_INSTRUCTION_RETIRED = 1, 82 CORE_AE_LLC_MISSES = 4, 83 CORE_AE_LLC_REFERENCE = 3, 84 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 85 CORE_AE_UNHALTED_CORE_CYCLES = 0 86 }; 87 88 static enum pmc_cputype core_cputype; 89 90 struct core_cpu { 91 volatile uint32_t pc_resync; 92 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 93 volatile uint64_t pc_globalctrl; /* Global control register. */ 94 struct pmc_hw pc_corepmcs[]; 95 }; 96 97 static struct core_cpu **core_pcpu; 98 99 static uint32_t core_architectural_events; 100 static uint64_t core_pmcmask; 101 102 static int core_iaf_ri; /* relative index of fixed counters */ 103 static int core_iaf_width; 104 static int core_iaf_npmc; 105 106 static int core_iap_width; 107 static int core_iap_npmc; 108 static int core_iap_wroffset; 109 110 static int 111 core_pcpu_noop(struct pmc_mdep *md, int cpu) 112 { 113 (void) md; 114 (void) cpu; 115 return (0); 116 } 117 118 static int 119 core_pcpu_init(struct pmc_mdep *md, int cpu) 120 { 121 struct pmc_cpu *pc; 122 struct core_cpu *cc; 123 struct pmc_hw *phw; 124 int core_ri, n, npmc; 125 126 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 127 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 128 129 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu); 130 131 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 132 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 133 134 if (core_cputype != PMC_CPU_INTEL_CORE) 135 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 136 137 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 138 M_PMC, M_WAITOK | M_ZERO); 139 140 core_pcpu[cpu] = cc; 141 pc = pmc_pcpu[cpu]; 142 143 KASSERT(pc != NULL && cc != NULL, 144 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 145 146 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 147 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 148 PMC_PHW_CPU_TO_STATE(cpu) | 149 PMC_PHW_INDEX_TO_STATE(n + core_ri); 150 phw->phw_pmc = NULL; 151 pc->pc_hwpmcs[n + core_ri] = phw; 152 } 153 154 return (0); 155 } 156 157 static int 158 core_pcpu_fini(struct pmc_mdep *md, int cpu) 159 { 160 int core_ri, n, npmc; 161 struct pmc_cpu *pc; 162 struct core_cpu *cc; 163 uint64_t msr = 0; 164 165 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 166 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 167 168 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 169 170 if ((cc = core_pcpu[cpu]) == NULL) 171 return (0); 172 173 core_pcpu[cpu] = NULL; 174 175 pc = pmc_pcpu[cpu]; 176 177 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 178 cpu)); 179 180 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 181 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 182 183 for (n = 0; n < npmc; n++) { 184 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 185 wrmsr(IAP_EVSEL0 + n, msr); 186 } 187 188 if (core_cputype != PMC_CPU_INTEL_CORE) { 189 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 190 wrmsr(IAF_CTRL, msr); 191 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 192 } 193 194 for (n = 0; n < npmc; n++) 195 pc->pc_hwpmcs[n + core_ri] = NULL; 196 197 free(cc, M_PMC); 198 199 return (0); 200 } 201 202 /* 203 * Fixed function counters. 204 */ 205 206 static pmc_value_t 207 iaf_perfctr_value_to_reload_count(pmc_value_t v) 208 { 209 210 /* If the PMC has overflowed, return a reload count of zero. */ 211 if ((v & (1ULL << (core_iaf_width - 1))) == 0) 212 return (0); 213 v &= (1ULL << core_iaf_width) - 1; 214 return (1ULL << core_iaf_width) - v; 215 } 216 217 static pmc_value_t 218 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 219 { 220 return (1ULL << core_iaf_width) - rlc; 221 } 222 223 static int 224 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 225 const struct pmc_op_pmcallocate *a) 226 { 227 enum pmc_event ev; 228 uint32_t caps, flags, validflags; 229 230 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 231 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 232 233 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 234 235 if (ri < 0 || ri > core_iaf_npmc) 236 return (EINVAL); 237 238 caps = a->pm_caps; 239 240 if (a->pm_class != PMC_CLASS_IAF || 241 (caps & IAF_PMC_CAPS) != caps) 242 return (EINVAL); 243 244 ev = pm->pm_event; 245 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 246 return (EINVAL); 247 248 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 249 return (EINVAL); 250 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 251 return (EINVAL); 252 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 253 return (EINVAL); 254 255 flags = a->pm_md.pm_iaf.pm_iaf_flags; 256 257 validflags = IAF_MASK; 258 259 if (core_cputype != PMC_CPU_INTEL_ATOM && 260 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 261 validflags &= ~IAF_ANY; 262 263 if ((flags & ~validflags) != 0) 264 return (EINVAL); 265 266 if (caps & PMC_CAP_INTERRUPT) 267 flags |= IAF_PMI; 268 if (caps & PMC_CAP_SYSTEM) 269 flags |= IAF_OS; 270 if (caps & PMC_CAP_USER) 271 flags |= IAF_USR; 272 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 273 flags |= (IAF_OS | IAF_USR); 274 275 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 276 277 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx", 278 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 279 280 return (0); 281 } 282 283 static int 284 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 285 { 286 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 287 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 288 289 KASSERT(ri >= 0 && ri < core_iaf_npmc, 290 ("[core,%d] illegal row-index %d", __LINE__, ri)); 291 292 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 293 294 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 295 cpu)); 296 297 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 298 299 return (0); 300 } 301 302 static int 303 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 304 { 305 int error; 306 struct pmc_hw *phw; 307 char iaf_name[PMC_NAME_MAX]; 308 309 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 310 311 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 312 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 313 NULL)) != 0) 314 return (error); 315 316 pi->pm_class = PMC_CLASS_IAF; 317 318 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 319 pi->pm_enabled = TRUE; 320 *ppmc = phw->phw_pmc; 321 } else { 322 pi->pm_enabled = FALSE; 323 *ppmc = NULL; 324 } 325 326 return (0); 327 } 328 329 static int 330 iaf_get_config(int cpu, int ri, struct pmc **ppm) 331 { 332 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 333 334 return (0); 335 } 336 337 static int 338 iaf_get_msr(int ri, uint32_t *msr) 339 { 340 KASSERT(ri >= 0 && ri < core_iaf_npmc, 341 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 342 343 *msr = IAF_RI_TO_MSR(ri); 344 345 return (0); 346 } 347 348 static int 349 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 350 { 351 struct pmc *pm; 352 pmc_value_t tmp; 353 354 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 355 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 356 KASSERT(ri >= 0 && ri < core_iaf_npmc, 357 ("[core,%d] illegal row-index %d", __LINE__, ri)); 358 359 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 360 361 KASSERT(pm, 362 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 363 ri, ri + core_iaf_ri)); 364 365 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 366 367 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 368 *v = iaf_perfctr_value_to_reload_count(tmp); 369 else 370 *v = tmp & ((1ULL << core_iaf_width) - 1); 371 372 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 373 IAF_RI_TO_MSR(ri), *v); 374 375 return (0); 376 } 377 378 static int 379 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 380 { 381 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 382 383 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 384 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 385 KASSERT(ri >= 0 && ri < core_iaf_npmc, 386 ("[core,%d] illegal row-index %d", __LINE__, ri)); 387 388 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 389 ("[core,%d] PHW pmc non-NULL", __LINE__)); 390 391 return (0); 392 } 393 394 static int 395 iaf_start_pmc(int cpu, int ri) 396 { 397 struct pmc *pm; 398 struct core_cpu *iafc; 399 uint64_t msr = 0; 400 401 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 402 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 403 KASSERT(ri >= 0 && ri < core_iaf_npmc, 404 ("[core,%d] illegal row-index %d", __LINE__, ri)); 405 406 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 407 408 iafc = core_pcpu[cpu]; 409 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 410 411 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 412 413 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 414 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 415 416 do { 417 iafc->pc_resync = 0; 418 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 419 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 420 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 421 IAF_GLOBAL_CTRL_MASK)); 422 } while (iafc->pc_resync != 0); 423 424 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 425 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 426 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 427 428 return (0); 429 } 430 431 static int 432 iaf_stop_pmc(int cpu, int ri) 433 { 434 uint32_t fc; 435 struct core_cpu *iafc; 436 uint64_t msr = 0; 437 438 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 439 440 iafc = core_pcpu[cpu]; 441 442 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 443 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 444 KASSERT(ri >= 0 && ri < core_iaf_npmc, 445 ("[core,%d] illegal row-index %d", __LINE__, ri)); 446 447 fc = (IAF_MASK << (ri * 4)); 448 449 if (core_cputype != PMC_CPU_INTEL_ATOM && 450 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 451 fc &= ~IAF_ANY; 452 453 iafc->pc_iafctrl &= ~fc; 454 455 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 456 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 457 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 458 459 do { 460 iafc->pc_resync = 0; 461 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 462 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 463 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 464 IAF_GLOBAL_CTRL_MASK)); 465 } while (iafc->pc_resync != 0); 466 467 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 468 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 469 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 470 471 return (0); 472 } 473 474 static int 475 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 476 { 477 struct core_cpu *cc; 478 struct pmc *pm; 479 uint64_t msr; 480 481 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 482 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 483 KASSERT(ri >= 0 && ri < core_iaf_npmc, 484 ("[core,%d] illegal row-index %d", __LINE__, ri)); 485 486 cc = core_pcpu[cpu]; 487 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 488 489 KASSERT(pm, 490 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 491 492 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 493 v = iaf_reload_count_to_perfctr_value(v); 494 495 /* Turn off fixed counters */ 496 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 497 wrmsr(IAF_CTRL, msr); 498 499 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 500 501 /* Turn on fixed counters */ 502 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 503 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 504 505 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 506 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 507 (uintmax_t) rdmsr(IAF_CTRL), 508 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 509 510 return (0); 511 } 512 513 514 static void 515 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 516 { 517 struct pmc_classdep *pcd; 518 519 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 520 521 PMCDBG0(MDP,INI,1, "iaf-initialize"); 522 523 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 524 525 pcd->pcd_caps = IAF_PMC_CAPS; 526 pcd->pcd_class = PMC_CLASS_IAF; 527 pcd->pcd_num = npmc; 528 pcd->pcd_ri = md->pmd_npmc; 529 pcd->pcd_width = pmcwidth; 530 531 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 532 pcd->pcd_config_pmc = iaf_config_pmc; 533 pcd->pcd_describe = iaf_describe; 534 pcd->pcd_get_config = iaf_get_config; 535 pcd->pcd_get_msr = iaf_get_msr; 536 pcd->pcd_pcpu_fini = core_pcpu_noop; 537 pcd->pcd_pcpu_init = core_pcpu_noop; 538 pcd->pcd_read_pmc = iaf_read_pmc; 539 pcd->pcd_release_pmc = iaf_release_pmc; 540 pcd->pcd_start_pmc = iaf_start_pmc; 541 pcd->pcd_stop_pmc = iaf_stop_pmc; 542 pcd->pcd_write_pmc = iaf_write_pmc; 543 544 md->pmd_npmc += npmc; 545 } 546 547 /* 548 * Intel programmable PMCs. 549 */ 550 551 /* Sub fields of UMASK that this event supports. */ 552 #define IAP_M_CORE (1 << 0) /* Core specificity */ 553 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 554 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 555 #define IAP_M_MESI (1 << 3) /* MESI */ 556 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 557 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 558 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 559 560 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 561 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 562 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 563 #define IAP_F_MESI (0xF << 8) /* MESI */ 564 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 565 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 566 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 567 568 #define IAP_PREFETCH_RESERVED (0x2 << 12) 569 #define IAP_CORE_THIS (0x1 << 14) 570 #define IAP_CORE_ALL (0x3 << 14) 571 #define IAP_F_CMASK 0xFF000000 572 573 static pmc_value_t 574 iap_perfctr_value_to_reload_count(pmc_value_t v) 575 { 576 577 /* If the PMC has overflowed, return a reload count of zero. */ 578 if ((v & (1ULL << (core_iap_width - 1))) == 0) 579 return (0); 580 v &= (1ULL << core_iap_width) - 1; 581 return (1ULL << core_iap_width) - v; 582 } 583 584 static pmc_value_t 585 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 586 { 587 return (1ULL << core_iap_width) - rlc; 588 } 589 590 static int 591 iap_pmc_has_overflowed(int ri) 592 { 593 uint64_t v; 594 595 /* 596 * We treat a Core (i.e., Intel architecture v1) PMC as has 597 * having overflowed if its MSB is zero. 598 */ 599 v = rdpmc(ri); 600 return ((v & (1ULL << (core_iap_width - 1))) == 0); 601 } 602 603 static int 604 iap_event_corei7_ok_on_counter(uint8_t evsel, int ri) 605 { 606 uint32_t mask; 607 608 switch (evsel) { 609 /* 610 * Events valid only on counter 0, 1. 611 */ 612 case 0x40: 613 case 0x41: 614 case 0x42: 615 case 0x43: 616 case 0x51: 617 case 0x63: 618 mask = 0x3; 619 break; 620 621 default: 622 mask = ~0; /* Any row index is ok. */ 623 } 624 625 return (mask & (1 << ri)); 626 } 627 628 static int 629 iap_event_westmere_ok_on_counter(uint8_t evsel, int ri) 630 { 631 uint32_t mask; 632 633 switch (evsel) { 634 /* 635 * Events valid only on counter 0. 636 */ 637 case 0x60: 638 case 0xB3: 639 mask = 0x1; 640 break; 641 642 /* 643 * Events valid only on counter 0, 1. 644 */ 645 case 0x4C: 646 case 0x4E: 647 case 0x51: 648 case 0x63: 649 mask = 0x3; 650 break; 651 652 default: 653 mask = ~0; /* Any row index is ok. */ 654 } 655 656 return (mask & (1 << ri)); 657 } 658 659 static int 660 iap_event_sb_sbx_ib_ibx_ok_on_counter(uint8_t evsel, int ri) 661 { 662 uint32_t mask; 663 664 switch (evsel) { 665 /* Events valid only on counter 0. */ 666 case 0xB7: 667 mask = 0x1; 668 break; 669 /* Events valid only on counter 1. */ 670 case 0xC0: 671 mask = 0x2; 672 break; 673 /* Events valid only on counter 2. */ 674 case 0x48: 675 case 0xA2: 676 case 0xA3: 677 mask = 0x4; 678 break; 679 /* Events valid only on counter 3. */ 680 case 0xBB: 681 case 0xCD: 682 mask = 0x8; 683 break; 684 default: 685 mask = ~0; /* Any row index is ok. */ 686 } 687 688 return (mask & (1 << ri)); 689 } 690 691 static int 692 iap_event_ok_on_counter(uint8_t evsel, int ri) 693 { 694 uint32_t mask; 695 696 switch (evsel) { 697 /* 698 * Events valid only on counter 0. 699 */ 700 case 0x10: 701 case 0x14: 702 case 0x18: 703 case 0xB3: 704 case 0xC1: 705 case 0xCB: 706 mask = (1 << 0); 707 break; 708 709 /* 710 * Events valid only on counter 1. 711 */ 712 case 0x11: 713 case 0x12: 714 case 0x13: 715 mask = (1 << 1); 716 break; 717 718 default: 719 mask = ~0; /* Any row index is ok. */ 720 } 721 722 return (mask & (1 << ri)); 723 } 724 725 static int 726 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 727 const struct pmc_op_pmcallocate *a) 728 { 729 enum pmc_event map; 730 uint8_t ev; 731 uint32_t caps; 732 const struct pmc_md_iap_op_pmcallocate *iap; 733 734 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 735 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 736 KASSERT(ri >= 0 && ri < core_iap_npmc, 737 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 738 739 /* check requested capabilities */ 740 caps = a->pm_caps; 741 if ((IAP_PMC_CAPS & caps) != caps) 742 return (EPERM); 743 map = 0; /* XXX: silent GCC warning */ 744 iap = &a->pm_md.pm_iap; 745 ev = IAP_EVSEL_GET(iap->pm_iap_config); 746 747 switch (core_cputype) { 748 case PMC_CPU_INTEL_COREI7: 749 case PMC_CPU_INTEL_NEHALEM_EX: 750 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 751 return (EINVAL); 752 break; 753 case PMC_CPU_INTEL_SKYLAKE: 754 case PMC_CPU_INTEL_SKYLAKE_XEON: 755 case PMC_CPU_INTEL_BROADWELL: 756 case PMC_CPU_INTEL_BROADWELL_XEON: 757 case PMC_CPU_INTEL_SANDYBRIDGE: 758 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 759 case PMC_CPU_INTEL_IVYBRIDGE: 760 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 761 case PMC_CPU_INTEL_HASWELL: 762 case PMC_CPU_INTEL_HASWELL_XEON: 763 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 764 return (EINVAL); 765 break; 766 case PMC_CPU_INTEL_WESTMERE: 767 case PMC_CPU_INTEL_WESTMERE_EX: 768 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 769 return (EINVAL); 770 break; 771 default: 772 if (iap_event_ok_on_counter(ev, ri) == 0) 773 return (EINVAL); 774 } 775 776 pm->pm_md.pm_iap.pm_iap_evsel = iap->pm_iap_config; 777 return (0); 778 } 779 780 static int 781 iap_config_pmc(int cpu, int ri, struct pmc *pm) 782 { 783 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 784 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 785 786 KASSERT(ri >= 0 && ri < core_iap_npmc, 787 ("[core,%d] illegal row-index %d", __LINE__, ri)); 788 789 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 790 791 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 792 cpu)); 793 794 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 795 796 return (0); 797 } 798 799 static int 800 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 801 { 802 int error; 803 struct pmc_hw *phw; 804 char iap_name[PMC_NAME_MAX]; 805 806 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 807 808 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 809 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 810 NULL)) != 0) 811 return (error); 812 813 pi->pm_class = PMC_CLASS_IAP; 814 815 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 816 pi->pm_enabled = TRUE; 817 *ppmc = phw->phw_pmc; 818 } else { 819 pi->pm_enabled = FALSE; 820 *ppmc = NULL; 821 } 822 823 return (0); 824 } 825 826 static int 827 iap_get_config(int cpu, int ri, struct pmc **ppm) 828 { 829 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 830 831 return (0); 832 } 833 834 static int 835 iap_get_msr(int ri, uint32_t *msr) 836 { 837 KASSERT(ri >= 0 && ri < core_iap_npmc, 838 ("[iap,%d] ri %d out of range", __LINE__, ri)); 839 840 *msr = ri; 841 842 return (0); 843 } 844 845 static int 846 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 847 { 848 struct pmc *pm; 849 pmc_value_t tmp; 850 851 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 852 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 853 KASSERT(ri >= 0 && ri < core_iap_npmc, 854 ("[core,%d] illegal row-index %d", __LINE__, ri)); 855 856 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 857 858 KASSERT(pm, 859 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 860 ri)); 861 862 tmp = rdpmc(ri); 863 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 864 *v = iap_perfctr_value_to_reload_count(tmp); 865 else 866 *v = tmp & ((1ULL << core_iap_width) - 1); 867 868 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 869 IAP_PMC0 + ri, *v); 870 871 return (0); 872 } 873 874 static int 875 iap_release_pmc(int cpu, int ri, struct pmc *pm) 876 { 877 (void) pm; 878 879 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 880 pm); 881 882 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 883 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 884 KASSERT(ri >= 0 && ri < core_iap_npmc, 885 ("[core,%d] illegal row-index %d", __LINE__, ri)); 886 887 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 888 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 889 890 return (0); 891 } 892 893 static int 894 iap_start_pmc(int cpu, int ri) 895 { 896 struct pmc *pm; 897 uint32_t evsel; 898 struct core_cpu *cc; 899 900 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 901 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 902 KASSERT(ri >= 0 && ri < core_iap_npmc, 903 ("[core,%d] illegal row-index %d", __LINE__, ri)); 904 905 cc = core_pcpu[cpu]; 906 pm = cc->pc_corepmcs[ri].phw_pmc; 907 908 KASSERT(pm, 909 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 910 __LINE__, cpu, ri)); 911 912 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 913 914 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 915 916 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 917 cpu, ri, IAP_EVSEL0 + ri, evsel); 918 919 /* Event specific configuration. */ 920 921 switch (IAP_EVSEL_GET(evsel)) { 922 case 0xB7: 923 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 924 break; 925 case 0xBB: 926 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 927 break; 928 default: 929 break; 930 } 931 932 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 933 934 if (core_cputype == PMC_CPU_INTEL_CORE) 935 return (0); 936 937 do { 938 cc->pc_resync = 0; 939 cc->pc_globalctrl |= (1ULL << ri); 940 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 941 } while (cc->pc_resync != 0); 942 943 return (0); 944 } 945 946 static int 947 iap_stop_pmc(int cpu, int ri) 948 { 949 struct pmc *pm; 950 struct core_cpu *cc; 951 uint64_t msr; 952 953 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 954 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 955 KASSERT(ri >= 0 && ri < core_iap_npmc, 956 ("[core,%d] illegal row index %d", __LINE__, ri)); 957 958 cc = core_pcpu[cpu]; 959 pm = cc->pc_corepmcs[ri].phw_pmc; 960 961 KASSERT(pm, 962 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 963 cpu, ri)); 964 965 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 966 967 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 968 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 969 970 if (core_cputype == PMC_CPU_INTEL_CORE) 971 return (0); 972 973 msr = 0; 974 do { 975 cc->pc_resync = 0; 976 cc->pc_globalctrl &= ~(1ULL << ri); 977 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 978 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 979 } while (cc->pc_resync != 0); 980 981 return (0); 982 } 983 984 static int 985 iap_write_pmc(int cpu, int ri, pmc_value_t v) 986 { 987 struct pmc *pm; 988 struct core_cpu *cc; 989 990 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 991 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 992 KASSERT(ri >= 0 && ri < core_iap_npmc, 993 ("[core,%d] illegal row index %d", __LINE__, ri)); 994 995 cc = core_pcpu[cpu]; 996 pm = cc->pc_corepmcs[ri].phw_pmc; 997 998 KASSERT(pm, 999 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1000 cpu, ri)); 1001 1002 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1003 v = iap_reload_count_to_perfctr_value(v); 1004 1005 v &= (1ULL << core_iap_width) - 1; 1006 1007 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1008 IAP_PMC0 + ri, v); 1009 1010 /* 1011 * Write the new value to the counter (or it's alias). The 1012 * counter will be in a stopped state when the pcd_write() 1013 * entry point is called. 1014 */ 1015 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 1016 return (0); 1017 } 1018 1019 1020 static void 1021 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 1022 int flags) 1023 { 1024 struct pmc_classdep *pcd; 1025 1026 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 1027 1028 PMCDBG0(MDP,INI,1, "iap-initialize"); 1029 1030 /* Remember the set of architectural events supported. */ 1031 core_architectural_events = ~flags; 1032 1033 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 1034 1035 pcd->pcd_caps = IAP_PMC_CAPS; 1036 pcd->pcd_class = PMC_CLASS_IAP; 1037 pcd->pcd_num = npmc; 1038 pcd->pcd_ri = md->pmd_npmc; 1039 pcd->pcd_width = pmcwidth; 1040 1041 pcd->pcd_allocate_pmc = iap_allocate_pmc; 1042 pcd->pcd_config_pmc = iap_config_pmc; 1043 pcd->pcd_describe = iap_describe; 1044 pcd->pcd_get_config = iap_get_config; 1045 pcd->pcd_get_msr = iap_get_msr; 1046 pcd->pcd_pcpu_fini = core_pcpu_fini; 1047 pcd->pcd_pcpu_init = core_pcpu_init; 1048 pcd->pcd_read_pmc = iap_read_pmc; 1049 pcd->pcd_release_pmc = iap_release_pmc; 1050 pcd->pcd_start_pmc = iap_start_pmc; 1051 pcd->pcd_stop_pmc = iap_stop_pmc; 1052 pcd->pcd_write_pmc = iap_write_pmc; 1053 1054 md->pmd_npmc += npmc; 1055 } 1056 1057 static int 1058 core_intr(int cpu, struct trapframe *tf) 1059 { 1060 pmc_value_t v; 1061 struct pmc *pm; 1062 struct core_cpu *cc; 1063 int error, found_interrupt, ri; 1064 uint64_t msr; 1065 1066 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 1067 TRAPF_USERMODE(tf)); 1068 1069 found_interrupt = 0; 1070 cc = core_pcpu[cpu]; 1071 1072 for (ri = 0; ri < core_iap_npmc; ri++) { 1073 1074 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 1075 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1076 continue; 1077 1078 if (!iap_pmc_has_overflowed(ri)) 1079 continue; 1080 1081 found_interrupt = 1; 1082 1083 if (pm->pm_state != PMC_STATE_RUNNING) 1084 continue; 1085 1086 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 1087 TRAPF_USERMODE(tf)); 1088 1089 v = pm->pm_sc.pm_reloadcount; 1090 v = iap_reload_count_to_perfctr_value(v); 1091 1092 /* 1093 * Stop the counter, reload it but only restart it if 1094 * the PMC is not stalled. 1095 */ 1096 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 1097 wrmsr(IAP_EVSEL0 + ri, msr); 1098 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 1099 1100 if (error) 1101 continue; 1102 1103 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 1104 IAP_EN)); 1105 } 1106 1107 if (found_interrupt) 1108 lapic_reenable_pmc(); 1109 1110 if (found_interrupt) 1111 counter_u64_add(pmc_stats.pm_intr_processed, 1); 1112 else 1113 counter_u64_add(pmc_stats.pm_intr_ignored, 1); 1114 1115 return (found_interrupt); 1116 } 1117 1118 static int 1119 core2_intr(int cpu, struct trapframe *tf) 1120 { 1121 int error, found_interrupt, n; 1122 uint64_t flag, intrstatus, intrenable, msr; 1123 struct pmc *pm; 1124 struct core_cpu *cc; 1125 pmc_value_t v; 1126 1127 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 1128 TRAPF_USERMODE(tf)); 1129 1130 /* 1131 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 1132 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 1133 * the current set of interrupting PMCs and process these 1134 * after stopping them. 1135 */ 1136 intrstatus = rdmsr(IA_GLOBAL_STATUS); 1137 intrenable = intrstatus & core_pmcmask; 1138 1139 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 1140 (uintmax_t) intrstatus); 1141 1142 found_interrupt = 0; 1143 cc = core_pcpu[cpu]; 1144 1145 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 1146 1147 cc->pc_globalctrl &= ~intrenable; 1148 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 1149 1150 /* 1151 * Stop PMCs and clear overflow status bits. 1152 */ 1153 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 1154 wrmsr(IA_GLOBAL_CTRL, msr); 1155 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 1156 IA_GLOBAL_STATUS_FLAG_OVFBUF | 1157 IA_GLOBAL_STATUS_FLAG_CONDCHG); 1158 1159 /* 1160 * Look for interrupts from fixed function PMCs. 1161 */ 1162 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 1163 n++, flag <<= 1) { 1164 1165 if ((intrstatus & flag) == 0) 1166 continue; 1167 1168 found_interrupt = 1; 1169 1170 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 1171 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 1172 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1173 continue; 1174 1175 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 1176 TRAPF_USERMODE(tf)); 1177 1178 if (error) 1179 intrenable &= ~flag; 1180 1181 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 1182 1183 /* Reload sampling count. */ 1184 wrmsr(IAF_CTR0 + n, v); 1185 1186 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 1187 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 1188 } 1189 1190 /* 1191 * Process interrupts from the programmable counters. 1192 */ 1193 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 1194 if ((intrstatus & flag) == 0) 1195 continue; 1196 1197 found_interrupt = 1; 1198 1199 pm = cc->pc_corepmcs[n].phw_pmc; 1200 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 1201 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1202 continue; 1203 1204 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 1205 TRAPF_USERMODE(tf)); 1206 if (error) 1207 intrenable &= ~flag; 1208 1209 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 1210 1211 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 1212 (uintmax_t) v); 1213 1214 /* Reload sampling count. */ 1215 wrmsr(core_iap_wroffset + IAP_PMC0 + n, v); 1216 } 1217 1218 /* 1219 * Reenable all non-stalled PMCs. 1220 */ 1221 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 1222 (uintmax_t) intrenable); 1223 1224 cc->pc_globalctrl |= intrenable; 1225 1226 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 1227 1228 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 1229 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 1230 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 1231 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 1232 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 1233 1234 if (found_interrupt) 1235 lapic_reenable_pmc(); 1236 1237 if (found_interrupt) 1238 counter_u64_add(pmc_stats.pm_intr_processed, 1); 1239 else 1240 counter_u64_add(pmc_stats.pm_intr_ignored, 1); 1241 1242 return (found_interrupt); 1243 } 1244 1245 int 1246 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 1247 { 1248 int cpuid[CORE_CPUID_REQUEST_SIZE]; 1249 int ipa_version, flags, nflags; 1250 1251 do_cpuid(CORE_CPUID_REQUEST, cpuid); 1252 1253 ipa_version = (version_override > 0) ? version_override : 1254 cpuid[CORE_CPUID_EAX] & 0xFF; 1255 core_cputype = md->pmd_cputype; 1256 1257 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 1258 core_cputype, maxcpu, ipa_version); 1259 1260 if (ipa_version < 1 || ipa_version > 4 || 1261 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 1262 /* Unknown PMC architecture. */ 1263 printf("hwpc_core: unknown PMC architecture: %d\n", 1264 ipa_version); 1265 return (EPROGMISMATCH); 1266 } 1267 1268 core_iap_wroffset = 0; 1269 if (cpu_feature2 & CPUID2_PDCM) { 1270 if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) { 1271 PMCDBG0(MDP, INI, 1, 1272 "core-init full-width write supported"); 1273 core_iap_wroffset = IAP_A_PMC0 - IAP_PMC0; 1274 } else 1275 PMCDBG0(MDP, INI, 1, 1276 "core-init full-width write NOT supported"); 1277 } else 1278 PMCDBG0(MDP, INI, 1, "core-init pdcm not supported"); 1279 1280 core_pmcmask = 0; 1281 1282 /* 1283 * Initialize programmable counters. 1284 */ 1285 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 1286 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 1287 1288 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 1289 1290 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 1291 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 1292 1293 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 1294 1295 /* 1296 * Initialize fixed function counters, if present. 1297 */ 1298 if (core_cputype != PMC_CPU_INTEL_CORE) { 1299 core_iaf_ri = core_iap_npmc; 1300 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 1301 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 1302 1303 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 1304 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 1305 } 1306 1307 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 1308 core_iaf_ri); 1309 1310 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 1311 M_ZERO | M_WAITOK); 1312 1313 /* 1314 * Choose the appropriate interrupt handler. 1315 */ 1316 if (ipa_version == 1) 1317 md->pmd_intr = core_intr; 1318 else 1319 md->pmd_intr = core2_intr; 1320 1321 md->pmd_pcpu_fini = NULL; 1322 md->pmd_pcpu_init = NULL; 1323 1324 return (0); 1325 } 1326 1327 void 1328 pmc_core_finalize(struct pmc_mdep *md) 1329 { 1330 PMCDBG0(MDP,INI,1, "core-finalize"); 1331 1332 free(core_pcpu, M_PMC); 1333 core_pcpu = NULL; 1334 } 1335