1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #if (__FreeBSD_version >= 1100000) 42 #include <x86/apicvar.h> 43 #else 44 #include <machine/apicvar.h> 45 #endif 46 #include <machine/cpu.h> 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #define CORE_CPUID_REQUEST 0xA 52 #define CORE_CPUID_REQUEST_SIZE 0x4 53 #define CORE_CPUID_EAX 0x0 54 #define CORE_CPUID_EBX 0x1 55 #define CORE_CPUID_ECX 0x2 56 #define CORE_CPUID_EDX 0x3 57 58 #define IAF_PMC_CAPS \ 59 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 60 PMC_CAP_USER | PMC_CAP_SYSTEM) 61 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 62 63 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 64 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 65 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 66 67 #define EV_IS_NOTARCH 0 68 #define EV_IS_ARCH_SUPP 1 69 #define EV_IS_ARCH_NOTSUPP -1 70 71 /* 72 * "Architectural" events defined by Intel. The values of these 73 * symbols correspond to positions in the bitmask returned by 74 * the CPUID.0AH instruction. 75 */ 76 enum core_arch_events { 77 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 78 CORE_AE_BRANCH_MISSES_RETIRED = 6, 79 CORE_AE_INSTRUCTION_RETIRED = 1, 80 CORE_AE_LLC_MISSES = 4, 81 CORE_AE_LLC_REFERENCE = 3, 82 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 83 CORE_AE_UNHALTED_CORE_CYCLES = 0 84 }; 85 86 static enum pmc_cputype core_cputype; 87 88 struct core_cpu { 89 volatile uint32_t pc_resync; 90 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 91 volatile uint64_t pc_globalctrl; /* Global control register. */ 92 struct pmc_hw pc_corepmcs[]; 93 }; 94 95 static struct core_cpu **core_pcpu; 96 97 static uint32_t core_architectural_events; 98 static uint64_t core_pmcmask; 99 100 static int core_iaf_ri; /* relative index of fixed counters */ 101 static int core_iaf_width; 102 static int core_iaf_npmc; 103 104 static int core_iap_width; 105 static int core_iap_npmc; 106 107 static int 108 core_pcpu_noop(struct pmc_mdep *md, int cpu) 109 { 110 (void) md; 111 (void) cpu; 112 return (0); 113 } 114 115 static int 116 core_pcpu_init(struct pmc_mdep *md, int cpu) 117 { 118 struct pmc_cpu *pc; 119 struct core_cpu *cc; 120 struct pmc_hw *phw; 121 int core_ri, n, npmc; 122 123 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 124 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 125 126 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu); 127 128 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 129 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 130 131 if (core_cputype != PMC_CPU_INTEL_CORE) 132 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 133 134 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 135 M_PMC, M_WAITOK | M_ZERO); 136 137 core_pcpu[cpu] = cc; 138 pc = pmc_pcpu[cpu]; 139 140 KASSERT(pc != NULL && cc != NULL, 141 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 142 143 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 144 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 145 PMC_PHW_CPU_TO_STATE(cpu) | 146 PMC_PHW_INDEX_TO_STATE(n + core_ri); 147 phw->phw_pmc = NULL; 148 pc->pc_hwpmcs[n + core_ri] = phw; 149 } 150 151 return (0); 152 } 153 154 static int 155 core_pcpu_fini(struct pmc_mdep *md, int cpu) 156 { 157 int core_ri, n, npmc; 158 struct pmc_cpu *pc; 159 struct core_cpu *cc; 160 uint64_t msr = 0; 161 162 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 163 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 164 165 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 166 167 if ((cc = core_pcpu[cpu]) == NULL) 168 return (0); 169 170 core_pcpu[cpu] = NULL; 171 172 pc = pmc_pcpu[cpu]; 173 174 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 175 cpu)); 176 177 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 178 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 179 180 for (n = 0; n < npmc; n++) { 181 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 182 wrmsr(IAP_EVSEL0 + n, msr); 183 } 184 185 if (core_cputype != PMC_CPU_INTEL_CORE) { 186 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 187 wrmsr(IAF_CTRL, msr); 188 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 189 } 190 191 for (n = 0; n < npmc; n++) 192 pc->pc_hwpmcs[n + core_ri] = NULL; 193 194 free(cc, M_PMC); 195 196 return (0); 197 } 198 199 /* 200 * Fixed function counters. 201 */ 202 203 static pmc_value_t 204 iaf_perfctr_value_to_reload_count(pmc_value_t v) 205 { 206 207 /* If the PMC has overflowed, return a reload count of zero. */ 208 if ((v & (1ULL << (core_iaf_width - 1))) == 0) 209 return (0); 210 v &= (1ULL << core_iaf_width) - 1; 211 return (1ULL << core_iaf_width) - v; 212 } 213 214 static pmc_value_t 215 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 216 { 217 return (1ULL << core_iaf_width) - rlc; 218 } 219 220 static int 221 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 222 const struct pmc_op_pmcallocate *a) 223 { 224 enum pmc_event ev; 225 uint32_t caps, flags, validflags; 226 227 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 228 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 229 230 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 231 232 if (ri < 0 || ri > core_iaf_npmc) 233 return (EINVAL); 234 235 caps = a->pm_caps; 236 237 if (a->pm_class != PMC_CLASS_IAF || 238 (caps & IAF_PMC_CAPS) != caps) 239 return (EINVAL); 240 241 ev = pm->pm_event; 242 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 243 return (EINVAL); 244 245 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 246 return (EINVAL); 247 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 248 return (EINVAL); 249 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 250 return (EINVAL); 251 252 flags = a->pm_md.pm_iaf.pm_iaf_flags; 253 254 validflags = IAF_MASK; 255 256 if (core_cputype != PMC_CPU_INTEL_ATOM && 257 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 258 validflags &= ~IAF_ANY; 259 260 if ((flags & ~validflags) != 0) 261 return (EINVAL); 262 263 if (caps & PMC_CAP_INTERRUPT) 264 flags |= IAF_PMI; 265 if (caps & PMC_CAP_SYSTEM) 266 flags |= IAF_OS; 267 if (caps & PMC_CAP_USER) 268 flags |= IAF_USR; 269 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 270 flags |= (IAF_OS | IAF_USR); 271 272 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 273 274 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx", 275 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 276 277 return (0); 278 } 279 280 static int 281 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 282 { 283 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 284 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 285 286 KASSERT(ri >= 0 && ri < core_iaf_npmc, 287 ("[core,%d] illegal row-index %d", __LINE__, ri)); 288 289 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 290 291 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 292 cpu)); 293 294 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 295 296 return (0); 297 } 298 299 static int 300 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 301 { 302 int error; 303 struct pmc_hw *phw; 304 char iaf_name[PMC_NAME_MAX]; 305 306 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 307 308 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 309 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 310 NULL)) != 0) 311 return (error); 312 313 pi->pm_class = PMC_CLASS_IAF; 314 315 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 316 pi->pm_enabled = TRUE; 317 *ppmc = phw->phw_pmc; 318 } else { 319 pi->pm_enabled = FALSE; 320 *ppmc = NULL; 321 } 322 323 return (0); 324 } 325 326 static int 327 iaf_get_config(int cpu, int ri, struct pmc **ppm) 328 { 329 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 330 331 return (0); 332 } 333 334 static int 335 iaf_get_msr(int ri, uint32_t *msr) 336 { 337 KASSERT(ri >= 0 && ri < core_iaf_npmc, 338 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 339 340 *msr = IAF_RI_TO_MSR(ri); 341 342 return (0); 343 } 344 345 static int 346 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 347 { 348 struct pmc *pm; 349 pmc_value_t tmp; 350 351 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 352 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 353 KASSERT(ri >= 0 && ri < core_iaf_npmc, 354 ("[core,%d] illegal row-index %d", __LINE__, ri)); 355 356 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 357 358 KASSERT(pm, 359 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 360 ri, ri + core_iaf_ri)); 361 362 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 363 364 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 365 *v = iaf_perfctr_value_to_reload_count(tmp); 366 else 367 *v = tmp; 368 369 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 370 IAF_RI_TO_MSR(ri), *v); 371 372 return (0); 373 } 374 375 static int 376 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 377 { 378 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 379 380 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 381 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 382 KASSERT(ri >= 0 && ri < core_iaf_npmc, 383 ("[core,%d] illegal row-index %d", __LINE__, ri)); 384 385 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 386 ("[core,%d] PHW pmc non-NULL", __LINE__)); 387 388 return (0); 389 } 390 391 static int 392 iaf_start_pmc(int cpu, int ri) 393 { 394 struct pmc *pm; 395 struct core_cpu *iafc; 396 uint64_t msr = 0; 397 398 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 399 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 400 KASSERT(ri >= 0 && ri < core_iaf_npmc, 401 ("[core,%d] illegal row-index %d", __LINE__, ri)); 402 403 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 404 405 iafc = core_pcpu[cpu]; 406 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 407 408 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 409 410 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 411 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 412 413 do { 414 iafc->pc_resync = 0; 415 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 416 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 417 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 418 IAF_GLOBAL_CTRL_MASK)); 419 } while (iafc->pc_resync != 0); 420 421 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 422 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 423 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 424 425 return (0); 426 } 427 428 static int 429 iaf_stop_pmc(int cpu, int ri) 430 { 431 uint32_t fc; 432 struct core_cpu *iafc; 433 uint64_t msr = 0; 434 435 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 436 437 iafc = core_pcpu[cpu]; 438 439 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 440 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 441 KASSERT(ri >= 0 && ri < core_iaf_npmc, 442 ("[core,%d] illegal row-index %d", __LINE__, ri)); 443 444 fc = (IAF_MASK << (ri * 4)); 445 446 if (core_cputype != PMC_CPU_INTEL_ATOM && 447 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 448 fc &= ~IAF_ANY; 449 450 iafc->pc_iafctrl &= ~fc; 451 452 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 453 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 454 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 455 456 do { 457 iafc->pc_resync = 0; 458 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 459 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 460 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 461 IAF_GLOBAL_CTRL_MASK)); 462 } while (iafc->pc_resync != 0); 463 464 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 465 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 466 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 467 468 return (0); 469 } 470 471 static int 472 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 473 { 474 struct core_cpu *cc; 475 struct pmc *pm; 476 uint64_t msr; 477 478 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 479 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 480 KASSERT(ri >= 0 && ri < core_iaf_npmc, 481 ("[core,%d] illegal row-index %d", __LINE__, ri)); 482 483 cc = core_pcpu[cpu]; 484 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 485 486 KASSERT(pm, 487 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 488 489 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 490 v = iaf_reload_count_to_perfctr_value(v); 491 492 /* Turn off fixed counters */ 493 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 494 wrmsr(IAF_CTRL, msr); 495 496 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 497 498 /* Turn on fixed counters */ 499 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 500 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 501 502 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 503 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 504 (uintmax_t) rdmsr(IAF_CTRL), 505 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 506 507 return (0); 508 } 509 510 511 static void 512 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 513 { 514 struct pmc_classdep *pcd; 515 516 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 517 518 PMCDBG0(MDP,INI,1, "iaf-initialize"); 519 520 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 521 522 pcd->pcd_caps = IAF_PMC_CAPS; 523 pcd->pcd_class = PMC_CLASS_IAF; 524 pcd->pcd_num = npmc; 525 pcd->pcd_ri = md->pmd_npmc; 526 pcd->pcd_width = pmcwidth; 527 528 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 529 pcd->pcd_config_pmc = iaf_config_pmc; 530 pcd->pcd_describe = iaf_describe; 531 pcd->pcd_get_config = iaf_get_config; 532 pcd->pcd_get_msr = iaf_get_msr; 533 pcd->pcd_pcpu_fini = core_pcpu_noop; 534 pcd->pcd_pcpu_init = core_pcpu_noop; 535 pcd->pcd_read_pmc = iaf_read_pmc; 536 pcd->pcd_release_pmc = iaf_release_pmc; 537 pcd->pcd_start_pmc = iaf_start_pmc; 538 pcd->pcd_stop_pmc = iaf_stop_pmc; 539 pcd->pcd_write_pmc = iaf_write_pmc; 540 541 md->pmd_npmc += npmc; 542 } 543 544 /* 545 * Intel programmable PMCs. 546 */ 547 548 /* 549 * Event descriptor tables. 550 * 551 * For each event id, we track: 552 * 553 * 1. The CPUs that the event is valid for. 554 * 555 * 2. If the event uses a fixed UMASK, the value of the umask field. 556 * If the event doesn't use a fixed UMASK, a mask of legal bits 557 * to check against. 558 */ 559 560 struct iap_event_descr { 561 enum pmc_event iap_ev; 562 unsigned char iap_evcode; 563 unsigned char iap_umask; 564 unsigned int iap_flags; 565 }; 566 567 #define IAP_F_CC (1 << 0) /* CPU: Core */ 568 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 569 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 570 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 571 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 572 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 573 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 574 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 575 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 576 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 577 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ 578 #define IAP_F_HW (1 << 10) /* CPU: Haswell */ 579 #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ 580 #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ 581 #define IAP_F_BW (1 << 13) /* CPU: Broadwell */ 582 #define IAP_F_FM (1 << 14) /* Fixed mask */ 583 584 #define IAP_F_ALLCPUSCORE2 \ 585 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 586 587 /* Sub fields of UMASK that this event supports. */ 588 #define IAP_M_CORE (1 << 0) /* Core specificity */ 589 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 590 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 591 #define IAP_M_MESI (1 << 3) /* MESI */ 592 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 593 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 594 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 595 596 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 597 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 598 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 599 #define IAP_F_MESI (0xF << 8) /* MESI */ 600 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 601 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 602 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 603 604 #define IAP_PREFETCH_RESERVED (0x2 << 12) 605 #define IAP_CORE_THIS (0x1 << 14) 606 #define IAP_CORE_ALL (0x3 << 14) 607 #define IAP_F_CMASK 0xFF000000 608 609 static struct iap_event_descr iap_events[] = { 610 #undef IAPDESCR 611 #define IAPDESCR(N,EV,UM,FLAGS) { \ 612 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 613 .iap_evcode = (EV), \ 614 .iap_umask = (UM), \ 615 .iap_flags = (FLAGS) \ 616 } 617 618 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 619 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 620 621 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 622 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 623 IAP_F_SBX | IAP_F_CAS), 624 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 625 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 626 IAP_F_CAS | IAP_F_HWX), 627 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 628 IAP_F_CAS), 629 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 630 IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 631 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 632 IAP_F_SBX | IAP_F_CAS), 633 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 634 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_CAS), 635 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_CAS), 636 637 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), 638 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 639 IAP_F_CAS), 640 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 641 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_CAS), 642 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 643 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 644 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_CAS), 645 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_CAS), 646 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_CAS), 647 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_CAS), 648 649 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 650 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 651 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 652 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | 653 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 654 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), 655 656 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 657 IAP_F_CC2E | IAP_F_CA), 658 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 659 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 660 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 661 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 662 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 663 664 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 665 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 666 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 667 IAP_F_HW | IAP_F_HWX), 668 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 669 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 670 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 671 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 672 IAP_F_SBX), 673 674 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 675 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 676 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 677 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 678 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 679 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 680 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 681 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 682 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 683 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 684 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 685 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 686 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 687 IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 688 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 689 IAP_F_HWX), 690 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 691 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 692 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 693 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 694 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 695 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 696 IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_IB | IAP_F_IBX), 697 698 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 699 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 700 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 701 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 702 703 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 704 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 705 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 706 707 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 708 IAP_F_WM), 709 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 710 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 711 712 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | 713 IAP_F_IB | IAP_F_IBX | IAP_F_HWX), 714 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 715 716 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 717 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 718 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 719 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 720 IAP_F_HWX), 721 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 722 IAP_F_HWX), 723 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 724 IAP_F_HWX), 725 726 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 727 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 728 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 729 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 730 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 731 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 732 733 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 734 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 735 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ), 736 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 737 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 738 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 739 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 740 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 741 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 742 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 743 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 744 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 745 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 746 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 747 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 748 749 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 750 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 751 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 752 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 753 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 754 755 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 756 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 757 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 758 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 759 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 760 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 761 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 762 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 763 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 764 765 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 766 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 767 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 768 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 769 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 770 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 771 772 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 773 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 774 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 775 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 776 777 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 778 IAP_F_SBX), 779 780 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 781 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 782 783 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 784 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 785 IAP_F_I7 | IAP_F_WM), 786 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 787 788 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 789 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 790 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 791 792 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 793 794 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 795 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 796 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 797 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 798 799 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 800 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 801 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 802 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 803 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 804 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 805 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 806 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 807 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 808 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 809 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 810 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 811 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 812 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 813 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 814 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 815 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 816 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 817 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 818 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 819 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 820 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 821 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 822 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 823 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 824 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 825 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 826 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 827 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 828 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 829 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 830 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 831 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 832 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 833 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 834 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 835 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 836 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 837 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 838 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 839 IAP_F_HWX), 840 841 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 842 843 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 844 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 845 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 846 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 847 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 848 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 849 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 850 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 851 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 852 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 853 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 854 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 855 856 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 857 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 858 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 859 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 860 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 861 IAP_F_SBX), 862 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 863 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 864 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 865 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 866 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 867 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 868 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 869 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 870 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 871 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 872 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 873 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 874 875 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 876 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 877 IAP_F_SBX | IAP_F_IBX), 878 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 879 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 880 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 881 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 882 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 883 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 884 IAP_F_SBX | IAP_F_IBX), 885 886 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 887 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 888 IAP_F_CA | IAP_F_CC2), 889 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 890 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 891 892 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 893 IAP_F_ALLCPUSCORE2), 894 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 895 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 896 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 897 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 898 IAP_F_CAS | IAP_F_HWX), 899 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 900 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 901 IAP_F_CAS | IAP_F_HWX), 902 903 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 904 IAP_F_ALLCPUSCORE2), 905 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_CAS), 906 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_CAS), 907 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 908 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 909 910 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 911 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 912 913 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 914 915 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 916 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 917 IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 918 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 919 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 920 IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 921 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 922 923 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 924 925 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 926 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 927 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 928 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 929 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 930 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 931 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 932 933 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 934 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 935 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 936 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 937 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 938 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 939 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 940 941 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 942 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 943 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 944 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 945 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 946 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 947 948 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 949 IAP_F_I7), 950 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 951 IAP_F_CC2 | IAP_F_I7), 952 953 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 954 955 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 956 957 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 958 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 959 960 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 961 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 962 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 963 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 964 965 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 966 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 967 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 968 IAP_F_HW | IAP_F_HWX), 969 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 970 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 971 IAP_F_HW | IAP_F_HWX), 972 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 973 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 974 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 975 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 976 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 977 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 978 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 979 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 980 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | 981 IAP_F_HWX), 982 983 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 984 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 985 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 986 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 987 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 988 989 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 990 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 991 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 992 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 993 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 994 995 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 996 997 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 998 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 999 IAP_F_SB | IAP_F_SBX), 1000 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1001 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1002 1003 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 1004 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 1005 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 1006 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 1007 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 1008 1009 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1010 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1011 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1012 IAP_F_SB | IAP_F_SBX), 1013 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1014 IAP_F_SB | IAP_F_SBX), 1015 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1016 IAP_F_SB | IAP_F_SBX), 1017 1018 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1019 1020 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1021 1022 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1023 IAP_F_HWX), 1024 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1025 IAP_F_HWX), 1026 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1027 IAP_F_HWX), 1028 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1029 IAP_F_HWX), 1030 1031 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1032 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1033 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1034 1035 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1036 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1037 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1038 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1039 1040 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1041 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1042 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1043 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1044 1045 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1046 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1047 1048 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */ 1049 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX | IAP_F_IB), 1050 1051 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1052 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1053 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1054 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1055 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1056 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1057 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1058 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1059 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1060 1061 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1062 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1063 1064 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1065 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1066 1067 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1068 IAP_F_CA | IAP_F_CC2), 1069 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1070 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1071 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1072 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1073 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1074 1075 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1076 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1077 1078 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1079 IAP_F_CA | IAP_F_CC2), 1080 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1081 1082 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1083 1084 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1085 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1086 1087 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1088 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1089 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1090 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1091 1092 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1093 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1094 1095 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1096 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1097 1098 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1099 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1100 1101 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1102 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1103 1104 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1105 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1106 1107 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1108 IAP_F_CA | IAP_F_CC2), 1109 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1110 1111 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1112 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1113 1114 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1115 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1116 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1117 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1118 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1119 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1120 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1121 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1122 1123 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1124 1125 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1126 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1127 1128 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1129 1130 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1131 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1132 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1133 IAP_F_HWX), 1134 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1135 IAP_F_HWX), 1136 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1137 IAP_F_HWX), 1138 1139 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1140 1141 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1142 1143 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1144 1145 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1146 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1147 1148 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1149 1150 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1151 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1152 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1153 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1154 IAP_F_CAS | IAP_F_HWX), 1155 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1156 IAP_F_WM | IAP_F_CAS), 1157 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_IBX), 1158 1159 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1160 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1161 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1162 1163 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1164 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1165 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1166 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1167 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1168 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1169 1170 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1171 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1172 1173 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1174 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1175 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1176 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1177 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1178 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1179 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1180 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1181 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1182 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1183 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1184 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1185 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1186 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1187 1188 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1189 1190 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1191 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1192 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1193 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1194 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1195 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1196 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1197 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1198 1199 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1200 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1201 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1202 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1203 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1204 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1205 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1206 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1207 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1208 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1209 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1210 IAPDESCR(88H_41H, 0x88, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1211 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1212 IAPDESCR(88H_81H, 0x88, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1213 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1214 IAPDESCR(88H_82H, 0x88, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1215 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1216 IAPDESCR(88H_84H, 0x88, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1217 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1218 IAPDESCR(88H_88H, 0x88, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1219 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1220 IAPDESCR(88H_90H, 0x88, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1221 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1222 IAPDESCR(88H_A0H, 0x88, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1223 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1224 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1225 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1226 1227 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1228 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1229 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1230 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1231 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1232 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1233 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1234 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1235 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1236 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1237 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1238 IAPDESCR(89H_41H, 0x89, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1239 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1240 IAPDESCR(89H_81H, 0x89, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1241 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1242 IAPDESCR(89H_82H, 0x89, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1243 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1244 IAPDESCR(89H_84H, 0x89, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1245 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1246 IAPDESCR(89H_88H, 0x89, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1247 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1248 IAPDESCR(89H_90H, 0x89, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1249 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1250 IAPDESCR(89H_A0H, 0x89, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1251 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1252 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1253 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1254 1255 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1256 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1257 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1258 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1259 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1260 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1261 1262 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1263 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1264 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1265 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1266 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1267 1268 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1269 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1270 1271 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1272 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1273 1274 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1275 1276 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1277 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1278 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1279 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1280 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1281 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1282 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1283 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1284 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1285 IAP_F_SBX | IAP_F_IBX), 1286 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1287 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1288 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1289 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1290 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1291 IAP_F_SBX | IAP_F_IBX), 1292 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1293 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1294 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1295 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1296 1297 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1298 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1299 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1300 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1301 IAP_F_SB | IAP_F_SBX), 1302 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1303 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1304 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1305 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1306 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1307 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1308 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1309 IAP_F_SB | IAP_F_SBX), 1310 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1311 IAP_F_SB | IAP_F_SBX), 1312 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1313 IAP_F_SB | IAP_F_SBX), 1314 1315 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), 1316 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), 1317 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB), 1318 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1319 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | IAP_F_HWX), 1320 IAPDESCR(A3H_0CH, 0xA3, 0x08, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1321 1322 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1323 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1324 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX | 1325 IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 1326 1327 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1328 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1329 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1330 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1331 1332 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1333 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1334 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1335 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1336 1337 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1338 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1339 IAP_F_SBX | IAP_F_IBX), 1340 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1341 1342 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1343 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1344 1345 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1346 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1347 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1348 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1349 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1350 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1351 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1352 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1353 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1354 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1355 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1356 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1357 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1358 1359 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1360 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1361 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1362 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1363 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1364 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1365 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1366 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1367 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1368 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1369 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1370 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1371 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1372 IAP_F_WM), 1373 1374 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1375 IAP_F_SB | IAP_F_SBX), 1376 1377 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1378 IAP_F_WM | IAP_F_I7O), 1379 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1380 IAP_F_WM | IAP_F_I7O), 1381 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1382 IAP_F_WM | IAP_F_I7O), 1383 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1384 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1385 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1386 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1387 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1388 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1389 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1390 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1391 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1392 1393 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1394 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1395 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1396 1397 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1398 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_CAS), 1399 1400 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1401 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | 1402 IAP_F_HWX), 1403 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), 1404 1405 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1406 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1407 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1408 1409 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1410 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1411 1412 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1413 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1414 1415 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1416 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1417 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1418 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1419 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1420 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1421 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1422 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1423 1424 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1425 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1426 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1427 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1428 1429 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1430 1431 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1432 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1433 IAP_F_CAS | IAP_F_HWX), 1434 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1435 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1436 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1437 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1438 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1439 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1440 IAP_F_I7 | IAP_F_WM), 1441 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1442 1443 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1444 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1445 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1446 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1447 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1448 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1449 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1450 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1451 IAP_F_SBX | IAP_F_IBX), 1452 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1453 IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_IB | IAP_F_IBX), 1454 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1455 1456 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1457 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1458 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1459 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1460 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1461 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1462 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1463 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1464 IAP_F_I7 | IAP_F_WM), 1465 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1466 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1467 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1468 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), 1469 1470 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1471 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1472 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1473 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1474 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1475 IAP_F_CAS | IAP_F_HWX), 1476 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1477 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1478 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1479 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_CAS), 1480 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1481 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1482 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1483 1484 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1485 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1486 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1487 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1488 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1489 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1490 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1491 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1492 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1493 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1494 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1495 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1496 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1497 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1498 IAP_F_HWX), 1499 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1500 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1501 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1502 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1503 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1504 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1505 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1506 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1507 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_CAS), 1508 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_CAS), 1509 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_CAS), 1510 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_CAS), 1511 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_CAS), 1512 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_CAS), 1513 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_CAS), 1514 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_CAS), 1515 1516 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1517 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1518 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1519 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1520 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1521 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1522 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1523 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1524 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1525 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1526 IAP_F_SBX | IAP_F_IBX), 1527 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1528 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1529 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_CAS), 1530 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_CAS), 1531 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_CAS), 1532 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_CAS), 1533 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_CAS), 1534 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_CAS), 1535 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_CAS), 1536 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_CAS), 1537 1538 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1539 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1540 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1541 1542 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1543 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1544 IAP_F_I7 | IAP_F_WM), 1545 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1546 IAP_F_I7 | IAP_F_WM), 1547 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1548 IAP_F_I7 | IAP_F_WM), 1549 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1550 IAP_F_I7 | IAP_F_WM), 1551 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1552 IAP_F_I7 | IAP_F_WM), 1553 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1554 1555 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1556 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1557 1558 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1559 1560 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1561 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 1562 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1563 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1564 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1565 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1566 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1567 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1568 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1569 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1570 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1571 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1572 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_CAS), 1573 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_CAS), 1574 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_CAS), 1575 1576 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1577 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1578 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1579 IAP_F_I7 | IAP_F_WM), 1580 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1581 IAP_F_I7 | IAP_F_WM), 1582 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1583 IAP_F_I7 | IAP_F_WM), 1584 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1585 IAP_F_WM), 1586 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_CAS), 1587 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1588 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1589 1590 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1591 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1592 IAP_F_I7 | IAP_F_WM), 1593 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1594 IAP_F_I7 | IAP_F_WM), 1595 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1596 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1597 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1598 1599 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1600 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1601 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1602 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1603 IAP_F_SBX | IAP_F_IBX), 1604 1605 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1606 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1607 1608 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ 1609 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1610 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1611 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1612 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1613 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1614 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1615 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1616 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1617 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1618 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1619 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1620 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1621 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1622 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1623 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1624 1625 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1626 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1627 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1628 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1629 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1630 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1631 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1632 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1633 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX), 1634 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1635 IAP_F_HW | IAP_F_HWX), 1636 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1637 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1638 1639 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1640 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1641 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1642 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1643 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1644 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1645 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1646 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1647 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1648 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1649 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1650 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1651 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1652 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1653 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1654 1655 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1656 1657 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1658 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1659 IAPDESCR(D3H_03H, 0xD3, 0x03, IAP_F_IBX), 1660 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), /* Not defined for IBX */ 1661 IAPDESCR(D3H_0CH, 0xD3, 0x0C, IAP_F_IBX), 1662 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX ), 1663 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX ), 1664 1665 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1666 IAP_F_I7 | IAP_F_WM), 1667 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1668 IAP_F_SB | IAP_F_SBX), 1669 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1670 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1671 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1672 1673 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1674 IAP_F_I7 | IAP_F_WM), 1675 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1676 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1677 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1678 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1679 1680 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1681 1682 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1683 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1684 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1685 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1686 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1687 1688 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1689 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1690 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1691 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1692 1693 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1694 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1695 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1696 1697 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1698 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1699 1700 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1701 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1702 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1703 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1704 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1705 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1706 1707 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1708 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1709 IAP_F_WM), 1710 1711 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1712 1713 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1714 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1715 1716 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1717 1718 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1719 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1720 IAP_F_WM | IAP_F_SBX | IAP_F_CAS), 1721 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1722 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_CAS), 1723 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_CAS), 1724 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB | 1725 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1726 1727 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_CAS), 1728 1729 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1730 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1731 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1732 1733 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1734 1735 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1736 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1737 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1738 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1739 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1740 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1741 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1742 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1743 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1744 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1745 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1746 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1747 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1748 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1749 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1750 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1751 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1752 1753 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1754 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1755 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1756 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1757 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1758 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1759 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1760 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1761 1762 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1763 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1764 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1765 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1766 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1767 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1768 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1769 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1770 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1771 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1772 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1773 IAP_F_IBX), 1774 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1775 1776 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1777 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1778 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1779 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1780 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1781 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1782 1783 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1784 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1785 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1786 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1787 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1788 IAP_F_SB | IAP_F_SBX), 1789 1790 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1791 1792 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1793 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1794 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1795 1796 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1797 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1798 1799 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1800 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1801 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1802 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1803 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1804 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1805 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1806 }; 1807 1808 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1809 1810 static pmc_value_t 1811 iap_perfctr_value_to_reload_count(pmc_value_t v) 1812 { 1813 1814 /* If the PMC has overflowed, return a reload count of zero. */ 1815 if ((v & (1ULL << (core_iap_width - 1))) == 0) 1816 return (0); 1817 v &= (1ULL << core_iap_width) - 1; 1818 return (1ULL << core_iap_width) - v; 1819 } 1820 1821 static pmc_value_t 1822 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1823 { 1824 return (1ULL << core_iap_width) - rlc; 1825 } 1826 1827 static int 1828 iap_pmc_has_overflowed(int ri) 1829 { 1830 uint64_t v; 1831 1832 /* 1833 * We treat a Core (i.e., Intel architecture v1) PMC as has 1834 * having overflowed if its MSB is zero. 1835 */ 1836 v = rdpmc(ri); 1837 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1838 } 1839 1840 /* 1841 * Check an event against the set of supported architectural events. 1842 * 1843 * If the event is not architectural EV_IS_NOTARCH is returned. 1844 * If the event is architectural and supported on this CPU, the correct 1845 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. 1846 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. 1847 */ 1848 1849 static int 1850 iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) 1851 { 1852 enum core_arch_events ae; 1853 1854 switch (pe) { 1855 case PMC_EV_IAP_ARCH_UNH_COR_CYC: 1856 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1857 *map = PMC_EV_IAP_EVENT_3CH_00H; 1858 break; 1859 case PMC_EV_IAP_ARCH_INS_RET: 1860 ae = CORE_AE_INSTRUCTION_RETIRED; 1861 *map = PMC_EV_IAP_EVENT_C0H_00H; 1862 break; 1863 case PMC_EV_IAP_ARCH_UNH_REF_CYC: 1864 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1865 *map = PMC_EV_IAP_EVENT_3CH_01H; 1866 break; 1867 case PMC_EV_IAP_ARCH_LLC_REF: 1868 ae = CORE_AE_LLC_REFERENCE; 1869 *map = PMC_EV_IAP_EVENT_2EH_4FH; 1870 break; 1871 case PMC_EV_IAP_ARCH_LLC_MIS: 1872 ae = CORE_AE_LLC_MISSES; 1873 *map = PMC_EV_IAP_EVENT_2EH_41H; 1874 break; 1875 case PMC_EV_IAP_ARCH_BR_INS_RET: 1876 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1877 *map = PMC_EV_IAP_EVENT_C4H_00H; 1878 break; 1879 case PMC_EV_IAP_ARCH_BR_MIS_RET: 1880 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1881 *map = PMC_EV_IAP_EVENT_C5H_00H; 1882 break; 1883 1884 default: /* Non architectural event. */ 1885 return (EV_IS_NOTARCH); 1886 } 1887 1888 return (((core_architectural_events & (1 << ae)) == 0) ? 1889 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); 1890 } 1891 1892 static int 1893 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1894 { 1895 uint32_t mask; 1896 1897 switch (pe) { 1898 /* 1899 * Events valid only on counter 0, 1. 1900 */ 1901 case PMC_EV_IAP_EVENT_40H_01H: 1902 case PMC_EV_IAP_EVENT_40H_02H: 1903 case PMC_EV_IAP_EVENT_40H_04H: 1904 case PMC_EV_IAP_EVENT_40H_08H: 1905 case PMC_EV_IAP_EVENT_40H_0FH: 1906 case PMC_EV_IAP_EVENT_41H_02H: 1907 case PMC_EV_IAP_EVENT_41H_04H: 1908 case PMC_EV_IAP_EVENT_41H_08H: 1909 case PMC_EV_IAP_EVENT_42H_01H: 1910 case PMC_EV_IAP_EVENT_42H_02H: 1911 case PMC_EV_IAP_EVENT_42H_04H: 1912 case PMC_EV_IAP_EVENT_42H_08H: 1913 case PMC_EV_IAP_EVENT_43H_01H: 1914 case PMC_EV_IAP_EVENT_43H_02H: 1915 case PMC_EV_IAP_EVENT_51H_01H: 1916 case PMC_EV_IAP_EVENT_51H_02H: 1917 case PMC_EV_IAP_EVENT_51H_04H: 1918 case PMC_EV_IAP_EVENT_51H_08H: 1919 case PMC_EV_IAP_EVENT_63H_01H: 1920 case PMC_EV_IAP_EVENT_63H_02H: 1921 mask = 0x3; 1922 break; 1923 1924 default: 1925 mask = ~0; /* Any row index is ok. */ 1926 } 1927 1928 return (mask & (1 << ri)); 1929 } 1930 1931 static int 1932 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1933 { 1934 uint32_t mask; 1935 1936 switch (pe) { 1937 /* 1938 * Events valid only on counter 0. 1939 */ 1940 case PMC_EV_IAP_EVENT_60H_01H: 1941 case PMC_EV_IAP_EVENT_60H_02H: 1942 case PMC_EV_IAP_EVENT_60H_04H: 1943 case PMC_EV_IAP_EVENT_60H_08H: 1944 case PMC_EV_IAP_EVENT_B3H_01H: 1945 case PMC_EV_IAP_EVENT_B3H_02H: 1946 case PMC_EV_IAP_EVENT_B3H_04H: 1947 mask = 0x1; 1948 break; 1949 1950 /* 1951 * Events valid only on counter 0, 1. 1952 */ 1953 case PMC_EV_IAP_EVENT_4CH_01H: 1954 case PMC_EV_IAP_EVENT_4EH_01H: 1955 case PMC_EV_IAP_EVENT_4EH_02H: 1956 case PMC_EV_IAP_EVENT_4EH_04H: 1957 case PMC_EV_IAP_EVENT_51H_01H: 1958 case PMC_EV_IAP_EVENT_51H_02H: 1959 case PMC_EV_IAP_EVENT_51H_04H: 1960 case PMC_EV_IAP_EVENT_51H_08H: 1961 case PMC_EV_IAP_EVENT_63H_01H: 1962 case PMC_EV_IAP_EVENT_63H_02H: 1963 mask = 0x3; 1964 break; 1965 1966 default: 1967 mask = ~0; /* Any row index is ok. */ 1968 } 1969 1970 return (mask & (1 << ri)); 1971 } 1972 1973 static int 1974 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 1975 { 1976 uint32_t mask; 1977 1978 switch (pe) { 1979 /* Events valid only on counter 0. */ 1980 case PMC_EV_IAP_EVENT_B7H_01H: 1981 mask = 0x1; 1982 break; 1983 /* Events valid only on counter 1. */ 1984 case PMC_EV_IAP_EVENT_C0H_01H: 1985 mask = 0x2; 1986 break; 1987 /* Events valid only on counter 2. */ 1988 case PMC_EV_IAP_EVENT_48H_01H: 1989 case PMC_EV_IAP_EVENT_A2H_02H: 1990 case PMC_EV_IAP_EVENT_A3H_08H: 1991 mask = 0x4; 1992 break; 1993 /* Events valid only on counter 3. */ 1994 case PMC_EV_IAP_EVENT_BBH_01H: 1995 case PMC_EV_IAP_EVENT_CDH_01H: 1996 case PMC_EV_IAP_EVENT_CDH_02H: 1997 mask = 0x8; 1998 break; 1999 default: 2000 mask = ~0; /* Any row index is ok. */ 2001 } 2002 2003 return (mask & (1 << ri)); 2004 } 2005 2006 static int 2007 iap_event_ok_on_counter(enum pmc_event pe, int ri) 2008 { 2009 uint32_t mask; 2010 2011 switch (pe) { 2012 /* 2013 * Events valid only on counter 0. 2014 */ 2015 case PMC_EV_IAP_EVENT_10H_00H: 2016 case PMC_EV_IAP_EVENT_14H_00H: 2017 case PMC_EV_IAP_EVENT_18H_00H: 2018 case PMC_EV_IAP_EVENT_B3H_01H: 2019 case PMC_EV_IAP_EVENT_B3H_02H: 2020 case PMC_EV_IAP_EVENT_B3H_04H: 2021 case PMC_EV_IAP_EVENT_C1H_00H: 2022 case PMC_EV_IAP_EVENT_CBH_01H: 2023 case PMC_EV_IAP_EVENT_CBH_02H: 2024 mask = (1 << 0); 2025 break; 2026 2027 /* 2028 * Events valid only on counter 1. 2029 */ 2030 case PMC_EV_IAP_EVENT_11H_00H: 2031 case PMC_EV_IAP_EVENT_12H_00H: 2032 case PMC_EV_IAP_EVENT_13H_00H: 2033 mask = (1 << 1); 2034 break; 2035 2036 default: 2037 mask = ~0; /* Any row index is ok. */ 2038 } 2039 2040 return (mask & (1 << ri)); 2041 } 2042 2043 static int 2044 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 2045 const struct pmc_op_pmcallocate *a) 2046 { 2047 int arch, n, model; 2048 enum pmc_event ev, map; 2049 struct iap_event_descr *ie; 2050 uint32_t c, caps, config, cpuflag, evsel, mask; 2051 2052 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2053 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2054 KASSERT(ri >= 0 && ri < core_iap_npmc, 2055 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 2056 2057 /* check requested capabilities */ 2058 caps = a->pm_caps; 2059 if ((IAP_PMC_CAPS & caps) != caps) 2060 return (EPERM); 2061 map = 0; /* XXX: silent GCC warning */ 2062 arch = iap_is_event_architectural(pm->pm_event, &map); 2063 if (arch == EV_IS_ARCH_NOTSUPP) 2064 return (EOPNOTSUPP); 2065 else if (arch == EV_IS_ARCH_SUPP) 2066 ev = map; 2067 else 2068 ev = pm->pm_event; 2069 2070 /* 2071 * A small number of events are not supported in all the 2072 * processors based on a given microarchitecture. 2073 */ 2074 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 2075 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 2076 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 2077 return (EINVAL); 2078 } 2079 2080 switch (core_cputype) { 2081 case PMC_CPU_INTEL_COREI7: 2082 case PMC_CPU_INTEL_NEHALEM_EX: 2083 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 2084 return (EINVAL); 2085 break; 2086 case PMC_CPU_INTEL_BROADWELL: 2087 case PMC_CPU_INTEL_SANDYBRIDGE: 2088 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2089 case PMC_CPU_INTEL_IVYBRIDGE: 2090 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2091 case PMC_CPU_INTEL_HASWELL: 2092 case PMC_CPU_INTEL_HASWELL_XEON: 2093 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 2094 return (EINVAL); 2095 break; 2096 case PMC_CPU_INTEL_WESTMERE: 2097 case PMC_CPU_INTEL_WESTMERE_EX: 2098 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 2099 return (EINVAL); 2100 break; 2101 default: 2102 if (iap_event_ok_on_counter(ev, ri) == 0) 2103 return (EINVAL); 2104 } 2105 2106 /* 2107 * Look for an event descriptor with matching CPU and event id 2108 * fields. 2109 */ 2110 2111 switch (core_cputype) { 2112 default: 2113 case PMC_CPU_INTEL_ATOM: 2114 cpuflag = IAP_F_CA; 2115 break; 2116 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2117 cpuflag = IAP_F_CAS; 2118 break; 2119 case PMC_CPU_INTEL_BROADWELL: 2120 cpuflag = IAP_F_BW; 2121 break; 2122 case PMC_CPU_INTEL_CORE: 2123 cpuflag = IAP_F_CC; 2124 break; 2125 case PMC_CPU_INTEL_CORE2: 2126 cpuflag = IAP_F_CC2; 2127 break; 2128 case PMC_CPU_INTEL_CORE2EXTREME: 2129 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 2130 break; 2131 case PMC_CPU_INTEL_COREI7: 2132 cpuflag = IAP_F_I7; 2133 break; 2134 case PMC_CPU_INTEL_HASWELL: 2135 cpuflag = IAP_F_HW; 2136 break; 2137 case PMC_CPU_INTEL_HASWELL_XEON: 2138 cpuflag = IAP_F_HWX; 2139 break; 2140 case PMC_CPU_INTEL_IVYBRIDGE: 2141 cpuflag = IAP_F_IB; 2142 break; 2143 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2144 cpuflag = IAP_F_IBX; 2145 break; 2146 case PMC_CPU_INTEL_SANDYBRIDGE: 2147 cpuflag = IAP_F_SB; 2148 break; 2149 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2150 cpuflag = IAP_F_SBX; 2151 break; 2152 case PMC_CPU_INTEL_WESTMERE: 2153 cpuflag = IAP_F_WM; 2154 break; 2155 } 2156 2157 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 2158 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2159 break; 2160 2161 if (n == niap_events) 2162 return (EINVAL); 2163 2164 /* 2165 * A matching event descriptor has been found, so start 2166 * assembling the contents of the event select register. 2167 */ 2168 evsel = ie->iap_evcode; 2169 2170 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2171 2172 /* 2173 * If the event uses a fixed umask value, reject any umask 2174 * bits set by the user. 2175 */ 2176 if (ie->iap_flags & IAP_F_FM) { 2177 2178 if (IAP_UMASK(config) != 0) 2179 return (EINVAL); 2180 2181 evsel |= (ie->iap_umask << 8); 2182 2183 } else { 2184 2185 /* 2186 * Otherwise, the UMASK value needs to be taken from 2187 * the MD fields of the allocation request. Reject 2188 * requests that specify reserved bits. 2189 */ 2190 2191 mask = 0; 2192 2193 if (ie->iap_umask & IAP_M_CORE) { 2194 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2195 c != IAP_CORE_THIS) 2196 return (EINVAL); 2197 mask |= IAP_F_CORE; 2198 } 2199 2200 if (ie->iap_umask & IAP_M_AGENT) 2201 mask |= IAP_F_AGENT; 2202 2203 if (ie->iap_umask & IAP_M_PREFETCH) { 2204 2205 if ((c = (config & IAP_F_PREFETCH)) == 2206 IAP_PREFETCH_RESERVED) 2207 return (EINVAL); 2208 2209 mask |= IAP_F_PREFETCH; 2210 } 2211 2212 if (ie->iap_umask & IAP_M_MESI) 2213 mask |= IAP_F_MESI; 2214 2215 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2216 mask |= IAP_F_SNOOPRESPONSE; 2217 2218 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2219 mask |= IAP_F_SNOOPTYPE; 2220 2221 if (ie->iap_umask & IAP_M_TRANSITION) 2222 mask |= IAP_F_TRANSITION; 2223 2224 /* 2225 * If bits outside of the allowed set of umask bits 2226 * are set, reject the request. 2227 */ 2228 if (config & ~mask) 2229 return (EINVAL); 2230 2231 evsel |= (config & mask); 2232 2233 } 2234 2235 /* 2236 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2237 */ 2238 if (core_cputype == PMC_CPU_INTEL_ATOM || 2239 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 2240 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2241 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2242 evsel |= (config & IAP_ANY); 2243 else if (config & IAP_ANY) 2244 return (EINVAL); 2245 2246 /* 2247 * Check offcore response configuration. 2248 */ 2249 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2250 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2251 ev != PMC_EV_IAP_EVENT_BBH_01H) 2252 return (EINVAL); 2253 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2254 ev == PMC_EV_IAP_EVENT_BBH_01H) 2255 return (EINVAL); 2256 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2257 core_cputype == PMC_CPU_INTEL_WESTMERE || 2258 core_cputype == PMC_CPU_INTEL_NEHALEM_EX || 2259 core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && 2260 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2261 return (EINVAL); 2262 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2263 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2264 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2265 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2266 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2267 return (EINVAL); 2268 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2269 } 2270 2271 if (caps & PMC_CAP_THRESHOLD) 2272 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2273 if (caps & PMC_CAP_USER) 2274 evsel |= IAP_USR; 2275 if (caps & PMC_CAP_SYSTEM) 2276 evsel |= IAP_OS; 2277 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2278 evsel |= (IAP_OS | IAP_USR); 2279 if (caps & PMC_CAP_EDGE) 2280 evsel |= IAP_EDGE; 2281 if (caps & PMC_CAP_INVERT) 2282 evsel |= IAP_INV; 2283 if (caps & PMC_CAP_INTERRUPT) 2284 evsel |= IAP_INT; 2285 2286 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2287 2288 return (0); 2289 } 2290 2291 static int 2292 iap_config_pmc(int cpu, int ri, struct pmc *pm) 2293 { 2294 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2295 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2296 2297 KASSERT(ri >= 0 && ri < core_iap_npmc, 2298 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2299 2300 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2301 2302 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2303 cpu)); 2304 2305 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2306 2307 return (0); 2308 } 2309 2310 static int 2311 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2312 { 2313 int error; 2314 struct pmc_hw *phw; 2315 char iap_name[PMC_NAME_MAX]; 2316 2317 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2318 2319 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2320 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2321 NULL)) != 0) 2322 return (error); 2323 2324 pi->pm_class = PMC_CLASS_IAP; 2325 2326 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2327 pi->pm_enabled = TRUE; 2328 *ppmc = phw->phw_pmc; 2329 } else { 2330 pi->pm_enabled = FALSE; 2331 *ppmc = NULL; 2332 } 2333 2334 return (0); 2335 } 2336 2337 static int 2338 iap_get_config(int cpu, int ri, struct pmc **ppm) 2339 { 2340 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2341 2342 return (0); 2343 } 2344 2345 static int 2346 iap_get_msr(int ri, uint32_t *msr) 2347 { 2348 KASSERT(ri >= 0 && ri < core_iap_npmc, 2349 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2350 2351 *msr = ri; 2352 2353 return (0); 2354 } 2355 2356 static int 2357 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2358 { 2359 struct pmc *pm; 2360 pmc_value_t tmp; 2361 2362 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2363 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2364 KASSERT(ri >= 0 && ri < core_iap_npmc, 2365 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2366 2367 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2368 2369 KASSERT(pm, 2370 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2371 ri)); 2372 2373 tmp = rdpmc(ri); 2374 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2375 *v = iap_perfctr_value_to_reload_count(tmp); 2376 else 2377 *v = tmp & ((1ULL << core_iap_width) - 1); 2378 2379 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2380 ri, *v); 2381 2382 return (0); 2383 } 2384 2385 static int 2386 iap_release_pmc(int cpu, int ri, struct pmc *pm) 2387 { 2388 (void) pm; 2389 2390 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2391 pm); 2392 2393 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2394 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2395 KASSERT(ri >= 0 && ri < core_iap_npmc, 2396 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2397 2398 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2399 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2400 2401 return (0); 2402 } 2403 2404 static int 2405 iap_start_pmc(int cpu, int ri) 2406 { 2407 struct pmc *pm; 2408 uint32_t evsel; 2409 struct core_cpu *cc; 2410 2411 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2412 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2413 KASSERT(ri >= 0 && ri < core_iap_npmc, 2414 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2415 2416 cc = core_pcpu[cpu]; 2417 pm = cc->pc_corepmcs[ri].phw_pmc; 2418 2419 KASSERT(pm, 2420 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2421 __LINE__, cpu, ri)); 2422 2423 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2424 2425 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2426 2427 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2428 cpu, ri, IAP_EVSEL0 + ri, evsel); 2429 2430 /* Event specific configuration. */ 2431 switch (pm->pm_event) { 2432 case PMC_EV_IAP_EVENT_B7H_01H: 2433 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2434 break; 2435 case PMC_EV_IAP_EVENT_BBH_01H: 2436 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2437 break; 2438 default: 2439 break; 2440 } 2441 2442 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2443 2444 if (core_cputype == PMC_CPU_INTEL_CORE) 2445 return (0); 2446 2447 do { 2448 cc->pc_resync = 0; 2449 cc->pc_globalctrl |= (1ULL << ri); 2450 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2451 } while (cc->pc_resync != 0); 2452 2453 return (0); 2454 } 2455 2456 static int 2457 iap_stop_pmc(int cpu, int ri) 2458 { 2459 struct pmc *pm; 2460 struct core_cpu *cc; 2461 uint64_t msr; 2462 2463 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2464 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2465 KASSERT(ri >= 0 && ri < core_iap_npmc, 2466 ("[core,%d] illegal row index %d", __LINE__, ri)); 2467 2468 cc = core_pcpu[cpu]; 2469 pm = cc->pc_corepmcs[ri].phw_pmc; 2470 2471 KASSERT(pm, 2472 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2473 cpu, ri)); 2474 2475 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2476 2477 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2478 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2479 2480 if (core_cputype == PMC_CPU_INTEL_CORE) 2481 return (0); 2482 2483 msr = 0; 2484 do { 2485 cc->pc_resync = 0; 2486 cc->pc_globalctrl &= ~(1ULL << ri); 2487 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2488 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2489 } while (cc->pc_resync != 0); 2490 2491 return (0); 2492 } 2493 2494 static int 2495 iap_write_pmc(int cpu, int ri, pmc_value_t v) 2496 { 2497 struct pmc *pm; 2498 struct core_cpu *cc; 2499 2500 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2501 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2502 KASSERT(ri >= 0 && ri < core_iap_npmc, 2503 ("[core,%d] illegal row index %d", __LINE__, ri)); 2504 2505 cc = core_pcpu[cpu]; 2506 pm = cc->pc_corepmcs[ri].phw_pmc; 2507 2508 KASSERT(pm, 2509 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2510 cpu, ri)); 2511 2512 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2513 IAP_PMC0 + ri, v); 2514 2515 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2516 v = iap_reload_count_to_perfctr_value(v); 2517 2518 /* 2519 * Write the new value to the counter. The counter will be in 2520 * a stopped state when the pcd_write() entry point is called. 2521 */ 2522 2523 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2524 2525 return (0); 2526 } 2527 2528 2529 static void 2530 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2531 int flags) 2532 { 2533 struct pmc_classdep *pcd; 2534 2535 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2536 2537 PMCDBG0(MDP,INI,1, "iap-initialize"); 2538 2539 /* Remember the set of architectural events supported. */ 2540 core_architectural_events = ~flags; 2541 2542 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2543 2544 pcd->pcd_caps = IAP_PMC_CAPS; 2545 pcd->pcd_class = PMC_CLASS_IAP; 2546 pcd->pcd_num = npmc; 2547 pcd->pcd_ri = md->pmd_npmc; 2548 pcd->pcd_width = pmcwidth; 2549 2550 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2551 pcd->pcd_config_pmc = iap_config_pmc; 2552 pcd->pcd_describe = iap_describe; 2553 pcd->pcd_get_config = iap_get_config; 2554 pcd->pcd_get_msr = iap_get_msr; 2555 pcd->pcd_pcpu_fini = core_pcpu_fini; 2556 pcd->pcd_pcpu_init = core_pcpu_init; 2557 pcd->pcd_read_pmc = iap_read_pmc; 2558 pcd->pcd_release_pmc = iap_release_pmc; 2559 pcd->pcd_start_pmc = iap_start_pmc; 2560 pcd->pcd_stop_pmc = iap_stop_pmc; 2561 pcd->pcd_write_pmc = iap_write_pmc; 2562 2563 md->pmd_npmc += npmc; 2564 } 2565 2566 static int 2567 core_intr(int cpu, struct trapframe *tf) 2568 { 2569 pmc_value_t v; 2570 struct pmc *pm; 2571 struct core_cpu *cc; 2572 int error, found_interrupt, ri; 2573 uint64_t msr; 2574 2575 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2576 TRAPF_USERMODE(tf)); 2577 2578 found_interrupt = 0; 2579 cc = core_pcpu[cpu]; 2580 2581 for (ri = 0; ri < core_iap_npmc; ri++) { 2582 2583 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2584 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2585 continue; 2586 2587 if (!iap_pmc_has_overflowed(ri)) 2588 continue; 2589 2590 found_interrupt = 1; 2591 2592 if (pm->pm_state != PMC_STATE_RUNNING) 2593 continue; 2594 2595 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2596 TRAPF_USERMODE(tf)); 2597 2598 v = pm->pm_sc.pm_reloadcount; 2599 v = iap_reload_count_to_perfctr_value(v); 2600 2601 /* 2602 * Stop the counter, reload it but only restart it if 2603 * the PMC is not stalled. 2604 */ 2605 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2606 wrmsr(IAP_EVSEL0 + ri, msr); 2607 wrmsr(IAP_PMC0 + ri, v); 2608 2609 if (error) 2610 continue; 2611 2612 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2613 IAP_EN)); 2614 } 2615 2616 if (found_interrupt) 2617 lapic_reenable_pmc(); 2618 2619 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2620 &pmc_stats.pm_intr_ignored, 1); 2621 2622 return (found_interrupt); 2623 } 2624 2625 static int 2626 core2_intr(int cpu, struct trapframe *tf) 2627 { 2628 int error, found_interrupt, n; 2629 uint64_t flag, intrstatus, intrenable, msr; 2630 struct pmc *pm; 2631 struct core_cpu *cc; 2632 pmc_value_t v; 2633 2634 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2635 TRAPF_USERMODE(tf)); 2636 2637 /* 2638 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2639 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2640 * the current set of interrupting PMCs and process these 2641 * after stopping them. 2642 */ 2643 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2644 intrenable = intrstatus & core_pmcmask; 2645 2646 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2647 (uintmax_t) intrstatus); 2648 2649 found_interrupt = 0; 2650 cc = core_pcpu[cpu]; 2651 2652 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2653 2654 cc->pc_globalctrl &= ~intrenable; 2655 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2656 2657 /* 2658 * Stop PMCs and clear overflow status bits. 2659 */ 2660 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2661 wrmsr(IA_GLOBAL_CTRL, msr); 2662 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2663 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2664 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2665 2666 /* 2667 * Look for interrupts from fixed function PMCs. 2668 */ 2669 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2670 n++, flag <<= 1) { 2671 2672 if ((intrstatus & flag) == 0) 2673 continue; 2674 2675 found_interrupt = 1; 2676 2677 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2678 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2679 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2680 continue; 2681 2682 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2683 TRAPF_USERMODE(tf)); 2684 if (error) 2685 intrenable &= ~flag; 2686 2687 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2688 2689 /* Reload sampling count. */ 2690 wrmsr(IAF_CTR0 + n, v); 2691 2692 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 2693 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2694 } 2695 2696 /* 2697 * Process interrupts from the programmable counters. 2698 */ 2699 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2700 if ((intrstatus & flag) == 0) 2701 continue; 2702 2703 found_interrupt = 1; 2704 2705 pm = cc->pc_corepmcs[n].phw_pmc; 2706 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2707 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2708 continue; 2709 2710 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2711 TRAPF_USERMODE(tf)); 2712 if (error) 2713 intrenable &= ~flag; 2714 2715 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2716 2717 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2718 (uintmax_t) v); 2719 2720 /* Reload sampling count. */ 2721 wrmsr(IAP_PMC0 + n, v); 2722 } 2723 2724 /* 2725 * Reenable all non-stalled PMCs. 2726 */ 2727 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2728 (uintmax_t) intrenable); 2729 2730 cc->pc_globalctrl |= intrenable; 2731 2732 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2733 2734 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2735 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2736 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2737 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2738 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2739 2740 if (found_interrupt) 2741 lapic_reenable_pmc(); 2742 2743 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2744 &pmc_stats.pm_intr_ignored, 1); 2745 2746 return (found_interrupt); 2747 } 2748 2749 int 2750 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 2751 { 2752 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2753 int ipa_version, flags, nflags; 2754 2755 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2756 2757 ipa_version = (version_override > 0) ? version_override : 2758 cpuid[CORE_CPUID_EAX] & 0xFF; 2759 core_cputype = md->pmd_cputype; 2760 2761 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2762 core_cputype, maxcpu, ipa_version); 2763 2764 if (ipa_version < 1 || ipa_version > 3 || 2765 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 2766 /* Unknown PMC architecture. */ 2767 printf("hwpc_core: unknown PMC architecture: %d\n", 2768 ipa_version); 2769 return (EPROGMISMATCH); 2770 } 2771 2772 core_pmcmask = 0; 2773 2774 /* 2775 * Initialize programmable counters. 2776 */ 2777 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2778 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2779 2780 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2781 2782 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2783 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2784 2785 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2786 2787 /* 2788 * Initialize fixed function counters, if present. 2789 */ 2790 if (core_cputype != PMC_CPU_INTEL_CORE) { 2791 core_iaf_ri = core_iap_npmc; 2792 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2793 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2794 2795 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2796 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2797 } 2798 2799 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2800 core_iaf_ri); 2801 2802 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 2803 M_ZERO | M_WAITOK); 2804 2805 /* 2806 * Choose the appropriate interrupt handler. 2807 */ 2808 if (ipa_version == 1) 2809 md->pmd_intr = core_intr; 2810 else 2811 md->pmd_intr = core2_intr; 2812 2813 md->pmd_pcpu_fini = NULL; 2814 md->pmd_pcpu_init = NULL; 2815 2816 return (0); 2817 } 2818 2819 void 2820 pmc_core_finalize(struct pmc_mdep *md) 2821 { 2822 PMCDBG0(MDP,INI,1, "core-finalize"); 2823 2824 free(core_pcpu, M_PMC); 2825 core_pcpu = NULL; 2826 } 2827