1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #include <machine/apicvar.h> 42 #include <machine/cpu.h> 43 #include <machine/cpufunc.h> 44 #include <machine/md_var.h> 45 #include <machine/specialreg.h> 46 47 #define CORE_CPUID_REQUEST 0xA 48 #define CORE_CPUID_REQUEST_SIZE 0x4 49 #define CORE_CPUID_EAX 0x0 50 #define CORE_CPUID_EBX 0x1 51 #define CORE_CPUID_ECX 0x2 52 #define CORE_CPUID_EDX 0x3 53 54 #define IAF_PMC_CAPS \ 55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT) 56 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 57 58 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 59 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 60 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 61 62 /* 63 * "Architectural" events defined by Intel. The values of these 64 * symbols correspond to positions in the bitmask returned by 65 * the CPUID.0AH instruction. 66 */ 67 enum core_arch_events { 68 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 69 CORE_AE_BRANCH_MISSES_RETIRED = 6, 70 CORE_AE_INSTRUCTION_RETIRED = 1, 71 CORE_AE_LLC_MISSES = 4, 72 CORE_AE_LLC_REFERENCE = 3, 73 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 74 CORE_AE_UNHALTED_CORE_CYCLES = 0 75 }; 76 77 static enum pmc_cputype core_cputype; 78 79 struct core_cpu { 80 volatile uint32_t pc_resync; 81 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 82 volatile uint64_t pc_globalctrl; /* Global control register. */ 83 struct pmc_hw pc_corepmcs[]; 84 }; 85 86 static struct core_cpu **core_pcpu; 87 88 static uint32_t core_architectural_events; 89 static uint64_t core_pmcmask; 90 91 static int core_iaf_ri; /* relative index of fixed counters */ 92 static int core_iaf_width; 93 static int core_iaf_npmc; 94 95 static int core_iap_width; 96 static int core_iap_npmc; 97 98 static int 99 core_pcpu_noop(struct pmc_mdep *md, int cpu) 100 { 101 (void) md; 102 (void) cpu; 103 return (0); 104 } 105 106 static int 107 core_pcpu_init(struct pmc_mdep *md, int cpu) 108 { 109 struct pmc_cpu *pc; 110 struct core_cpu *cc; 111 struct pmc_hw *phw; 112 int core_ri, n, npmc; 113 114 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 115 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 116 117 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 118 119 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 120 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 121 122 if (core_cputype != PMC_CPU_INTEL_CORE) 123 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 124 125 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 126 M_PMC, M_WAITOK | M_ZERO); 127 128 core_pcpu[cpu] = cc; 129 pc = pmc_pcpu[cpu]; 130 131 KASSERT(pc != NULL && cc != NULL, 132 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 133 134 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 135 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 136 PMC_PHW_CPU_TO_STATE(cpu) | 137 PMC_PHW_INDEX_TO_STATE(n + core_ri); 138 phw->phw_pmc = NULL; 139 pc->pc_hwpmcs[n + core_ri] = phw; 140 } 141 142 return (0); 143 } 144 145 static int 146 core_pcpu_fini(struct pmc_mdep *md, int cpu) 147 { 148 int core_ri, n, npmc; 149 struct pmc_cpu *pc; 150 struct core_cpu *cc; 151 uint64_t msr = 0; 152 153 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 154 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 155 156 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 157 158 if ((cc = core_pcpu[cpu]) == NULL) 159 return (0); 160 161 core_pcpu[cpu] = NULL; 162 163 pc = pmc_pcpu[cpu]; 164 165 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 166 cpu)); 167 168 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 169 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 170 171 for (n = 0; n < npmc; n++) { 172 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 173 wrmsr(IAP_EVSEL0 + n, msr); 174 } 175 176 if (core_cputype != PMC_CPU_INTEL_CORE) { 177 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 178 wrmsr(IAF_CTRL, msr); 179 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 180 } 181 182 for (n = 0; n < npmc; n++) 183 pc->pc_hwpmcs[n + core_ri] = NULL; 184 185 free(cc, M_PMC); 186 187 return (0); 188 } 189 190 /* 191 * Fixed function counters. 192 */ 193 194 static pmc_value_t 195 iaf_perfctr_value_to_reload_count(pmc_value_t v) 196 { 197 v &= (1ULL << core_iaf_width) - 1; 198 return (1ULL << core_iaf_width) - v; 199 } 200 201 static pmc_value_t 202 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 203 { 204 return (1ULL << core_iaf_width) - rlc; 205 } 206 207 static int 208 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 209 const struct pmc_op_pmcallocate *a) 210 { 211 enum pmc_event ev; 212 uint32_t caps, flags, validflags; 213 214 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 215 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 216 217 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 218 219 if (ri < 0 || ri > core_iaf_npmc) 220 return (EINVAL); 221 222 caps = a->pm_caps; 223 224 if (a->pm_class != PMC_CLASS_IAF || 225 (caps & IAF_PMC_CAPS) != caps) 226 return (EINVAL); 227 228 ev = pm->pm_event; 229 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 230 return (EINVAL); 231 232 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 233 return (EINVAL); 234 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 235 return (EINVAL); 236 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 237 return (EINVAL); 238 239 flags = a->pm_md.pm_iaf.pm_iaf_flags; 240 241 validflags = IAF_MASK; 242 243 if (core_cputype != PMC_CPU_INTEL_ATOM) 244 validflags &= ~IAF_ANY; 245 246 if ((flags & ~validflags) != 0) 247 return (EINVAL); 248 249 if (caps & PMC_CAP_INTERRUPT) 250 flags |= IAF_PMI; 251 if (caps & PMC_CAP_SYSTEM) 252 flags |= IAF_OS; 253 if (caps & PMC_CAP_USER) 254 flags |= IAF_USR; 255 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 256 flags |= (IAF_OS | IAF_USR); 257 258 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 259 260 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 261 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 262 263 return (0); 264 } 265 266 static int 267 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 268 { 269 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 270 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 271 272 KASSERT(ri >= 0 && ri < core_iaf_npmc, 273 ("[core,%d] illegal row-index %d", __LINE__, ri)); 274 275 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 276 277 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 278 cpu)); 279 280 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 281 282 return (0); 283 } 284 285 static int 286 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 287 { 288 int error; 289 struct pmc_hw *phw; 290 char iaf_name[PMC_NAME_MAX]; 291 292 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 293 294 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 295 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 296 NULL)) != 0) 297 return (error); 298 299 pi->pm_class = PMC_CLASS_IAF; 300 301 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 302 pi->pm_enabled = TRUE; 303 *ppmc = phw->phw_pmc; 304 } else { 305 pi->pm_enabled = FALSE; 306 *ppmc = NULL; 307 } 308 309 return (0); 310 } 311 312 static int 313 iaf_get_config(int cpu, int ri, struct pmc **ppm) 314 { 315 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 316 317 return (0); 318 } 319 320 static int 321 iaf_get_msr(int ri, uint32_t *msr) 322 { 323 KASSERT(ri >= 0 && ri < core_iaf_npmc, 324 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 325 326 *msr = IAF_RI_TO_MSR(ri); 327 328 return (0); 329 } 330 331 static int 332 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 333 { 334 struct pmc *pm; 335 pmc_value_t tmp; 336 337 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 338 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 339 KASSERT(ri >= 0 && ri < core_iaf_npmc, 340 ("[core,%d] illegal row-index %d", __LINE__, ri)); 341 342 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 343 344 KASSERT(pm, 345 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 346 ri, ri + core_iaf_ri)); 347 348 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 349 350 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 351 *v = iaf_perfctr_value_to_reload_count(tmp); 352 else 353 *v = tmp; 354 355 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 356 IAF_RI_TO_MSR(ri), *v); 357 358 return (0); 359 } 360 361 static int 362 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 363 { 364 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 365 366 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 367 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 368 KASSERT(ri >= 0 && ri < core_iaf_npmc, 369 ("[core,%d] illegal row-index %d", __LINE__, ri)); 370 371 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 372 ("[core,%d] PHW pmc non-NULL", __LINE__)); 373 374 return (0); 375 } 376 377 static int 378 iaf_start_pmc(int cpu, int ri) 379 { 380 struct pmc *pm; 381 struct core_cpu *iafc; 382 uint64_t msr = 0; 383 384 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 385 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 386 KASSERT(ri >= 0 && ri < core_iaf_npmc, 387 ("[core,%d] illegal row-index %d", __LINE__, ri)); 388 389 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 390 391 iafc = core_pcpu[cpu]; 392 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 393 394 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 395 396 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 397 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 398 399 do { 400 iafc->pc_resync = 0; 401 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 402 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 403 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 404 IAF_GLOBAL_CTRL_MASK)); 405 } while (iafc->pc_resync != 0); 406 407 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 408 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 409 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 410 411 return (0); 412 } 413 414 static int 415 iaf_stop_pmc(int cpu, int ri) 416 { 417 uint32_t fc; 418 struct core_cpu *iafc; 419 uint64_t msr = 0; 420 421 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 422 423 iafc = core_pcpu[cpu]; 424 425 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 426 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 427 KASSERT(ri >= 0 && ri < core_iaf_npmc, 428 ("[core,%d] illegal row-index %d", __LINE__, ri)); 429 430 fc = (IAF_MASK << (ri * 4)); 431 432 if (core_cputype != PMC_CPU_INTEL_ATOM) 433 fc &= ~IAF_ANY; 434 435 iafc->pc_iafctrl &= ~fc; 436 437 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 438 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 439 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 440 441 do { 442 iafc->pc_resync = 0; 443 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 444 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 445 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 446 IAF_GLOBAL_CTRL_MASK)); 447 } while (iafc->pc_resync != 0); 448 449 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 450 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 451 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 452 453 return (0); 454 } 455 456 static int 457 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 458 { 459 struct core_cpu *cc; 460 struct pmc *pm; 461 uint64_t msr; 462 463 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 464 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 465 KASSERT(ri >= 0 && ri < core_iaf_npmc, 466 ("[core,%d] illegal row-index %d", __LINE__, ri)); 467 468 cc = core_pcpu[cpu]; 469 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 470 471 KASSERT(pm, 472 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 473 474 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 475 v = iaf_reload_count_to_perfctr_value(v); 476 477 /* Turn off fixed counters */ 478 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 479 wrmsr(IAF_CTRL, msr); 480 481 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 482 483 /* Turn on fixed counters */ 484 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 485 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 486 487 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 488 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 489 (uintmax_t) rdmsr(IAF_CTRL), 490 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 491 492 return (0); 493 } 494 495 496 static void 497 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 498 { 499 struct pmc_classdep *pcd; 500 501 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 502 503 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 504 505 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 506 507 pcd->pcd_caps = IAF_PMC_CAPS; 508 pcd->pcd_class = PMC_CLASS_IAF; 509 pcd->pcd_num = npmc; 510 pcd->pcd_ri = md->pmd_npmc; 511 pcd->pcd_width = pmcwidth; 512 513 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 514 pcd->pcd_config_pmc = iaf_config_pmc; 515 pcd->pcd_describe = iaf_describe; 516 pcd->pcd_get_config = iaf_get_config; 517 pcd->pcd_get_msr = iaf_get_msr; 518 pcd->pcd_pcpu_fini = core_pcpu_noop; 519 pcd->pcd_pcpu_init = core_pcpu_noop; 520 pcd->pcd_read_pmc = iaf_read_pmc; 521 pcd->pcd_release_pmc = iaf_release_pmc; 522 pcd->pcd_start_pmc = iaf_start_pmc; 523 pcd->pcd_stop_pmc = iaf_stop_pmc; 524 pcd->pcd_write_pmc = iaf_write_pmc; 525 526 md->pmd_npmc += npmc; 527 } 528 529 /* 530 * Intel programmable PMCs. 531 */ 532 533 /* 534 * Event descriptor tables. 535 * 536 * For each event id, we track: 537 * 538 * 1. The CPUs that the event is valid for. 539 * 540 * 2. If the event uses a fixed UMASK, the value of the umask field. 541 * If the event doesn't use a fixed UMASK, a mask of legal bits 542 * to check against. 543 */ 544 545 struct iap_event_descr { 546 enum pmc_event iap_ev; 547 unsigned char iap_evcode; 548 unsigned char iap_umask; 549 unsigned char iap_flags; 550 }; 551 552 #define IAP_F_CC (1 << 0) /* CPU: Core */ 553 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 554 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 555 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 556 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 557 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 558 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 559 #define IAP_F_FM (1 << 6) /* Fixed mask */ 560 561 #define IAP_F_ALLCPUSCORE2 \ 562 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 563 564 /* Sub fields of UMASK that this event supports. */ 565 #define IAP_M_CORE (1 << 0) /* Core specificity */ 566 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 567 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 568 #define IAP_M_MESI (1 << 3) /* MESI */ 569 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 570 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 571 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 572 573 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 574 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 575 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 576 #define IAP_F_MESI (0xF << 8) /* MESI */ 577 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 578 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 579 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 580 581 #define IAP_PREFETCH_RESERVED (0x2 << 12) 582 #define IAP_CORE_THIS (0x1 << 14) 583 #define IAP_CORE_ALL (0x3 << 14) 584 #define IAP_F_CMASK 0xFF000000 585 586 static struct iap_event_descr iap_events[] = { 587 #undef IAPDESCR 588 #define IAPDESCR(N,EV,UM,FLAGS) { \ 589 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 590 .iap_evcode = (EV), \ 591 .iap_umask = (UM), \ 592 .iap_flags = (FLAGS) \ 593 } 594 595 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 596 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 597 598 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 599 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O), 600 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_WM), 601 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 602 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 603 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 604 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 605 606 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 607 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 608 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 609 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 610 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 611 612 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 613 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O), 614 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM), 615 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), 616 617 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 618 IAP_F_CC2E | IAP_F_CA), 619 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 620 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 621 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 622 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 623 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 624 625 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 626 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM), 627 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 628 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 629 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 630 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA), 631 632 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 633 IAP_F_I7 | IAP_F_WM), 634 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 635 IAP_F_I7 | IAP_F_WM), 636 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 637 IAP_F_WM), 638 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 639 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 640 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 641 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 642 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 643 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 644 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 645 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O), 646 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), 647 648 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 649 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 650 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 651 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 652 653 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 654 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 655 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 656 657 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 658 IAP_F_WM), 659 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 660 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 661 662 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 663 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 664 665 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 666 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 667 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 668 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 669 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 670 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 671 672 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 673 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 674 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 675 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 676 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 677 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 678 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 679 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 680 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 681 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 682 683 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 684 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA), 685 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 686 687 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 688 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 689 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 690 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 691 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 692 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 693 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 694 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 695 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 696 697 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 698 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 699 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 700 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 701 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 702 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 703 704 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 705 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 706 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 707 708 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 709 710 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 711 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 712 713 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 714 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 715 IAP_F_I7 | IAP_F_WM), 716 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 717 718 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 719 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 720 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 721 722 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 723 724 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 725 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 726 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 727 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 728 729 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 730 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 731 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 732 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 733 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 734 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 735 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 736 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 737 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 738 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 739 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 740 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 741 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 742 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 743 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 744 745 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 746 747 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 748 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 749 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 750 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 751 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 752 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 753 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 754 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 755 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 756 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 757 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 758 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 759 760 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 761 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 762 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 763 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O), 764 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 765 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 766 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 767 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 768 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 769 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 770 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 771 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 772 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 773 774 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 775 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 776 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 777 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 778 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 779 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 780 781 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 782 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 783 IAP_F_CA | IAP_F_CC2), 784 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 785 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 786 787 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 788 IAP_F_ALLCPUSCORE2), 789 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 790 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 791 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7), 792 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7), 793 794 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 795 IAP_F_ALLCPUSCORE2), 796 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 797 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 798 799 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 800 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 801 802 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 803 804 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 805 IAP_F_I7 | IAP_F_WM), 806 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 807 IAP_F_I7 | IAP_F_WM), 808 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 809 810 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 811 812 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 813 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 814 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 815 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 816 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 817 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 818 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 819 820 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 821 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 822 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 823 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 824 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 825 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 826 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 827 828 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 829 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 830 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 831 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 832 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 833 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 834 835 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 836 IAP_F_I7), 837 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 838 IAP_F_CC2 | IAP_F_I7), 839 840 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 841 842 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 843 844 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 845 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 846 847 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 848 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 849 850 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 851 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 852 IAP_F_I7 | IAP_F_WM), 853 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 854 IAP_F_I7 | IAP_F_WM), 855 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM), 856 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 857 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7), 858 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O), 859 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7), 860 861 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 862 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 863 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 864 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 865 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 866 867 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 868 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 869 870 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 871 872 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 873 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 874 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 875 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 876 877 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 878 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 879 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 880 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 881 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 882 883 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 884 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 885 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 886 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 887 888 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 889 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 890 891 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 892 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 893 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 894 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 895 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 896 897 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 898 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 899 900 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 901 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 902 903 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 904 IAP_F_CA | IAP_F_CC2), 905 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 906 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 907 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 908 909 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 910 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 911 912 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 913 IAP_F_CA | IAP_F_CC2), 914 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 915 916 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 917 918 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 919 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 920 921 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 922 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 923 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 924 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 925 926 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 927 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 928 929 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 930 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 931 932 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 933 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 934 935 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 936 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 937 938 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 939 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 940 941 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 942 IAP_F_CA | IAP_F_CC2), 943 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 944 945 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 946 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 947 948 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 949 950 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 951 952 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 953 954 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 955 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 956 957 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 958 959 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 960 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 961 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 962 IAP_F_WM), 963 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 964 IAP_F_WM), 965 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 966 967 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 968 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 969 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 970 971 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 972 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 973 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 974 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 975 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 976 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 977 978 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 979 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 980 981 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 982 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 983 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 984 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 985 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O), 986 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O), 987 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O), 988 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 989 990 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 991 992 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 993 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 994 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 995 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 996 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 997 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 998 999 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1000 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1001 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1002 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1003 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1004 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1005 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1006 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1007 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1008 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1009 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1010 1011 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1012 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1013 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1014 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1015 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1016 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1017 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1018 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1019 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1020 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1021 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1022 1023 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1024 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1025 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1026 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1027 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1028 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1029 1030 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1031 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1032 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1033 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1034 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1035 1036 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1037 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1038 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1039 1040 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1041 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1042 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1043 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1044 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1045 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1046 1047 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1048 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1049 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1050 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1051 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1052 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1053 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1054 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1055 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1056 1057 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1058 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1059 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1060 1061 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1062 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1063 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1064 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1065 1066 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1067 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1068 1069 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1070 1071 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1072 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1073 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1074 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1075 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1076 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1077 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1078 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1079 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1080 1081 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1082 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1083 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1084 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1085 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1086 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1087 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1088 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1089 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1090 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1091 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1092 IAP_F_WM), 1093 1094 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1095 1096 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1097 IAP_F_WM | IAP_F_I7O), 1098 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1099 IAP_F_WM | IAP_F_I7O), 1100 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1101 IAP_F_WM | IAP_F_I7O), 1102 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1103 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1104 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1105 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1106 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1107 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1108 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1109 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1110 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1111 1112 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1113 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1114 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1115 1116 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1117 1118 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1119 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1120 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1121 1122 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1123 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1124 1125 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1126 1127 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1128 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1129 IAP_F_I7 | IAP_F_WM), 1130 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1131 IAP_F_I7 | IAP_F_WM), 1132 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1133 IAP_F_I7 | IAP_F_WM), 1134 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1135 1136 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1137 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1138 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1139 1140 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1141 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1142 IAP_F_I7 | IAP_F_WM), 1143 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1144 IAP_F_I7 | IAP_F_WM), 1145 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1146 IAP_F_I7 | IAP_F_WM), 1147 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1148 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1149 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1150 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 1151 1152 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1153 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1154 IAP_F_I7 | IAP_F_WM), 1155 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1156 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1157 IAP_F_I7 | IAP_F_WM), 1158 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1159 1160 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1161 IAP_F_I7 | IAP_F_WM), 1162 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1163 IAP_F_I7 | IAP_F_WM), 1164 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1165 IAP_F_I7 | IAP_F_WM), 1166 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1167 IAP_F_I7 | IAP_F_WM), 1168 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1169 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1170 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1171 1172 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1173 IAP_F_I7 | IAP_F_WM), 1174 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM), 1175 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1176 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM), 1177 1178 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1179 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1180 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1181 1182 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1183 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1184 IAP_F_I7 | IAP_F_WM), 1185 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1186 IAP_F_I7 | IAP_F_WM), 1187 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1188 IAP_F_I7 | IAP_F_WM), 1189 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1190 IAP_F_I7 | IAP_F_WM), 1191 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1192 IAP_F_I7 | IAP_F_WM), 1193 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1194 1195 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1196 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1197 1198 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1199 1200 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1201 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1202 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1203 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1204 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1205 1206 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1207 IAP_F_I7 | IAP_F_WM), 1208 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1209 IAP_F_I7 | IAP_F_WM), 1210 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1211 IAP_F_I7 | IAP_F_WM), 1212 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1213 IAP_F_I7 | IAP_F_WM), 1214 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1215 IAP_F_WM), 1216 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1217 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1218 1219 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1220 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1221 IAP_F_I7 | IAP_F_WM), 1222 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1223 IAP_F_I7 | IAP_F_WM), 1224 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1225 1226 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1227 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1228 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1229 1230 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1231 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1232 1233 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM), 1234 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1235 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1236 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1237 1238 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1239 IAP_F_I7 | IAP_F_WM), 1240 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1241 IAP_F_I7 | IAP_F_WM), 1242 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1243 IAP_F_I7 | IAP_F_WM), 1244 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1245 IAP_F_I7 | IAP_F_WM), 1246 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1247 IAP_F_I7 | IAP_F_WM), 1248 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1249 1250 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1251 IAP_F_I7 | IAP_F_WM), 1252 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1253 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1254 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1255 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1256 1257 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1258 IAP_F_I7 | IAP_F_WM), 1259 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1260 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1261 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1262 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1263 1264 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1265 1266 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1267 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1268 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1269 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1270 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1271 1272 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1273 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1274 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1275 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1276 1277 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1278 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1279 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1280 1281 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1282 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1283 1284 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1285 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1286 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1287 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1288 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1289 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1290 1291 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1292 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1293 IAP_F_WM), 1294 1295 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1296 1297 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1298 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1299 1300 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1301 1302 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1303 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1304 IAP_F_WM), 1305 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1306 1307 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1308 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1309 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1310 1311 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1312 1313 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1314 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1315 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1316 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1317 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1318 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1319 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1320 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1321 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1322 1323 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1324 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1325 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1326 1327 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1328 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1329 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1330 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1331 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1332 1333 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1334 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1335 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1336 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1337 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1338 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1339 1340 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1341 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1342 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1343 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1344 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1345 1346 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1347 1348 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1349 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1350 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1351 1352 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1353 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1354 1355 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1356 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1357 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1358 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1359 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1360 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1361 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1362 }; 1363 1364 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1365 1366 static pmc_value_t 1367 iap_perfctr_value_to_reload_count(pmc_value_t v) 1368 { 1369 v &= (1ULL << core_iap_width) - 1; 1370 return (1ULL << core_iap_width) - v; 1371 } 1372 1373 static pmc_value_t 1374 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1375 { 1376 return (1ULL << core_iap_width) - rlc; 1377 } 1378 1379 static int 1380 iap_pmc_has_overflowed(int ri) 1381 { 1382 uint64_t v; 1383 1384 /* 1385 * We treat a Core (i.e., Intel architecture v1) PMC as has 1386 * having overflowed if its MSB is zero. 1387 */ 1388 v = rdpmc(ri); 1389 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1390 } 1391 1392 /* 1393 * Check an event against the set of supported architectural events. 1394 * 1395 * Returns 1 if the event is architectural and unsupported on this 1396 * CPU. Returns 0 otherwise. 1397 */ 1398 1399 static int 1400 iap_architectural_event_is_unsupported(enum pmc_event pe) 1401 { 1402 enum core_arch_events ae; 1403 1404 switch (pe) { 1405 case PMC_EV_IAP_EVENT_3CH_00H: 1406 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1407 break; 1408 case PMC_EV_IAP_EVENT_C0H_00H: 1409 ae = CORE_AE_INSTRUCTION_RETIRED; 1410 break; 1411 case PMC_EV_IAP_EVENT_3CH_01H: 1412 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1413 break; 1414 case PMC_EV_IAP_EVENT_2EH_4FH: 1415 ae = CORE_AE_LLC_REFERENCE; 1416 break; 1417 case PMC_EV_IAP_EVENT_2EH_41H: 1418 ae = CORE_AE_LLC_MISSES; 1419 break; 1420 case PMC_EV_IAP_EVENT_C4H_00H: 1421 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1422 break; 1423 case PMC_EV_IAP_EVENT_C5H_00H: 1424 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1425 break; 1426 1427 default: /* Non architectural event. */ 1428 return (0); 1429 } 1430 1431 return ((core_architectural_events & (1 << ae)) == 0); 1432 } 1433 1434 static int 1435 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1436 { 1437 uint32_t mask; 1438 1439 switch (pe) { 1440 /* 1441 * Events valid only on counter 0, 1. 1442 */ 1443 case PMC_EV_IAP_EVENT_40H_01H: 1444 case PMC_EV_IAP_EVENT_40H_02H: 1445 case PMC_EV_IAP_EVENT_40H_04H: 1446 case PMC_EV_IAP_EVENT_40H_08H: 1447 case PMC_EV_IAP_EVENT_40H_0FH: 1448 case PMC_EV_IAP_EVENT_41H_02H: 1449 case PMC_EV_IAP_EVENT_41H_04H: 1450 case PMC_EV_IAP_EVENT_41H_08H: 1451 case PMC_EV_IAP_EVENT_42H_01H: 1452 case PMC_EV_IAP_EVENT_42H_02H: 1453 case PMC_EV_IAP_EVENT_42H_04H: 1454 case PMC_EV_IAP_EVENT_42H_08H: 1455 case PMC_EV_IAP_EVENT_43H_01H: 1456 case PMC_EV_IAP_EVENT_43H_02H: 1457 case PMC_EV_IAP_EVENT_51H_01H: 1458 case PMC_EV_IAP_EVENT_51H_02H: 1459 case PMC_EV_IAP_EVENT_51H_04H: 1460 case PMC_EV_IAP_EVENT_51H_08H: 1461 case PMC_EV_IAP_EVENT_63H_01H: 1462 case PMC_EV_IAP_EVENT_63H_02H: 1463 mask = 0x3; 1464 break; 1465 1466 default: 1467 mask = ~0; /* Any row index is ok. */ 1468 } 1469 1470 return (mask & (1 << ri)); 1471 } 1472 1473 static int 1474 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1475 { 1476 uint32_t mask; 1477 1478 switch (pe) { 1479 /* 1480 * Events valid only on counter 0. 1481 */ 1482 case PMC_EV_IAP_EVENT_60H_01H: 1483 case PMC_EV_IAP_EVENT_60H_02H: 1484 case PMC_EV_IAP_EVENT_60H_04H: 1485 case PMC_EV_IAP_EVENT_60H_08H: 1486 case PMC_EV_IAP_EVENT_B3H_01H: 1487 case PMC_EV_IAP_EVENT_B3H_02H: 1488 case PMC_EV_IAP_EVENT_B3H_04H: 1489 mask = 0x1; 1490 break; 1491 1492 /* 1493 * Events valid only on counter 0, 1. 1494 */ 1495 case PMC_EV_IAP_EVENT_4CH_01H: 1496 case PMC_EV_IAP_EVENT_4EH_01H: 1497 case PMC_EV_IAP_EVENT_4EH_02H: 1498 case PMC_EV_IAP_EVENT_4EH_04H: 1499 case PMC_EV_IAP_EVENT_51H_01H: 1500 case PMC_EV_IAP_EVENT_51H_02H: 1501 case PMC_EV_IAP_EVENT_51H_04H: 1502 case PMC_EV_IAP_EVENT_51H_08H: 1503 case PMC_EV_IAP_EVENT_63H_01H: 1504 case PMC_EV_IAP_EVENT_63H_02H: 1505 mask = 0x3; 1506 break; 1507 1508 default: 1509 mask = ~0; /* Any row index is ok. */ 1510 } 1511 1512 return (mask & (1 << ri)); 1513 } 1514 1515 static int 1516 iap_event_ok_on_counter(enum pmc_event pe, int ri) 1517 { 1518 uint32_t mask; 1519 1520 switch (pe) { 1521 /* 1522 * Events valid only on counter 0. 1523 */ 1524 case PMC_EV_IAP_EVENT_10H_00H: 1525 case PMC_EV_IAP_EVENT_14H_00H: 1526 case PMC_EV_IAP_EVENT_18H_00H: 1527 case PMC_EV_IAP_EVENT_B3H_01H: 1528 case PMC_EV_IAP_EVENT_B3H_02H: 1529 case PMC_EV_IAP_EVENT_B3H_04H: 1530 case PMC_EV_IAP_EVENT_C1H_00H: 1531 case PMC_EV_IAP_EVENT_CBH_01H: 1532 case PMC_EV_IAP_EVENT_CBH_02H: 1533 mask = (1 << 0); 1534 break; 1535 1536 /* 1537 * Events valid only on counter 1. 1538 */ 1539 case PMC_EV_IAP_EVENT_11H_00H: 1540 case PMC_EV_IAP_EVENT_12H_00H: 1541 case PMC_EV_IAP_EVENT_13H_00H: 1542 mask = (1 << 1); 1543 break; 1544 1545 default: 1546 mask = ~0; /* Any row index is ok. */ 1547 } 1548 1549 return (mask & (1 << ri)); 1550 } 1551 1552 static int 1553 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1554 const struct pmc_op_pmcallocate *a) 1555 { 1556 int n, model; 1557 enum pmc_event ev; 1558 struct iap_event_descr *ie; 1559 uint32_t c, caps, config, cpuflag, evsel, mask; 1560 1561 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1562 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1563 KASSERT(ri >= 0 && ri < core_iap_npmc, 1564 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1565 1566 /* check requested capabilities */ 1567 caps = a->pm_caps; 1568 if ((IAP_PMC_CAPS & caps) != caps) 1569 return (EPERM); 1570 1571 ev = pm->pm_event; 1572 1573 if (iap_architectural_event_is_unsupported(ev)) 1574 return (EOPNOTSUPP); 1575 1576 /* 1577 * A small number of events are not supported in all the 1578 * processors based on a given microarchitecture. 1579 */ 1580 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 1581 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 1582 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 1583 return (EINVAL); 1584 } 1585 1586 switch (core_cputype) { 1587 case PMC_CPU_INTEL_COREI7: 1588 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 1589 return (EINVAL); 1590 break; 1591 case PMC_CPU_INTEL_WESTMERE: 1592 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 1593 return (EINVAL); 1594 break; 1595 default: 1596 if (iap_event_ok_on_counter(ev, ri) == 0) 1597 return (EINVAL); 1598 } 1599 1600 /* 1601 * Look for an event descriptor with matching CPU and event id 1602 * fields. 1603 */ 1604 1605 switch (core_cputype) { 1606 default: 1607 case PMC_CPU_INTEL_ATOM: 1608 cpuflag = IAP_F_CA; 1609 break; 1610 case PMC_CPU_INTEL_CORE: 1611 cpuflag = IAP_F_CC; 1612 break; 1613 case PMC_CPU_INTEL_CORE2: 1614 cpuflag = IAP_F_CC2; 1615 break; 1616 case PMC_CPU_INTEL_CORE2EXTREME: 1617 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1618 break; 1619 case PMC_CPU_INTEL_COREI7: 1620 cpuflag = IAP_F_I7; 1621 break; 1622 case PMC_CPU_INTEL_WESTMERE: 1623 cpuflag = IAP_F_WM; 1624 break; 1625 } 1626 1627 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 1628 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 1629 break; 1630 1631 if (n == niap_events) 1632 return (EINVAL); 1633 1634 /* 1635 * A matching event descriptor has been found, so start 1636 * assembling the contents of the event select register. 1637 */ 1638 evsel = ie->iap_evcode; 1639 1640 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 1641 1642 /* 1643 * If the event uses a fixed umask value, reject any umask 1644 * bits set by the user. 1645 */ 1646 if (ie->iap_flags & IAP_F_FM) { 1647 1648 if (IAP_UMASK(config) != 0) 1649 return (EINVAL); 1650 1651 evsel |= (ie->iap_umask << 8); 1652 1653 } else { 1654 1655 /* 1656 * Otherwise, the UMASK value needs to be taken from 1657 * the MD fields of the allocation request. Reject 1658 * requests that specify reserved bits. 1659 */ 1660 1661 mask = 0; 1662 1663 if (ie->iap_umask & IAP_M_CORE) { 1664 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 1665 c != IAP_CORE_THIS) 1666 return (EINVAL); 1667 mask |= IAP_F_CORE; 1668 } 1669 1670 if (ie->iap_umask & IAP_M_AGENT) 1671 mask |= IAP_F_AGENT; 1672 1673 if (ie->iap_umask & IAP_M_PREFETCH) { 1674 1675 if ((c = (config & IAP_F_PREFETCH)) == 1676 IAP_PREFETCH_RESERVED) 1677 return (EINVAL); 1678 1679 mask |= IAP_F_PREFETCH; 1680 } 1681 1682 if (ie->iap_umask & IAP_M_MESI) 1683 mask |= IAP_F_MESI; 1684 1685 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 1686 mask |= IAP_F_SNOOPRESPONSE; 1687 1688 if (ie->iap_umask & IAP_M_SNOOPTYPE) 1689 mask |= IAP_F_SNOOPTYPE; 1690 1691 if (ie->iap_umask & IAP_M_TRANSITION) 1692 mask |= IAP_F_TRANSITION; 1693 1694 /* 1695 * If bits outside of the allowed set of umask bits 1696 * are set, reject the request. 1697 */ 1698 if (config & ~mask) 1699 return (EINVAL); 1700 1701 evsel |= (config & mask); 1702 1703 } 1704 1705 /* 1706 * Only Atom CPUs support the 'ANY' qualifier. 1707 */ 1708 if (core_cputype == PMC_CPU_INTEL_ATOM) 1709 evsel |= (config & IAP_ANY); 1710 else if (config & IAP_ANY) 1711 return (EINVAL); 1712 1713 /* 1714 * Check offcore response configuration. 1715 */ 1716 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 1717 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 1718 ev != PMC_EV_IAP_EVENT_BBH_01H) 1719 return (EINVAL); 1720 if (core_cputype == PMC_CPU_INTEL_COREI7 && 1721 ev == PMC_EV_IAP_EVENT_BBH_01H) 1722 return (EINVAL); 1723 if (a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK) 1724 return (EINVAL); 1725 pm->pm_md.pm_iap.pm_iap_rsp = 1726 a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK; 1727 } 1728 1729 if (caps & PMC_CAP_THRESHOLD) 1730 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 1731 if (caps & PMC_CAP_USER) 1732 evsel |= IAP_USR; 1733 if (caps & PMC_CAP_SYSTEM) 1734 evsel |= IAP_OS; 1735 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 1736 evsel |= (IAP_OS | IAP_USR); 1737 if (caps & PMC_CAP_EDGE) 1738 evsel |= IAP_EDGE; 1739 if (caps & PMC_CAP_INVERT) 1740 evsel |= IAP_INV; 1741 if (caps & PMC_CAP_INTERRUPT) 1742 evsel |= IAP_INT; 1743 1744 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 1745 1746 return (0); 1747 } 1748 1749 static int 1750 iap_config_pmc(int cpu, int ri, struct pmc *pm) 1751 { 1752 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1753 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1754 1755 KASSERT(ri >= 0 && ri < core_iap_npmc, 1756 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1757 1758 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 1759 1760 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 1761 cpu)); 1762 1763 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 1764 1765 return (0); 1766 } 1767 1768 static int 1769 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 1770 { 1771 int error; 1772 struct pmc_hw *phw; 1773 char iap_name[PMC_NAME_MAX]; 1774 1775 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 1776 1777 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 1778 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 1779 NULL)) != 0) 1780 return (error); 1781 1782 pi->pm_class = PMC_CLASS_IAP; 1783 1784 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 1785 pi->pm_enabled = TRUE; 1786 *ppmc = phw->phw_pmc; 1787 } else { 1788 pi->pm_enabled = FALSE; 1789 *ppmc = NULL; 1790 } 1791 1792 return (0); 1793 } 1794 1795 static int 1796 iap_get_config(int cpu, int ri, struct pmc **ppm) 1797 { 1798 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1799 1800 return (0); 1801 } 1802 1803 static int 1804 iap_get_msr(int ri, uint32_t *msr) 1805 { 1806 KASSERT(ri >= 0 && ri < core_iap_npmc, 1807 ("[iap,%d] ri %d out of range", __LINE__, ri)); 1808 1809 *msr = ri; 1810 1811 return (0); 1812 } 1813 1814 static int 1815 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 1816 { 1817 struct pmc *pm; 1818 pmc_value_t tmp; 1819 1820 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1821 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1822 KASSERT(ri >= 0 && ri < core_iap_npmc, 1823 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1824 1825 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1826 1827 KASSERT(pm, 1828 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 1829 ri)); 1830 1831 tmp = rdpmc(ri); 1832 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1833 *v = iap_perfctr_value_to_reload_count(tmp); 1834 else 1835 *v = tmp; 1836 1837 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 1838 ri, *v); 1839 1840 return (0); 1841 } 1842 1843 static int 1844 iap_release_pmc(int cpu, int ri, struct pmc *pm) 1845 { 1846 (void) pm; 1847 1848 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 1849 pm); 1850 1851 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1852 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1853 KASSERT(ri >= 0 && ri < core_iap_npmc, 1854 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1855 1856 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 1857 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 1858 1859 return (0); 1860 } 1861 1862 static int 1863 iap_start_pmc(int cpu, int ri) 1864 { 1865 struct pmc *pm; 1866 uint32_t evsel; 1867 struct core_cpu *cc; 1868 1869 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1870 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1871 KASSERT(ri >= 0 && ri < core_iap_npmc, 1872 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1873 1874 cc = core_pcpu[cpu]; 1875 pm = cc->pc_corepmcs[ri].phw_pmc; 1876 1877 KASSERT(pm, 1878 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 1879 __LINE__, cpu, ri)); 1880 1881 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 1882 1883 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 1884 1885 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 1886 cpu, ri, IAP_EVSEL0 + ri, evsel); 1887 1888 /* Event specific configuration. */ 1889 switch (pm->pm_event) { 1890 case PMC_EV_IAP_EVENT_B7H_01H: 1891 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 1892 break; 1893 case PMC_EV_IAP_EVENT_BBH_01H: 1894 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 1895 break; 1896 default: 1897 break; 1898 } 1899 1900 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 1901 1902 if (core_cputype == PMC_CPU_INTEL_CORE) 1903 return (0); 1904 1905 do { 1906 cc->pc_resync = 0; 1907 cc->pc_globalctrl |= (1ULL << ri); 1908 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1909 } while (cc->pc_resync != 0); 1910 1911 return (0); 1912 } 1913 1914 static int 1915 iap_stop_pmc(int cpu, int ri) 1916 { 1917 struct pmc *pm; 1918 struct core_cpu *cc; 1919 uint64_t msr; 1920 1921 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1922 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1923 KASSERT(ri >= 0 && ri < core_iap_npmc, 1924 ("[core,%d] illegal row index %d", __LINE__, ri)); 1925 1926 cc = core_pcpu[cpu]; 1927 pm = cc->pc_corepmcs[ri].phw_pmc; 1928 1929 KASSERT(pm, 1930 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1931 cpu, ri)); 1932 1933 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 1934 1935 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 1936 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 1937 1938 if (core_cputype == PMC_CPU_INTEL_CORE) 1939 return (0); 1940 1941 msr = 0; 1942 do { 1943 cc->pc_resync = 0; 1944 cc->pc_globalctrl &= ~(1ULL << ri); 1945 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 1946 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1947 } while (cc->pc_resync != 0); 1948 1949 return (0); 1950 } 1951 1952 static int 1953 iap_write_pmc(int cpu, int ri, pmc_value_t v) 1954 { 1955 struct pmc *pm; 1956 struct core_cpu *cc; 1957 1958 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1959 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1960 KASSERT(ri >= 0 && ri < core_iap_npmc, 1961 ("[core,%d] illegal row index %d", __LINE__, ri)); 1962 1963 cc = core_pcpu[cpu]; 1964 pm = cc->pc_corepmcs[ri].phw_pmc; 1965 1966 KASSERT(pm, 1967 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1968 cpu, ri)); 1969 1970 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1971 IAP_PMC0 + ri, v); 1972 1973 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1974 v = iap_reload_count_to_perfctr_value(v); 1975 1976 /* 1977 * Write the new value to the counter. The counter will be in 1978 * a stopped state when the pcd_write() entry point is called. 1979 */ 1980 1981 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 1982 1983 return (0); 1984 } 1985 1986 1987 static void 1988 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 1989 int flags) 1990 { 1991 struct pmc_classdep *pcd; 1992 1993 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 1994 1995 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 1996 1997 /* Remember the set of architectural events supported. */ 1998 core_architectural_events = ~flags; 1999 2000 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2001 2002 pcd->pcd_caps = IAP_PMC_CAPS; 2003 pcd->pcd_class = PMC_CLASS_IAP; 2004 pcd->pcd_num = npmc; 2005 pcd->pcd_ri = md->pmd_npmc; 2006 pcd->pcd_width = pmcwidth; 2007 2008 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2009 pcd->pcd_config_pmc = iap_config_pmc; 2010 pcd->pcd_describe = iap_describe; 2011 pcd->pcd_get_config = iap_get_config; 2012 pcd->pcd_get_msr = iap_get_msr; 2013 pcd->pcd_pcpu_fini = core_pcpu_fini; 2014 pcd->pcd_pcpu_init = core_pcpu_init; 2015 pcd->pcd_read_pmc = iap_read_pmc; 2016 pcd->pcd_release_pmc = iap_release_pmc; 2017 pcd->pcd_start_pmc = iap_start_pmc; 2018 pcd->pcd_stop_pmc = iap_stop_pmc; 2019 pcd->pcd_write_pmc = iap_write_pmc; 2020 2021 md->pmd_npmc += npmc; 2022 } 2023 2024 static int 2025 core_intr(int cpu, struct trapframe *tf) 2026 { 2027 pmc_value_t v; 2028 struct pmc *pm; 2029 struct core_cpu *cc; 2030 int error, found_interrupt, ri; 2031 uint64_t msr; 2032 2033 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2034 TRAPF_USERMODE(tf)); 2035 2036 found_interrupt = 0; 2037 cc = core_pcpu[cpu]; 2038 2039 for (ri = 0; ri < core_iap_npmc; ri++) { 2040 2041 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2042 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2043 continue; 2044 2045 if (!iap_pmc_has_overflowed(ri)) 2046 continue; 2047 2048 found_interrupt = 1; 2049 2050 if (pm->pm_state != PMC_STATE_RUNNING) 2051 continue; 2052 2053 error = pmc_process_interrupt(cpu, pm, tf, 2054 TRAPF_USERMODE(tf)); 2055 2056 v = pm->pm_sc.pm_reloadcount; 2057 v = iaf_reload_count_to_perfctr_value(v); 2058 2059 /* 2060 * Stop the counter, reload it but only restart it if 2061 * the PMC is not stalled. 2062 */ 2063 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2064 wrmsr(IAP_EVSEL0 + ri, msr); 2065 wrmsr(IAP_PMC0 + ri, v); 2066 2067 if (error) 2068 continue; 2069 2070 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2071 IAP_EN)); 2072 } 2073 2074 if (found_interrupt) 2075 lapic_reenable_pmc(); 2076 2077 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2078 &pmc_stats.pm_intr_ignored, 1); 2079 2080 return (found_interrupt); 2081 } 2082 2083 static int 2084 core2_intr(int cpu, struct trapframe *tf) 2085 { 2086 int error, found_interrupt, n; 2087 uint64_t flag, intrstatus, intrenable, msr; 2088 struct pmc *pm; 2089 struct core_cpu *cc; 2090 pmc_value_t v; 2091 2092 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2093 TRAPF_USERMODE(tf)); 2094 2095 /* 2096 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2097 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2098 * the current set of interrupting PMCs and process these 2099 * after stopping them. 2100 */ 2101 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2102 intrenable = intrstatus & core_pmcmask; 2103 2104 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2105 (uintmax_t) intrstatus); 2106 2107 found_interrupt = 0; 2108 cc = core_pcpu[cpu]; 2109 2110 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2111 2112 cc->pc_globalctrl &= ~intrenable; 2113 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2114 2115 /* 2116 * Stop PMCs and clear overflow status bits. 2117 */ 2118 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2119 wrmsr(IA_GLOBAL_CTRL, msr); 2120 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2121 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2122 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2123 2124 /* 2125 * Look for interrupts from fixed function PMCs. 2126 */ 2127 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2128 n++, flag <<= 1) { 2129 2130 if ((intrstatus & flag) == 0) 2131 continue; 2132 2133 found_interrupt = 1; 2134 2135 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2136 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2137 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2138 continue; 2139 2140 error = pmc_process_interrupt(cpu, pm, tf, 2141 TRAPF_USERMODE(tf)); 2142 if (error) 2143 intrenable &= ~flag; 2144 2145 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2146 2147 /* Reload sampling count. */ 2148 wrmsr(IAF_CTR0 + n, v); 2149 2150 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 2151 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2152 } 2153 2154 /* 2155 * Process interrupts from the programmable counters. 2156 */ 2157 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2158 if ((intrstatus & flag) == 0) 2159 continue; 2160 2161 found_interrupt = 1; 2162 2163 pm = cc->pc_corepmcs[n].phw_pmc; 2164 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2165 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2166 continue; 2167 2168 error = pmc_process_interrupt(cpu, pm, tf, 2169 TRAPF_USERMODE(tf)); 2170 if (error) 2171 intrenable &= ~flag; 2172 2173 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2174 2175 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2176 (uintmax_t) v); 2177 2178 /* Reload sampling count. */ 2179 wrmsr(IAP_PMC0 + n, v); 2180 } 2181 2182 /* 2183 * Reenable all non-stalled PMCs. 2184 */ 2185 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2186 (uintmax_t) intrenable); 2187 2188 cc->pc_globalctrl |= intrenable; 2189 2190 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2191 2192 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2193 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2194 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2195 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2196 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2197 2198 if (found_interrupt) 2199 lapic_reenable_pmc(); 2200 2201 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2202 &pmc_stats.pm_intr_ignored, 1); 2203 2204 return (found_interrupt); 2205 } 2206 2207 int 2208 pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 2209 { 2210 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2211 int ipa_version, flags, nflags; 2212 2213 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2214 2215 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 2216 2217 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2218 md->pmd_cputype, maxcpu, ipa_version); 2219 2220 if (ipa_version < 1 || ipa_version > 3) /* Unknown PMC architecture. */ 2221 return (EPROGMISMATCH); 2222 2223 core_cputype = md->pmd_cputype; 2224 2225 core_pmcmask = 0; 2226 2227 /* 2228 * Initialize programmable counters. 2229 */ 2230 KASSERT(ipa_version >= 1, 2231 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 2232 2233 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2234 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2235 2236 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2237 2238 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2239 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2240 2241 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2242 2243 /* 2244 * Initialize fixed function counters, if present. 2245 */ 2246 if (core_cputype != PMC_CPU_INTEL_CORE) { 2247 KASSERT(ipa_version >= 2, 2248 ("[core,%d] ipa_version %d too small", __LINE__, 2249 ipa_version)); 2250 2251 core_iaf_ri = core_iap_npmc; 2252 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2253 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2254 2255 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2256 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2257 } 2258 2259 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2260 core_iaf_ri); 2261 2262 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 2263 M_ZERO | M_WAITOK); 2264 2265 /* 2266 * Choose the appropriate interrupt handler. 2267 */ 2268 if (ipa_version == 1) 2269 md->pmd_intr = core_intr; 2270 else 2271 md->pmd_intr = core2_intr; 2272 2273 md->pmd_pcpu_fini = NULL; 2274 md->pmd_pcpu_init = NULL; 2275 2276 return (0); 2277 } 2278 2279 void 2280 pmc_core_finalize(struct pmc_mdep *md) 2281 { 2282 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2283 2284 free(core_pcpu, M_PMC); 2285 core_pcpu = NULL; 2286 } 2287