1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #if (__FreeBSD_version >= 1100000) 42 #include <x86/apicvar.h> 43 #else 44 #include <machine/apicvar.h> 45 #endif 46 #include <machine/cpu.h> 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #define CORE_CPUID_REQUEST 0xA 52 #define CORE_CPUID_REQUEST_SIZE 0x4 53 #define CORE_CPUID_EAX 0x0 54 #define CORE_CPUID_EBX 0x1 55 #define CORE_CPUID_ECX 0x2 56 #define CORE_CPUID_EDX 0x3 57 58 #define IAF_PMC_CAPS \ 59 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 60 PMC_CAP_USER | PMC_CAP_SYSTEM) 61 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 62 63 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 64 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 65 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 66 67 #define EV_IS_NOTARCH 0 68 #define EV_IS_ARCH_SUPP 1 69 #define EV_IS_ARCH_NOTSUPP -1 70 71 /* 72 * "Architectural" events defined by Intel. The values of these 73 * symbols correspond to positions in the bitmask returned by 74 * the CPUID.0AH instruction. 75 */ 76 enum core_arch_events { 77 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 78 CORE_AE_BRANCH_MISSES_RETIRED = 6, 79 CORE_AE_INSTRUCTION_RETIRED = 1, 80 CORE_AE_LLC_MISSES = 4, 81 CORE_AE_LLC_REFERENCE = 3, 82 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 83 CORE_AE_UNHALTED_CORE_CYCLES = 0 84 }; 85 86 static enum pmc_cputype core_cputype; 87 88 struct core_cpu { 89 volatile uint32_t pc_resync; 90 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 91 volatile uint64_t pc_globalctrl; /* Global control register. */ 92 struct pmc_hw pc_corepmcs[]; 93 }; 94 95 static struct core_cpu **core_pcpu; 96 97 static uint32_t core_architectural_events; 98 static uint64_t core_pmcmask; 99 100 static int core_iaf_ri; /* relative index of fixed counters */ 101 static int core_iaf_width; 102 static int core_iaf_npmc; 103 104 static int core_iap_width; 105 static int core_iap_npmc; 106 static int core_iap_wroffset; 107 108 static int 109 core_pcpu_noop(struct pmc_mdep *md, int cpu) 110 { 111 (void) md; 112 (void) cpu; 113 return (0); 114 } 115 116 static int 117 core_pcpu_init(struct pmc_mdep *md, int cpu) 118 { 119 struct pmc_cpu *pc; 120 struct core_cpu *cc; 121 struct pmc_hw *phw; 122 int core_ri, n, npmc; 123 124 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 125 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 126 127 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu); 128 129 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 130 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 131 132 if (core_cputype != PMC_CPU_INTEL_CORE) 133 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 134 135 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 136 M_PMC, M_WAITOK | M_ZERO); 137 138 core_pcpu[cpu] = cc; 139 pc = pmc_pcpu[cpu]; 140 141 KASSERT(pc != NULL && cc != NULL, 142 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 143 144 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 145 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 146 PMC_PHW_CPU_TO_STATE(cpu) | 147 PMC_PHW_INDEX_TO_STATE(n + core_ri); 148 phw->phw_pmc = NULL; 149 pc->pc_hwpmcs[n + core_ri] = phw; 150 } 151 152 return (0); 153 } 154 155 static int 156 core_pcpu_fini(struct pmc_mdep *md, int cpu) 157 { 158 int core_ri, n, npmc; 159 struct pmc_cpu *pc; 160 struct core_cpu *cc; 161 uint64_t msr = 0; 162 163 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 164 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 165 166 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 167 168 if ((cc = core_pcpu[cpu]) == NULL) 169 return (0); 170 171 core_pcpu[cpu] = NULL; 172 173 pc = pmc_pcpu[cpu]; 174 175 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 176 cpu)); 177 178 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 179 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 180 181 for (n = 0; n < npmc; n++) { 182 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 183 wrmsr(IAP_EVSEL0 + n, msr); 184 } 185 186 if (core_cputype != PMC_CPU_INTEL_CORE) { 187 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 188 wrmsr(IAF_CTRL, msr); 189 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 190 } 191 192 for (n = 0; n < npmc; n++) 193 pc->pc_hwpmcs[n + core_ri] = NULL; 194 195 free(cc, M_PMC); 196 197 return (0); 198 } 199 200 /* 201 * Fixed function counters. 202 */ 203 204 static pmc_value_t 205 iaf_perfctr_value_to_reload_count(pmc_value_t v) 206 { 207 208 /* If the PMC has overflowed, return a reload count of zero. */ 209 if ((v & (1ULL << (core_iaf_width - 1))) == 0) 210 return (0); 211 v &= (1ULL << core_iaf_width) - 1; 212 return (1ULL << core_iaf_width) - v; 213 } 214 215 static pmc_value_t 216 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 217 { 218 return (1ULL << core_iaf_width) - rlc; 219 } 220 221 static int 222 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 223 const struct pmc_op_pmcallocate *a) 224 { 225 enum pmc_event ev; 226 uint32_t caps, flags, validflags; 227 228 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 229 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 230 231 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 232 233 if (ri < 0 || ri > core_iaf_npmc) 234 return (EINVAL); 235 236 caps = a->pm_caps; 237 238 if (a->pm_class != PMC_CLASS_IAF || 239 (caps & IAF_PMC_CAPS) != caps) 240 return (EINVAL); 241 242 ev = pm->pm_event; 243 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 244 return (EINVAL); 245 246 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 247 return (EINVAL); 248 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 249 return (EINVAL); 250 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 251 return (EINVAL); 252 253 flags = a->pm_md.pm_iaf.pm_iaf_flags; 254 255 validflags = IAF_MASK; 256 257 if (core_cputype != PMC_CPU_INTEL_ATOM && 258 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 259 validflags &= ~IAF_ANY; 260 261 if ((flags & ~validflags) != 0) 262 return (EINVAL); 263 264 if (caps & PMC_CAP_INTERRUPT) 265 flags |= IAF_PMI; 266 if (caps & PMC_CAP_SYSTEM) 267 flags |= IAF_OS; 268 if (caps & PMC_CAP_USER) 269 flags |= IAF_USR; 270 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 271 flags |= (IAF_OS | IAF_USR); 272 273 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 274 275 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx", 276 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 277 278 return (0); 279 } 280 281 static int 282 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 283 { 284 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 285 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 286 287 KASSERT(ri >= 0 && ri < core_iaf_npmc, 288 ("[core,%d] illegal row-index %d", __LINE__, ri)); 289 290 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 291 292 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 293 cpu)); 294 295 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 296 297 return (0); 298 } 299 300 static int 301 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 302 { 303 int error; 304 struct pmc_hw *phw; 305 char iaf_name[PMC_NAME_MAX]; 306 307 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 308 309 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 310 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 311 NULL)) != 0) 312 return (error); 313 314 pi->pm_class = PMC_CLASS_IAF; 315 316 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 317 pi->pm_enabled = TRUE; 318 *ppmc = phw->phw_pmc; 319 } else { 320 pi->pm_enabled = FALSE; 321 *ppmc = NULL; 322 } 323 324 return (0); 325 } 326 327 static int 328 iaf_get_config(int cpu, int ri, struct pmc **ppm) 329 { 330 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 331 332 return (0); 333 } 334 335 static int 336 iaf_get_msr(int ri, uint32_t *msr) 337 { 338 KASSERT(ri >= 0 && ri < core_iaf_npmc, 339 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 340 341 *msr = IAF_RI_TO_MSR(ri); 342 343 return (0); 344 } 345 346 static int 347 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 348 { 349 struct pmc *pm; 350 pmc_value_t tmp; 351 352 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 353 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 354 KASSERT(ri >= 0 && ri < core_iaf_npmc, 355 ("[core,%d] illegal row-index %d", __LINE__, ri)); 356 357 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 358 359 KASSERT(pm, 360 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 361 ri, ri + core_iaf_ri)); 362 363 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 364 365 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 366 *v = iaf_perfctr_value_to_reload_count(tmp); 367 else 368 *v = tmp & ((1ULL << core_iaf_width) - 1); 369 370 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 371 IAF_RI_TO_MSR(ri), *v); 372 373 return (0); 374 } 375 376 static int 377 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 378 { 379 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 380 381 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 382 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 383 KASSERT(ri >= 0 && ri < core_iaf_npmc, 384 ("[core,%d] illegal row-index %d", __LINE__, ri)); 385 386 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 387 ("[core,%d] PHW pmc non-NULL", __LINE__)); 388 389 return (0); 390 } 391 392 static int 393 iaf_start_pmc(int cpu, int ri) 394 { 395 struct pmc *pm; 396 struct core_cpu *iafc; 397 uint64_t msr = 0; 398 399 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 400 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 401 KASSERT(ri >= 0 && ri < core_iaf_npmc, 402 ("[core,%d] illegal row-index %d", __LINE__, ri)); 403 404 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 405 406 iafc = core_pcpu[cpu]; 407 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 408 409 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 410 411 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 412 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 413 414 do { 415 iafc->pc_resync = 0; 416 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 417 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 418 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 419 IAF_GLOBAL_CTRL_MASK)); 420 } while (iafc->pc_resync != 0); 421 422 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 423 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 424 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 425 426 return (0); 427 } 428 429 static int 430 iaf_stop_pmc(int cpu, int ri) 431 { 432 uint32_t fc; 433 struct core_cpu *iafc; 434 uint64_t msr = 0; 435 436 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 437 438 iafc = core_pcpu[cpu]; 439 440 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 441 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 442 KASSERT(ri >= 0 && ri < core_iaf_npmc, 443 ("[core,%d] illegal row-index %d", __LINE__, ri)); 444 445 fc = (IAF_MASK << (ri * 4)); 446 447 if (core_cputype != PMC_CPU_INTEL_ATOM && 448 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 449 fc &= ~IAF_ANY; 450 451 iafc->pc_iafctrl &= ~fc; 452 453 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 454 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 455 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 456 457 do { 458 iafc->pc_resync = 0; 459 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 460 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 461 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 462 IAF_GLOBAL_CTRL_MASK)); 463 } while (iafc->pc_resync != 0); 464 465 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 466 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 467 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 468 469 return (0); 470 } 471 472 static int 473 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 474 { 475 struct core_cpu *cc; 476 struct pmc *pm; 477 uint64_t msr; 478 479 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 480 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 481 KASSERT(ri >= 0 && ri < core_iaf_npmc, 482 ("[core,%d] illegal row-index %d", __LINE__, ri)); 483 484 cc = core_pcpu[cpu]; 485 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 486 487 KASSERT(pm, 488 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 489 490 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 491 v = iaf_reload_count_to_perfctr_value(v); 492 493 /* Turn off fixed counters */ 494 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 495 wrmsr(IAF_CTRL, msr); 496 497 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 498 499 /* Turn on fixed counters */ 500 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 501 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 502 503 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 504 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 505 (uintmax_t) rdmsr(IAF_CTRL), 506 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 507 508 return (0); 509 } 510 511 512 static void 513 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 514 { 515 struct pmc_classdep *pcd; 516 517 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 518 519 PMCDBG0(MDP,INI,1, "iaf-initialize"); 520 521 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 522 523 pcd->pcd_caps = IAF_PMC_CAPS; 524 pcd->pcd_class = PMC_CLASS_IAF; 525 pcd->pcd_num = npmc; 526 pcd->pcd_ri = md->pmd_npmc; 527 pcd->pcd_width = pmcwidth; 528 529 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 530 pcd->pcd_config_pmc = iaf_config_pmc; 531 pcd->pcd_describe = iaf_describe; 532 pcd->pcd_get_config = iaf_get_config; 533 pcd->pcd_get_msr = iaf_get_msr; 534 pcd->pcd_pcpu_fini = core_pcpu_noop; 535 pcd->pcd_pcpu_init = core_pcpu_noop; 536 pcd->pcd_read_pmc = iaf_read_pmc; 537 pcd->pcd_release_pmc = iaf_release_pmc; 538 pcd->pcd_start_pmc = iaf_start_pmc; 539 pcd->pcd_stop_pmc = iaf_stop_pmc; 540 pcd->pcd_write_pmc = iaf_write_pmc; 541 542 md->pmd_npmc += npmc; 543 } 544 545 /* 546 * Intel programmable PMCs. 547 */ 548 549 /* 550 * Event descriptor tables. 551 * 552 * For each event id, we track: 553 * 554 * 1. The CPUs that the event is valid for. 555 * 556 * 2. If the event uses a fixed UMASK, the value of the umask field. 557 * If the event doesn't use a fixed UMASK, a mask of legal bits 558 * to check against. 559 */ 560 561 struct iap_event_descr { 562 enum pmc_event iap_ev; 563 unsigned char iap_evcode; 564 unsigned char iap_umask; 565 unsigned int iap_flags; 566 }; 567 568 #define IAP_F_CC (1 << 0) /* CPU: Core */ 569 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 570 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 571 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 572 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 573 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 574 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 575 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 576 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 577 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 578 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ 579 #define IAP_F_HW (1 << 10) /* CPU: Haswell */ 580 #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ 581 #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ 582 #define IAP_F_BW (1 << 13) /* CPU: Broadwell */ 583 #define IAP_F_BWX (1 << 14) /* CPU: Broadwell Xeon */ 584 #define IAP_F_SL (1 << 15) /* CPU: Skylake */ 585 #define IAP_F_SLX (1 << 16) /* CPU: Skylake Xeon AKA scalable */ 586 #define IAP_F_FM (1 << 18) /* Fixed mask */ 587 588 #define IAP_F_ALLCPUSCORE2 \ 589 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 590 591 /* Sub fields of UMASK that this event supports. */ 592 #define IAP_M_CORE (1 << 0) /* Core specificity */ 593 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 594 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 595 #define IAP_M_MESI (1 << 3) /* MESI */ 596 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 597 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 598 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 599 600 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 601 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 602 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 603 #define IAP_F_MESI (0xF << 8) /* MESI */ 604 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 605 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 606 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 607 608 #define IAP_PREFETCH_RESERVED (0x2 << 12) 609 #define IAP_CORE_THIS (0x1 << 14) 610 #define IAP_CORE_ALL (0x3 << 14) 611 #define IAP_F_CMASK 0xFF000000 612 613 static struct iap_event_descr iap_events[] = { 614 #undef IAPDESCR 615 #define IAPDESCR(N,EV,UM,FLAGS) { \ 616 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 617 .iap_evcode = (EV), \ 618 .iap_umask = (UM), \ 619 .iap_flags = (FLAGS) \ 620 } 621 622 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 623 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 624 625 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 626 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 627 IAP_F_SBX | IAP_F_CAS), 628 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 629 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 630 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 631 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 632 IAP_F_CAS), 633 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 634 IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 635 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 636 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 637 IAP_F_SBX | IAP_F_CAS), 638 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 639 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_FM | IAP_F_CAS), 640 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_FM | IAP_F_CAS), 641 642 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), 643 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 644 IAP_F_CAS), 645 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 646 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_FM | IAP_F_CAS), 647 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 648 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 649 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_FM | IAP_F_CAS), 650 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_FM | IAP_F_CAS), 651 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_FM | IAP_F_CAS), 652 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_FM | IAP_F_CAS), 653 654 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 655 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 656 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | 657 IAP_F_BWX), 658 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | 659 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | 660 IAP_F_BW | IAP_F_BWX), 661 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), 662 663 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 664 IAP_F_CC2E | IAP_F_CA), 665 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 666 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 667 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 668 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 669 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 670 671 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 672 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 673 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 674 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 675 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 676 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 677 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 678 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 679 IAP_F_SBX), 680 681 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 682 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | 683 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 684 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 685 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | 686 IAP_F_BW | IAP_F_BWX | IAP_F_SLX), 687 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 688 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_SLX), 689 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 690 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 691 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 692 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SLX), 693 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 694 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 695 IAP_F_SLX), 696 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 697 IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 698 IAP_F_SLX), 699 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 700 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 701 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 702 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 703 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 704 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 705 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 706 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 707 IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 708 709 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 710 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 711 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 712 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 713 714 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 715 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 716 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 717 718 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 719 IAP_F_WM | IAP_F_SL), 720 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 721 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 722 723 IAPDESCR(0DH_01H, 0x0D, 0x80, IAP_F_FM | IAP_F_SLX), 724 IAPDESCR(0DH_03H, 0x0D, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | 725 IAP_F_IB | IAP_F_IBX | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 726 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 727 IAPDESCR(0DH_80H, 0x0D, 0x80, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 728 729 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 730 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 731 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 732 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SL | 733 IAP_F_SLX), 734 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 735 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 736 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 737 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 738 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 739 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 740 741 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 742 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 743 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 744 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 745 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 746 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 747 748 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 749 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 750 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ), 751 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 752 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 753 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 754 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 755 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 756 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 757 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 758 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 759 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 760 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 761 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 762 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 763 764 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 765 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 766 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 767 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 768 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 769 770 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 771 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 772 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 773 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 774 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 775 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 776 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 777 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 778 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 779 780 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 781 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 782 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 783 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 784 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 785 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 786 787 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 788 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 789 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 790 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 791 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 792 793 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 794 IAP_F_SBX), 795 796 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 797 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 798 799 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 800 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 801 IAP_F_I7 | IAP_F_WM), 802 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 803 804 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 805 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 806 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 807 808 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 809 810 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 811 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 812 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 813 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 814 815 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 816 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 817 IAP_F_IB | IAP_F_SBX | IAP_F_IBX ), 818 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 819 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 820 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 821 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 822 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 823 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 824 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 825 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 826 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 827 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 828 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 829 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 830 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 831 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 832 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 833 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 834 IAP_F_SLX), 835 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 836 IAP_F_SLX), 837 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 838 IAP_F_SLX), 839 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 840 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 841 IAP_F_BW | IAP_F_BWX), 842 IAPDESCR(24H_38H, 0x24, 0x38, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 843 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 844 IAP_F_SLX), 845 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 846 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 847 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 848 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 849 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 850 IAP_F_SLX), 851 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 852 IAP_F_SLX), 853 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 854 IAP_F_BW | IAP_F_BWX), 855 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 856 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 857 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 858 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 859 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 860 IAPDESCR(24H_D8H, 0x24, 0xD8, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 861 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 862 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 863 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 864 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 865 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 866 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 867 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 868 IAP_F_SLX), 869 IAPDESCR(24H_EFH, 0x24, 0xEF, IAP_F_FM | IAP_F_SL), 870 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 871 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 872 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 873 IAP_F_HWX | IAP_F_SLX), 874 875 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 876 877 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 878 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 879 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 880 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 881 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 882 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 883 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 884 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 885 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 886 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 887 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 888 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 889 890 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 891 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 892 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 893 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 894 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 895 IAP_F_SBX), 896 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 897 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 898 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 899 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 900 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 901 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 902 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 903 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 904 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 905 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 906 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 907 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 908 909 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 910 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 911 IAP_F_SBX | IAP_F_IBX), 912 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 913 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 914 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 915 IAPDESCR(28H_07H, 0x28, 0x07, IAP_F_FM | IAP_F_SLX), 916 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 917 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 918 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 919 IAP_F_SBX | IAP_F_IBX), 920 IAPDESCR(28H_18H, 0x28, 0x18, IAP_F_SLX), 921 IAPDESCR(28H_20H, 0x28, 0x20, IAP_F_SLX), 922 IAPDESCR(28H_40H, 0x28, 0x40, IAP_F_SLX), 923 924 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 925 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 926 IAP_F_CA | IAP_F_CC2), 927 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 928 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 929 930 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 931 IAP_F_ALLCPUSCORE2), 932 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 933 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 934 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 935 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 936 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 937 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 938 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 939 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 940 941 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 942 IAP_F_ALLCPUSCORE2), 943 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_FM | IAP_F_CAS), 944 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_FM | IAP_F_CAS), 945 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 946 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 947 948 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 949 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 950 951 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 952 953 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 954 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 955 IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 956 IAP_F_SLX), 957 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 958 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 959 IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 960 IAP_F_SLX), 961 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_SL | 962 IAP_F_SLX), 963 964 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 965 966 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 967 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 968 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 969 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 970 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 971 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 972 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 973 974 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 975 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 976 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 977 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 978 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 979 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 980 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 981 982 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 983 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 984 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 985 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 986 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 987 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 988 989 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 990 IAP_F_I7), 991 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 992 IAP_F_CC2 | IAP_F_I7), 993 994 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 995 996 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 997 998 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 999 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1000 1001 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1002 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1003 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1004 IAP_F_SL | IAP_F_SLX), 1005 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_SL | IAP_F_SLX), 1006 1007 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 1008 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1009 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 1010 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1011 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1012 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 1013 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SLX), 1014 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 1015 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SLX), 1016 IAPDESCR(49H_08H, 0x49, 0x08, IAP_F_FM | IAP_F_SLX), 1017 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 1018 IAP_F_SLX), 1019 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1020 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1021 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1022 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX | 1023 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1024 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1025 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1026 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | 1027 IAP_F_HWX), 1028 1029 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1030 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 1031 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1032 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 1033 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 1034 1035 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1036 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1037 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1038 IAP_F_SL | IAP_F_SLX), 1039 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1040 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1041 1042 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 1043 1044 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1045 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1046 IAP_F_SB | IAP_F_SBX), 1047 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1048 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1049 1050 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 1051 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 1052 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 1053 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 1054 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_BW | IAP_F_BWX | 1055 IAP_F_SL | IAP_F_SLX), 1056 1057 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1058 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1059 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1060 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1061 IAP_F_SB | IAP_F_SBX), 1062 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1063 IAP_F_SB | IAP_F_SBX), 1064 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1065 IAP_F_SB | IAP_F_SBX), 1066 1067 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1068 1069 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1070 1071 IAPDESCR(54H_01H, 0x54, 0x01, IAP_F_FM | IAP_F_SLX), 1072 IAPDESCR(54H_02H, 0x54, 0x02, IAP_F_FM | IAP_F_SLX), 1073 IAPDESCR(54H_04H, 0x54, 0x04, IAP_F_FM | IAP_F_SLX), 1074 IAPDESCR(54H_08H, 0x54, 0x08, IAP_F_FM | IAP_F_SLX), 1075 IAPDESCR(54H_10H, 0x54, 0x10, IAP_F_FM | IAP_F_SLX), 1076 IAPDESCR(54H_20H, 0x54, 0x20, IAP_F_FM | IAP_F_SLX), 1077 IAPDESCR(54H_40H, 0x54, 0x40, IAP_F_FM | IAP_F_SLX), 1078 1079 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1080 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1081 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1082 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1083 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1084 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1085 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1086 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1087 1088 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1089 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1090 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1091 1092 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1093 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1094 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1095 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1096 1097 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1098 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1099 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1100 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1101 1102 IAPDESCR(5DH_01H, 0x5d, 0x01, IAP_F_FM | IAP_F_SLX), 1103 IAPDESCR(5DH_02H, 0x5d, 0x02, IAP_F_FM | IAP_F_SLX), 1104 IAPDESCR(5DH_04H, 0x5d, 0x04, IAP_F_FM | IAP_F_SLX), 1105 IAPDESCR(5DH_08H, 0x5d, 0x08, IAP_F_FM | IAP_F_SLX), 1106 IAPDESCR(5DH_10H, 0x5d, 0x10, IAP_F_FM | IAP_F_SLX), 1107 1108 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1109 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1110 IAP_F_SL | IAP_F_SLX), 1111 1112 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */ 1113 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_FM | IAP_F_IBX | IAP_F_IB), 1114 1115 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1116 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1117 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1118 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1119 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1120 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1121 IAP_F_SLX), 1122 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM |IAP_F_I7O | 1123 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1124 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1125 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM |IAP_F_I7O | 1126 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1127 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1128 IAPDESCR(60H_10H, 0x60, 0x10, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1129 1130 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1131 1132 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1133 1134 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1135 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1136 1137 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1138 IAP_F_CA | IAP_F_CC2), 1139 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1140 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1141 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1142 IAP_F_BW | IAP_F_BWX ), 1143 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1144 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1145 IAP_F_BW | IAP_F_BWX), 1146 1147 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1148 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1149 1150 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1151 IAP_F_CA | IAP_F_CC2), 1152 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1153 1154 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1155 1156 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1157 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1158 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1159 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1160 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1161 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1162 1163 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1164 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1165 1166 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1167 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1168 1169 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1170 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1171 1172 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1173 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1174 1175 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1176 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1177 1178 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1179 IAP_F_CA | IAP_F_CC2), 1180 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1181 1182 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1183 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1184 1185 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1186 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1187 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1188 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1189 IAP_F_SL | IAP_F_SLX), 1190 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1191 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_BW | 1192 IAP_F_BWX | IAP_F_SLX), 1193 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1194 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1195 IAP_F_SL | IAP_F_SLX), 1196 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1197 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1198 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1199 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1200 IAP_F_SL | IAP_F_SLX), 1201 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1202 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1203 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1204 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1205 IAP_F_SL | IAP_F_SLX), 1206 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1207 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1208 1209 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1210 1211 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1212 1213 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1214 1215 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1216 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1217 1218 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1219 1220 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1221 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1222 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1223 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1224 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1225 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1226 IAP_F_WM | IAP_F_CAS), 1227 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1228 IAP_F_IBX | IAP_F_SL | IAP_F_SLX), /* SL may have a spec bug two with 1229 same entry no cmask */ 1230 1231 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1232 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1233 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1234 1235 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1236 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1237 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1238 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1239 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1240 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1241 1242 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SL | IAP_F_SLX), 1243 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SL | 1244 IAP_F_SLX), 1245 IAPDESCR(83H_04H, 0x83, 0x04, IAP_F_FM | IAP_F_SLX), 1246 1247 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1248 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1249 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1250 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1251 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1252 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1253 IAP_F_BW | IAP_F_BWX | IAP_F_SLX), 1254 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1255 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1256 IAP_F_SLX), 1257 IAPDESCR(85H_08H, 0x85, 0x08, IAP_F_FM | IAP_F_SLX), 1258 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 1259 IAP_F_SLX), 1260 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1261 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1262 IAP_F_SL | IAP_F_SLX), 1263 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX | 1264 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1265 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1266 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1267 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1268 1269 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1270 1271 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1272 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1273 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1274 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1275 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1276 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1277 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1278 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1279 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1280 1281 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1282 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1283 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1284 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1285 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1286 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1287 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1288 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1289 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1290 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1291 IAPDESCR(88H_41H, 0x88, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1292 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1293 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1294 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_BW | IAP_F_BWX), 1295 IAPDESCR(88H_81H, 0x88, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1296 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1297 IAPDESCR(88H_82H, 0x88, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1298 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1299 IAPDESCR(88H_84H, 0x88, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1300 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1301 IAPDESCR(88H_88H, 0x88, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1302 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1303 IAPDESCR(88H_90H, 0x88, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1304 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1305 IAPDESCR(88H_A0H, 0x88, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1306 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1307 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1308 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1309 1310 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1311 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1312 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1313 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1314 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1315 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1316 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1317 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1318 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1319 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1320 IAPDESCR(89H_41H, 0x89, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1321 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1322 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1323 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_BW | IAP_F_BWX), 1324 IAPDESCR(89H_81H, 0x89, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1325 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1326 IAPDESCR(89H_82H, 0x89, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1327 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1328 IAPDESCR(89H_84H, 0x89, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1329 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1330 IAPDESCR(89H_88H, 0x89, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1331 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1332 IAPDESCR(89H_90H, 0x89, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1333 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1334 IAPDESCR(89H_A0H, 0x89, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1335 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1336 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1337 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1338 1339 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1340 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1341 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1342 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1343 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1344 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1345 1346 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1347 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1348 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1349 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1350 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1351 1352 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1353 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1354 1355 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1356 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1357 IAP_F_SL | IAP_F_SLX), 1358 1359 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1360 1361 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1362 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1363 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1364 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1365 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1366 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1367 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1368 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1369 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1370 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1371 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1372 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1373 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1374 IAP_F_SBX | IAP_F_IBX), 1375 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1376 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1377 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1378 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1379 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1380 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1381 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1382 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1383 IAP_F_SL | IAP_F_SLX), 1384 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1385 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1386 IAP_F_SL | IAP_F_SLX), 1387 1388 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1389 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1390 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1391 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1392 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1393 IAP_F_SB | IAP_F_SBX), 1394 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1395 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1396 IAP_F_BW | IAP_F_BWX), 1397 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1398 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1399 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1400 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1401 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1402 IAP_F_BW | IAP_F_BWX), 1403 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1404 IAP_F_SB | IAP_F_SBX), 1405 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1406 IAP_F_SB | IAP_F_SBX), 1407 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1408 IAP_F_SB | IAP_F_SBX), 1409 1410 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1411 IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_SLX), 1412 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1413 IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_SLX), 1414 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1415 IAP_F_SL | IAP_F_SLX), 1416 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL | 1417 IAP_F_SLX), 1418 IAPDESCR(A3H_06H, 0xA3, 0x06, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1419 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | 1420 IAP_F_HWX | IAP_F_SL | IAP_F_SLX), 1421 IAPDESCR(A3H_0CH, 0xA3, 0x0C, IAP_F_FM | IAP_F_HW | IAP_F_HW | IAP_F_SL | 1422 IAP_F_SLX), 1423 IAPDESCR(A3H_10H, 0xA3, 0x10, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1424 IAPDESCR(A3H_14H, 0xA3, 0x14, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1425 1426 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SL | 1427 IAP_F_SLX), 1428 IAPDESCR(A6H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1429 IAPDESCR(A6H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1430 IAPDESCR(A6H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1431 IAPDESCR(A6H_10H, 0xA3, 0x10, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1432 IAPDESCR(A6H_40H, 0xA3, 0x40, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1433 1434 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM ), 1435 1436 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX | 1437 IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1438 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1439 1440 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1441 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1442 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1443 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1444 1445 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1446 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1447 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1448 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_BW | IAP_F_BWX | 1449 IAP_F_SLX), 1450 1451 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_SL), 1452 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1453 IAP_F_SBX | IAP_F_IBX), 1454 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1455 1456 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1457 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1458 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1459 1460 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1461 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1462 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1463 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1464 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1465 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1466 IAP_F_SLX), 1467 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1468 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1469 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1470 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1471 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1472 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1473 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SL | 1474 IAP_F_SLX), 1475 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1476 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1477 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O | 1478 IAP_F_SL | IAP_F_SLX), 1479 1480 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1481 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1482 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_BW | IAP_F_BWX | 1483 IAP_F_SL | IAP_F_SLX), 1484 IAPDESCR(B1H_02H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1485 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1486 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1487 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1488 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1489 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SLX), 1490 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1491 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1492 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1493 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1494 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1495 IAP_F_WM), 1496 1497 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1498 IAP_F_SB | IAP_F_SBX | IAP_F_SLX), 1499 1500 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1501 IAP_F_WM | IAP_F_I7O), 1502 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1503 IAP_F_WM | IAP_F_I7O), 1504 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1505 IAP_F_WM | IAP_F_I7O), 1506 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1507 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1508 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1509 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1510 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1511 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1512 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1513 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1514 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1515 1516 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1517 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1518 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1519 1520 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1521 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_FM | IAP_F_CAS), 1522 1523 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1524 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | 1525 IAP_F_HWX |IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1526 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), 1527 1528 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1529 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1530 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1531 1532 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1533 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1534 1535 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1536 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1537 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1538 1539 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1540 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1541 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1542 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1543 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1544 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1545 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1546 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1547 1548 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1549 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_SLX), /* spec bug SL? */ 1550 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1551 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SLX), 1552 1553 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1554 1555 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1556 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1557 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1558 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1559 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1560 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1561 IAP_F_SLX), 1562 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1563 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_BW | IAP_F_BWX), 1564 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1565 IAP_F_I7 | IAP_F_WM), 1566 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1567 1568 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1569 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1570 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1571 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1572 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1573 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1574 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1575 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1576 IAP_F_SBX | IAP_F_IBX), 1577 IAPDESCR(C1H_3FH, 0xC1, 0x3F, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1578 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1579 IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_FM |IAP_F_IB | IAP_F_IBX), 1580 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1581 1582 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1583 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1584 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1585 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1586 IAP_F_SL | IAP_F_SLX), 1587 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1588 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1589 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1590 IAP_F_SLX), 1591 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1592 IAP_F_I7 | IAP_F_WM), 1593 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1594 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1595 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1596 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), 1597 1598 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1599 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1600 IAP_F_I7 | IAP_F_WM | IAP_F_CAS | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1601 IAP_F_SLX), 1602 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1603 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1604 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1605 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1606 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1607 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1608 IAP_F_SL | IAP_F_SLX), 1609 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_FM | IAP_F_CAS), 1610 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1611 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1612 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1613 1614 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1615 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1616 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1617 IAP_F_SL | IAP_F_SLX), 1618 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1619 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1620 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1621 IAP_F_SLX), 1622 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1623 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1624 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1625 IAP_F_SLX), 1626 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1627 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1628 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1629 IAP_F_SLX), 1630 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1631 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1632 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1633 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1634 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1635 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1636 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1637 IAP_F_SL | IAP_F_SLX), 1638 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1639 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1640 IAP_F_SL | IAP_F_SLX), 1641 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1642 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1643 IAP_F_SL | IAP_F_SLX), 1644 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_FM | IAP_F_CAS), 1645 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_FM | IAP_F_CAS), 1646 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_FM | IAP_F_CAS), 1647 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_FM | IAP_F_CAS), 1648 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_FM | IAP_F_CAS), 1649 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_FM | IAP_F_CAS), 1650 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_FM | IAP_F_CAS), 1651 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_FM | IAP_F_CAS), 1652 1653 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1654 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1655 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1656 IAP_F_SL | IAP_F_SLX), 1657 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1658 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1659 IAP_F_BWX | IAP_F_SLX), 1660 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1661 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SL | IAP_F_SLX), 1662 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1663 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1664 IAP_F_BWX | IAP_F_SL), 1665 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1666 IAP_F_SBX | IAP_F_IBX), 1667 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1668 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_SLX), 1669 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_FM | IAP_F_CAS), 1670 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_FM | IAP_F_CAS), 1671 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_FM | IAP_F_CAS), 1672 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_FM | IAP_F_CAS), 1673 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_FM | IAP_F_CAS), 1674 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_FM | IAP_F_CAS), 1675 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_FM | IAP_F_CAS), 1676 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_FM | IAP_F_CAS), 1677 1678 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1679 /* For SL C6_01 needs EV_SEL? 0x11, 0x12, 0x13, 0x14, 0x15? */ 1680 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SL | 1681 IAP_F_SLX), 1682 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1683 1684 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1685 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1686 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1687 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1688 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1689 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1690 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1691 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1692 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1693 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1694 IAP_F_I7 | IAP_F_WM | IAP_F_SL | IAP_F_SLX), 1695 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1696 IAPDESCR(C7H_20H, 0xC7, 0x20, IAP_F_FM | IAP_F_SL | IAP_F_SLX), 1697 IAPDESCR(C7H_40H, 0xc7, 0x40, IAP_F_FM | IAP_F_SLX), 1698 IAPDESCR(C7H_80H, 0xc7, 0x80, IAP_F_FM | IAP_F_SLX), 1699 1700 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1701 IAPDESCR(C8H_01H, 0xC8, 0x01, IAP_F_FM | IAP_F_SLX), 1702 IAPDESCR(C8H_02H, 0xC8, 0x02, IAP_F_FM | IAP_F_SLX), 1703 IAPDESCR(C8H_04H, 0xC8, 0x04, IAP_F_FM | IAP_F_SLX), 1704 IAPDESCR(C8H_08H, 0xC8, 0x08, IAP_F_FM | IAP_F_SLX), 1705 IAPDESCR(C8H_10H, 0xC8, 0x10, IAP_F_FM | IAP_F_SLX), 1706 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SLX), 1707 IAPDESCR(C8H_40H, 0xC8, 0x40, IAP_F_FM | IAP_F_SLX), 1708 IAPDESCR(C8H_80H, 0xC8, 0x80, IAP_F_FM | IAP_F_SLX), 1709 1710 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1711 IAPDESCR(C9H_01H, 0xC9, 0x01, IAP_F_FM | IAP_F_SLX), 1712 IAPDESCR(C9H_02H, 0xC9, 0x02, IAP_F_FM | IAP_F_SLX), 1713 IAPDESCR(C9H_04H, 0xC9, 0x04, IAP_F_FM | IAP_F_SLX), 1714 IAPDESCR(C9H_08H, 0xC9, 0x08, IAP_F_FM | IAP_F_SLX), 1715 IAPDESCR(C9H_10H, 0xC9, 0x10, IAP_F_FM | IAP_F_SLX), 1716 IAPDESCR(C9H_20H, 0xC9, 0x20, IAP_F_FM | IAP_F_SLX), 1717 IAPDESCR(C9H_40H, 0xC9, 0x40, IAP_F_FM | IAP_F_SLX), 1718 IAPDESCR(C9H_80H, 0xC9, 0x80, IAP_F_FM | IAP_F_SLX), 1719 1720 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1721 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 1722 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1723 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1724 IAP_F_BW | IAP_F_BWX), 1725 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1726 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1727 IAP_F_BW | IAP_F_BWX), 1728 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1729 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1730 IAP_F_BW | IAP_F_BWX), 1731 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1732 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1733 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1734 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1735 IAP_F_SL | IAP_F_SLX), 1736 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_FM | IAP_F_CAS | IAP_F_BW | IAP_F_BWX), 1737 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_FM | IAP_F_CAS), 1738 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_FM | IAP_F_CAS), 1739 1740 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1741 IAP_F_I7 | IAP_F_WM | IAP_F_CAS | IAP_F_SL | IAP_F_SLX), 1742 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1743 IAP_F_I7 | IAP_F_WM), 1744 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1745 IAP_F_I7 | IAP_F_WM), 1746 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1747 IAP_F_I7 | IAP_F_WM), 1748 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1749 IAP_F_WM), 1750 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_FM | IAP_F_CAS), 1751 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1752 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1753 1754 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1755 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1756 IAP_F_I7 | IAP_F_WM), 1757 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1758 IAP_F_I7 | IAP_F_WM), 1759 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1760 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1761 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1762 IAP_F_SLX), 1763 1764 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1765 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1766 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | 1767 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1768 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1769 IAP_F_SBX | IAP_F_IBX), 1770 1771 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1772 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1773 1774 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ 1775 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1776 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1777 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1778 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1779 IAP_F_SLX), 1780 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1781 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1782 IAP_F_SLX), 1783 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_BW | 1784 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1785 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1786 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1787 IAP_F_SLX), 1788 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1789 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1790 IAP_F_SLX), 1791 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1792 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1793 IAP_F_SLX), 1794 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1795 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1796 IAP_F_SLX), 1797 1798 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1799 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1800 IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1801 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1802 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1803 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1804 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1805 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1806 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1807 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1808 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1809 IAP_F_SLX), 1810 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX | 1811 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1812 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1813 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1814 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1815 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1816 IAP_F_SL | IAP_F_SLX), 1817 1818 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1819 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1820 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1821 IAP_F_SLX), 1822 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1823 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1824 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1825 IAP_F_SLX), 1826 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1827 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1828 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1829 IAP_F_SLX), 1830 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1831 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1832 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL | 1833 IAP_F_SLX), 1834 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1835 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1836 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1837 1838 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1839 1840 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1841 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SLX), 1842 IAPDESCR(D3H_02H, 0xD3, 0x02, IAP_F_FM | IAP_F_SLX), 1843 IAPDESCR(D3H_03H, 0xD3, 0x03, IAP_F_FM | IAP_F_IBX), 1844 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_SLX), /* Not defined for IBX */ 1845 IAPDESCR(D3H_08H, 0xD3, 0x08, IAP_F_FM | IAP_F_SLX), 1846 IAPDESCR(D3H_0CH, 0xD3, 0x0C, IAP_F_FM | IAP_F_IBX), 1847 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_FM | IAP_F_IBX ), 1848 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_FM | IAP_F_IBX ), 1849 1850 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1851 IAP_F_I7 | IAP_F_WM), 1852 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1853 IAP_F_SB | IAP_F_SBX), 1854 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SLX), 1855 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1856 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1857 1858 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1859 IAP_F_I7 | IAP_F_WM), 1860 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1861 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1862 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1863 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1864 1865 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1866 1867 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1868 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1869 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1870 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1871 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1872 1873 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1874 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1875 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1876 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1877 1878 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1879 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1880 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1881 1882 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1883 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1884 1885 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1886 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1887 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1888 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1889 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1890 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1891 1892 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1893 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1894 IAP_F_WM), 1895 1896 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1897 1898 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1899 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1900 1901 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1902 1903 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1904 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1905 IAP_F_WM | IAP_F_SBX | IAP_F_CAS | IAP_F_SL | IAP_F_SLX), 1906 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1907 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_FM | IAP_F_CAS), 1908 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_FM | IAP_F_CAS), 1909 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB | 1910 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1911 1912 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_FM | IAP_F_CAS), 1913 1914 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1915 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1916 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1917 1918 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1919 1920 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1921 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1922 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1923 IAP_F_BW | IAP_F_BWX), 1924 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1925 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1926 IAP_F_BW | IAP_F_BWX), 1927 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1928 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1929 IAP_F_BW | IAP_F_BWX), 1930 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1931 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1932 IAP_F_BW | IAP_F_BWX), 1933 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1934 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1935 IAP_F_BW | IAP_F_BWX), 1936 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1937 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1938 IAP_F_BW | IAP_F_BWX), 1939 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1940 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1941 IAP_F_BW | IAP_F_BWX | IAP_F_SL | IAP_F_SLX), 1942 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1943 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1944 IAP_F_BW | IAP_F_BWX), 1945 1946 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1947 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1948 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1949 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1950 IAP_F_BW | IAP_F_BWX), 1951 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1952 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1953 IAP_F_BW | IAP_F_BWX ), 1954 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1955 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1956 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1957 IAPDESCR(F1H_1FH, 0xF1, 0x1f, IAP_F_FM | IAP_F_SLX), 1958 1959 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1960 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SLX), 1961 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1962 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SLX), 1963 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1964 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SLX), 1965 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1966 IAP_F_BWX), 1967 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1968 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1969 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1970 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1971 IAP_F_IBX), 1972 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1973 1974 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1975 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1976 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1977 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1978 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1979 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1980 1981 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1982 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1983 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1984 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1985 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1986 IAP_F_SB | IAP_F_SBX | IAP_F_SLX), 1987 1988 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1989 1990 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1991 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1992 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1993 1994 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1995 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1996 1997 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1998 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1999 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2000 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2001 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2002 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2003 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 2004 2005 IAPDESCR(FEH_02H, 0xfe, 0x02, IAP_F_FM | IAP_F_SLX), 2006 IAPDESCR(FEH_04H, 0xfe, 0x04, IAP_F_FM | IAP_F_SLX), 2007 }; 2008 2009 static pmc_value_t 2010 iap_perfctr_value_to_reload_count(pmc_value_t v) 2011 { 2012 2013 /* If the PMC has overflowed, return a reload count of zero. */ 2014 if ((v & (1ULL << (core_iap_width - 1))) == 0) 2015 return (0); 2016 v &= (1ULL << core_iap_width) - 1; 2017 return (1ULL << core_iap_width) - v; 2018 } 2019 2020 static pmc_value_t 2021 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 2022 { 2023 return (1ULL << core_iap_width) - rlc; 2024 } 2025 2026 static int 2027 iap_pmc_has_overflowed(int ri) 2028 { 2029 uint64_t v; 2030 2031 /* 2032 * We treat a Core (i.e., Intel architecture v1) PMC as has 2033 * having overflowed if its MSB is zero. 2034 */ 2035 v = rdpmc(ri); 2036 return ((v & (1ULL << (core_iap_width - 1))) == 0); 2037 } 2038 2039 /* 2040 * Check an event against the set of supported architectural events. 2041 * 2042 * If the event is not architectural EV_IS_NOTARCH is returned. 2043 * If the event is architectural and supported on this CPU, the correct 2044 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. 2045 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. 2046 */ 2047 2048 static int 2049 iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) 2050 { 2051 enum core_arch_events ae; 2052 2053 switch (pe) { 2054 case PMC_EV_IAP_ARCH_UNH_COR_CYC: 2055 ae = CORE_AE_UNHALTED_CORE_CYCLES; 2056 *map = PMC_EV_IAP_EVENT_3CH_00H; 2057 break; 2058 case PMC_EV_IAP_ARCH_INS_RET: 2059 ae = CORE_AE_INSTRUCTION_RETIRED; 2060 *map = PMC_EV_IAP_EVENT_C0H_00H; 2061 break; 2062 case PMC_EV_IAP_ARCH_UNH_REF_CYC: 2063 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 2064 *map = PMC_EV_IAP_EVENT_3CH_01H; 2065 break; 2066 case PMC_EV_IAP_ARCH_LLC_REF: 2067 ae = CORE_AE_LLC_REFERENCE; 2068 *map = PMC_EV_IAP_EVENT_2EH_4FH; 2069 break; 2070 case PMC_EV_IAP_ARCH_LLC_MIS: 2071 ae = CORE_AE_LLC_MISSES; 2072 *map = PMC_EV_IAP_EVENT_2EH_41H; 2073 break; 2074 case PMC_EV_IAP_ARCH_BR_INS_RET: 2075 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 2076 *map = PMC_EV_IAP_EVENT_C4H_00H; 2077 break; 2078 case PMC_EV_IAP_ARCH_BR_MIS_RET: 2079 ae = CORE_AE_BRANCH_MISSES_RETIRED; 2080 *map = PMC_EV_IAP_EVENT_C5H_00H; 2081 break; 2082 2083 default: /* Non architectural event. */ 2084 return (EV_IS_NOTARCH); 2085 } 2086 2087 return (((core_architectural_events & (1 << ae)) == 0) ? 2088 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); 2089 } 2090 2091 static int 2092 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 2093 { 2094 uint32_t mask; 2095 2096 switch (pe) { 2097 /* 2098 * Events valid only on counter 0, 1. 2099 */ 2100 case PMC_EV_IAP_EVENT_40H_01H: 2101 case PMC_EV_IAP_EVENT_40H_02H: 2102 case PMC_EV_IAP_EVENT_40H_04H: 2103 case PMC_EV_IAP_EVENT_40H_08H: 2104 case PMC_EV_IAP_EVENT_40H_0FH: 2105 case PMC_EV_IAP_EVENT_41H_02H: 2106 case PMC_EV_IAP_EVENT_41H_04H: 2107 case PMC_EV_IAP_EVENT_41H_08H: 2108 case PMC_EV_IAP_EVENT_42H_01H: 2109 case PMC_EV_IAP_EVENT_42H_02H: 2110 case PMC_EV_IAP_EVENT_42H_04H: 2111 case PMC_EV_IAP_EVENT_42H_08H: 2112 case PMC_EV_IAP_EVENT_43H_01H: 2113 case PMC_EV_IAP_EVENT_43H_02H: 2114 case PMC_EV_IAP_EVENT_51H_01H: 2115 case PMC_EV_IAP_EVENT_51H_02H: 2116 case PMC_EV_IAP_EVENT_51H_04H: 2117 case PMC_EV_IAP_EVENT_51H_08H: 2118 case PMC_EV_IAP_EVENT_63H_01H: 2119 case PMC_EV_IAP_EVENT_63H_02H: 2120 mask = 0x3; 2121 break; 2122 2123 default: 2124 mask = ~0; /* Any row index is ok. */ 2125 } 2126 2127 return (mask & (1 << ri)); 2128 } 2129 2130 static int 2131 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 2132 { 2133 uint32_t mask; 2134 2135 switch (pe) { 2136 /* 2137 * Events valid only on counter 0. 2138 */ 2139 case PMC_EV_IAP_EVENT_60H_01H: 2140 case PMC_EV_IAP_EVENT_60H_02H: 2141 case PMC_EV_IAP_EVENT_60H_04H: 2142 case PMC_EV_IAP_EVENT_60H_08H: 2143 case PMC_EV_IAP_EVENT_B3H_01H: 2144 case PMC_EV_IAP_EVENT_B3H_02H: 2145 case PMC_EV_IAP_EVENT_B3H_04H: 2146 mask = 0x1; 2147 break; 2148 2149 /* 2150 * Events valid only on counter 0, 1. 2151 */ 2152 case PMC_EV_IAP_EVENT_4CH_01H: 2153 case PMC_EV_IAP_EVENT_4EH_01H: 2154 case PMC_EV_IAP_EVENT_4EH_02H: 2155 case PMC_EV_IAP_EVENT_4EH_04H: 2156 case PMC_EV_IAP_EVENT_51H_01H: 2157 case PMC_EV_IAP_EVENT_51H_02H: 2158 case PMC_EV_IAP_EVENT_51H_04H: 2159 case PMC_EV_IAP_EVENT_51H_08H: 2160 case PMC_EV_IAP_EVENT_63H_01H: 2161 case PMC_EV_IAP_EVENT_63H_02H: 2162 mask = 0x3; 2163 break; 2164 2165 default: 2166 mask = ~0; /* Any row index is ok. */ 2167 } 2168 2169 return (mask & (1 << ri)); 2170 } 2171 2172 static int 2173 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 2174 { 2175 uint32_t mask; 2176 2177 switch (pe) { 2178 /* Events valid only on counter 0. */ 2179 case PMC_EV_IAP_EVENT_B7H_01H: 2180 mask = 0x1; 2181 break; 2182 /* Events valid only on counter 1. */ 2183 case PMC_EV_IAP_EVENT_C0H_01H: 2184 mask = 0x2; 2185 break; 2186 /* Events valid only on counter 2. */ 2187 case PMC_EV_IAP_EVENT_48H_01H: 2188 case PMC_EV_IAP_EVENT_A2H_02H: 2189 case PMC_EV_IAP_EVENT_A3H_08H: 2190 mask = 0x4; 2191 break; 2192 /* Events valid only on counter 3. */ 2193 case PMC_EV_IAP_EVENT_BBH_01H: 2194 case PMC_EV_IAP_EVENT_CDH_01H: 2195 case PMC_EV_IAP_EVENT_CDH_02H: 2196 mask = 0x8; 2197 break; 2198 default: 2199 mask = ~0; /* Any row index is ok. */ 2200 } 2201 2202 return (mask & (1 << ri)); 2203 } 2204 2205 static int 2206 iap_event_ok_on_counter(enum pmc_event pe, int ri) 2207 { 2208 uint32_t mask; 2209 2210 switch (pe) { 2211 /* 2212 * Events valid only on counter 0. 2213 */ 2214 case PMC_EV_IAP_EVENT_10H_00H: 2215 case PMC_EV_IAP_EVENT_14H_00H: 2216 case PMC_EV_IAP_EVENT_18H_00H: 2217 case PMC_EV_IAP_EVENT_B3H_01H: 2218 case PMC_EV_IAP_EVENT_B3H_02H: 2219 case PMC_EV_IAP_EVENT_B3H_04H: 2220 case PMC_EV_IAP_EVENT_C1H_00H: 2221 case PMC_EV_IAP_EVENT_CBH_01H: 2222 case PMC_EV_IAP_EVENT_CBH_02H: 2223 mask = (1 << 0); 2224 break; 2225 2226 /* 2227 * Events valid only on counter 1. 2228 */ 2229 case PMC_EV_IAP_EVENT_11H_00H: 2230 case PMC_EV_IAP_EVENT_12H_00H: 2231 case PMC_EV_IAP_EVENT_13H_00H: 2232 mask = (1 << 1); 2233 break; 2234 2235 default: 2236 mask = ~0; /* Any row index is ok. */ 2237 } 2238 2239 return (mask & (1 << ri)); 2240 } 2241 2242 static int 2243 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 2244 const struct pmc_op_pmcallocate *a) 2245 { 2246 int arch, n, model; 2247 enum pmc_event ev, map; 2248 struct iap_event_descr *ie; 2249 uint32_t c, caps, config, cpuflag, evsel, mask; 2250 2251 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2252 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2253 KASSERT(ri >= 0 && ri < core_iap_npmc, 2254 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 2255 2256 /* check requested capabilities */ 2257 caps = a->pm_caps; 2258 if ((IAP_PMC_CAPS & caps) != caps) 2259 return (EPERM); 2260 map = 0; /* XXX: silent GCC warning */ 2261 arch = iap_is_event_architectural(pm->pm_event, &map); 2262 if (arch == EV_IS_ARCH_NOTSUPP) 2263 return (EOPNOTSUPP); 2264 else if (arch == EV_IS_ARCH_SUPP) 2265 ev = map; 2266 else 2267 ev = pm->pm_event; 2268 2269 /* 2270 * A small number of events are not supported in all the 2271 * processors based on a given microarchitecture. 2272 */ 2273 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 2274 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 2275 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 2276 return (EINVAL); 2277 } 2278 2279 switch (core_cputype) { 2280 case PMC_CPU_INTEL_COREI7: 2281 case PMC_CPU_INTEL_NEHALEM_EX: 2282 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 2283 return (EINVAL); 2284 break; 2285 case PMC_CPU_INTEL_SKYLAKE: 2286 case PMC_CPU_INTEL_SKYLAKE_XEON: 2287 case PMC_CPU_INTEL_BROADWELL: 2288 case PMC_CPU_INTEL_BROADWELL_XEON: 2289 case PMC_CPU_INTEL_SANDYBRIDGE: 2290 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2291 case PMC_CPU_INTEL_IVYBRIDGE: 2292 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2293 case PMC_CPU_INTEL_HASWELL: 2294 case PMC_CPU_INTEL_HASWELL_XEON: 2295 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 2296 return (EINVAL); 2297 break; 2298 case PMC_CPU_INTEL_WESTMERE: 2299 case PMC_CPU_INTEL_WESTMERE_EX: 2300 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 2301 return (EINVAL); 2302 break; 2303 default: 2304 if (iap_event_ok_on_counter(ev, ri) == 0) 2305 return (EINVAL); 2306 } 2307 2308 /* 2309 * Look for an event descriptor with matching CPU and event id 2310 * fields. 2311 */ 2312 2313 switch (core_cputype) { 2314 default: 2315 case PMC_CPU_INTEL_ATOM: 2316 cpuflag = IAP_F_CA; 2317 break; 2318 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2319 cpuflag = IAP_F_CAS; 2320 break; 2321 case PMC_CPU_INTEL_SKYLAKE_XEON: 2322 cpuflag = IAP_F_SLX; 2323 break; 2324 case PMC_CPU_INTEL_SKYLAKE: 2325 cpuflag = IAP_F_SL; 2326 break; 2327 case PMC_CPU_INTEL_BROADWELL_XEON: 2328 cpuflag = IAP_F_BWX; 2329 break; 2330 case PMC_CPU_INTEL_BROADWELL: 2331 cpuflag = IAP_F_BW; 2332 break; 2333 case PMC_CPU_INTEL_CORE: 2334 cpuflag = IAP_F_CC; 2335 break; 2336 case PMC_CPU_INTEL_CORE2: 2337 cpuflag = IAP_F_CC2; 2338 break; 2339 case PMC_CPU_INTEL_CORE2EXTREME: 2340 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 2341 break; 2342 case PMC_CPU_INTEL_COREI7: 2343 cpuflag = IAP_F_I7; 2344 break; 2345 case PMC_CPU_INTEL_HASWELL: 2346 cpuflag = IAP_F_HW; 2347 break; 2348 case PMC_CPU_INTEL_HASWELL_XEON: 2349 cpuflag = IAP_F_HWX; 2350 break; 2351 case PMC_CPU_INTEL_IVYBRIDGE: 2352 cpuflag = IAP_F_IB; 2353 break; 2354 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2355 cpuflag = IAP_F_IBX; 2356 break; 2357 case PMC_CPU_INTEL_SANDYBRIDGE: 2358 cpuflag = IAP_F_SB; 2359 break; 2360 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2361 cpuflag = IAP_F_SBX; 2362 break; 2363 case PMC_CPU_INTEL_WESTMERE: 2364 cpuflag = IAP_F_WM; 2365 break; 2366 } 2367 2368 for (n = 0, ie = iap_events; n < nitems(iap_events); n++, ie++) 2369 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2370 break; 2371 2372 if (n == nitems(iap_events)) 2373 return (EINVAL); 2374 2375 /* 2376 * A matching event descriptor has been found, so start 2377 * assembling the contents of the event select register. 2378 */ 2379 evsel = ie->iap_evcode; 2380 2381 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2382 2383 /* 2384 * If the event uses a fixed umask value, reject any umask 2385 * bits set by the user. 2386 */ 2387 if (ie->iap_flags & IAP_F_FM) { 2388 2389 if (IAP_UMASK(config) != 0) 2390 return (EINVAL); 2391 2392 evsel |= (ie->iap_umask << 8); 2393 2394 } else { 2395 2396 /* 2397 * Otherwise, the UMASK value needs to be taken from 2398 * the MD fields of the allocation request. Reject 2399 * requests that specify reserved bits. 2400 */ 2401 2402 mask = 0; 2403 2404 if (ie->iap_umask & IAP_M_CORE) { 2405 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2406 c != IAP_CORE_THIS) 2407 return (EINVAL); 2408 mask |= IAP_F_CORE; 2409 } 2410 2411 if (ie->iap_umask & IAP_M_AGENT) 2412 mask |= IAP_F_AGENT; 2413 2414 if (ie->iap_umask & IAP_M_PREFETCH) { 2415 2416 if ((c = (config & IAP_F_PREFETCH)) == 2417 IAP_PREFETCH_RESERVED) 2418 return (EINVAL); 2419 2420 mask |= IAP_F_PREFETCH; 2421 } 2422 2423 if (ie->iap_umask & IAP_M_MESI) 2424 mask |= IAP_F_MESI; 2425 2426 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2427 mask |= IAP_F_SNOOPRESPONSE; 2428 2429 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2430 mask |= IAP_F_SNOOPTYPE; 2431 2432 if (ie->iap_umask & IAP_M_TRANSITION) 2433 mask |= IAP_F_TRANSITION; 2434 2435 /* 2436 * If bits outside of the allowed set of umask bits 2437 * are set, reject the request. 2438 */ 2439 if (config & ~mask) 2440 return (EINVAL); 2441 2442 evsel |= (config & mask); 2443 2444 } 2445 2446 /* 2447 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2448 */ 2449 if (core_cputype == PMC_CPU_INTEL_ATOM || 2450 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 2451 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2452 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2453 evsel |= (config & IAP_ANY); 2454 else if (config & IAP_ANY) 2455 return (EINVAL); 2456 2457 /* 2458 * Check offcore response configuration. 2459 */ 2460 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2461 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2462 ev != PMC_EV_IAP_EVENT_BBH_01H) 2463 return (EINVAL); 2464 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2465 ev == PMC_EV_IAP_EVENT_BBH_01H) 2466 return (EINVAL); 2467 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2468 core_cputype == PMC_CPU_INTEL_WESTMERE || 2469 core_cputype == PMC_CPU_INTEL_NEHALEM_EX || 2470 core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && 2471 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2472 return (EINVAL); 2473 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2474 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2475 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2476 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2477 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2478 return (EINVAL); 2479 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2480 } 2481 2482 if (caps & PMC_CAP_THRESHOLD) 2483 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2484 if (caps & PMC_CAP_USER) 2485 evsel |= IAP_USR; 2486 if (caps & PMC_CAP_SYSTEM) 2487 evsel |= IAP_OS; 2488 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2489 evsel |= (IAP_OS | IAP_USR); 2490 if (caps & PMC_CAP_EDGE) 2491 evsel |= IAP_EDGE; 2492 if (caps & PMC_CAP_INVERT) 2493 evsel |= IAP_INV; 2494 if (caps & PMC_CAP_INTERRUPT) 2495 evsel |= IAP_INT; 2496 2497 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2498 2499 return (0); 2500 } 2501 2502 static int 2503 iap_config_pmc(int cpu, int ri, struct pmc *pm) 2504 { 2505 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2506 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2507 2508 KASSERT(ri >= 0 && ri < core_iap_npmc, 2509 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2510 2511 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2512 2513 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2514 cpu)); 2515 2516 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2517 2518 return (0); 2519 } 2520 2521 static int 2522 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2523 { 2524 int error; 2525 struct pmc_hw *phw; 2526 char iap_name[PMC_NAME_MAX]; 2527 2528 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2529 2530 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2531 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2532 NULL)) != 0) 2533 return (error); 2534 2535 pi->pm_class = PMC_CLASS_IAP; 2536 2537 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2538 pi->pm_enabled = TRUE; 2539 *ppmc = phw->phw_pmc; 2540 } else { 2541 pi->pm_enabled = FALSE; 2542 *ppmc = NULL; 2543 } 2544 2545 return (0); 2546 } 2547 2548 static int 2549 iap_get_config(int cpu, int ri, struct pmc **ppm) 2550 { 2551 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2552 2553 return (0); 2554 } 2555 2556 static int 2557 iap_get_msr(int ri, uint32_t *msr) 2558 { 2559 KASSERT(ri >= 0 && ri < core_iap_npmc, 2560 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2561 2562 *msr = ri; 2563 2564 return (0); 2565 } 2566 2567 static int 2568 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2569 { 2570 struct pmc *pm; 2571 pmc_value_t tmp; 2572 2573 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2574 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2575 KASSERT(ri >= 0 && ri < core_iap_npmc, 2576 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2577 2578 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2579 2580 KASSERT(pm, 2581 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2582 ri)); 2583 2584 tmp = rdpmc(ri); 2585 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2586 *v = iap_perfctr_value_to_reload_count(tmp); 2587 else 2588 *v = tmp & ((1ULL << core_iap_width) - 1); 2589 2590 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2591 IAP_PMC0 + ri, *v); 2592 2593 return (0); 2594 } 2595 2596 static int 2597 iap_release_pmc(int cpu, int ri, struct pmc *pm) 2598 { 2599 (void) pm; 2600 2601 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2602 pm); 2603 2604 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2605 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2606 KASSERT(ri >= 0 && ri < core_iap_npmc, 2607 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2608 2609 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2610 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2611 2612 return (0); 2613 } 2614 2615 static int 2616 iap_start_pmc(int cpu, int ri) 2617 { 2618 struct pmc *pm; 2619 uint32_t evsel; 2620 struct core_cpu *cc; 2621 2622 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2623 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2624 KASSERT(ri >= 0 && ri < core_iap_npmc, 2625 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2626 2627 cc = core_pcpu[cpu]; 2628 pm = cc->pc_corepmcs[ri].phw_pmc; 2629 2630 KASSERT(pm, 2631 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2632 __LINE__, cpu, ri)); 2633 2634 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2635 2636 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2637 2638 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2639 cpu, ri, IAP_EVSEL0 + ri, evsel); 2640 2641 /* Event specific configuration. */ 2642 switch (pm->pm_event) { 2643 case PMC_EV_IAP_EVENT_B7H_01H: 2644 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2645 break; 2646 case PMC_EV_IAP_EVENT_BBH_01H: 2647 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2648 break; 2649 default: 2650 break; 2651 } 2652 2653 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2654 2655 if (core_cputype == PMC_CPU_INTEL_CORE) 2656 return (0); 2657 2658 do { 2659 cc->pc_resync = 0; 2660 cc->pc_globalctrl |= (1ULL << ri); 2661 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2662 } while (cc->pc_resync != 0); 2663 2664 return (0); 2665 } 2666 2667 static int 2668 iap_stop_pmc(int cpu, int ri) 2669 { 2670 struct pmc *pm; 2671 struct core_cpu *cc; 2672 uint64_t msr; 2673 2674 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2675 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2676 KASSERT(ri >= 0 && ri < core_iap_npmc, 2677 ("[core,%d] illegal row index %d", __LINE__, ri)); 2678 2679 cc = core_pcpu[cpu]; 2680 pm = cc->pc_corepmcs[ri].phw_pmc; 2681 2682 KASSERT(pm, 2683 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2684 cpu, ri)); 2685 2686 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2687 2688 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2689 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2690 2691 if (core_cputype == PMC_CPU_INTEL_CORE) 2692 return (0); 2693 2694 msr = 0; 2695 do { 2696 cc->pc_resync = 0; 2697 cc->pc_globalctrl &= ~(1ULL << ri); 2698 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2699 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2700 } while (cc->pc_resync != 0); 2701 2702 return (0); 2703 } 2704 2705 static int 2706 iap_write_pmc(int cpu, int ri, pmc_value_t v) 2707 { 2708 struct pmc *pm; 2709 struct core_cpu *cc; 2710 2711 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2712 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2713 KASSERT(ri >= 0 && ri < core_iap_npmc, 2714 ("[core,%d] illegal row index %d", __LINE__, ri)); 2715 2716 cc = core_pcpu[cpu]; 2717 pm = cc->pc_corepmcs[ri].phw_pmc; 2718 2719 KASSERT(pm, 2720 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2721 cpu, ri)); 2722 2723 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2724 v = iap_reload_count_to_perfctr_value(v); 2725 2726 v &= (1ULL << core_iap_width) - 1; 2727 2728 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2729 IAP_PMC0 + ri, v); 2730 2731 /* 2732 * Write the new value to the counter (or it's alias). The 2733 * counter will be in a stopped state when the pcd_write() 2734 * entry point is called. 2735 */ 2736 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 2737 return (0); 2738 } 2739 2740 2741 static void 2742 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2743 int flags) 2744 { 2745 struct pmc_classdep *pcd; 2746 2747 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2748 2749 PMCDBG0(MDP,INI,1, "iap-initialize"); 2750 2751 /* Remember the set of architectural events supported. */ 2752 core_architectural_events = ~flags; 2753 2754 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2755 2756 pcd->pcd_caps = IAP_PMC_CAPS; 2757 pcd->pcd_class = PMC_CLASS_IAP; 2758 pcd->pcd_num = npmc; 2759 pcd->pcd_ri = md->pmd_npmc; 2760 pcd->pcd_width = pmcwidth; 2761 2762 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2763 pcd->pcd_config_pmc = iap_config_pmc; 2764 pcd->pcd_describe = iap_describe; 2765 pcd->pcd_get_config = iap_get_config; 2766 pcd->pcd_get_msr = iap_get_msr; 2767 pcd->pcd_pcpu_fini = core_pcpu_fini; 2768 pcd->pcd_pcpu_init = core_pcpu_init; 2769 pcd->pcd_read_pmc = iap_read_pmc; 2770 pcd->pcd_release_pmc = iap_release_pmc; 2771 pcd->pcd_start_pmc = iap_start_pmc; 2772 pcd->pcd_stop_pmc = iap_stop_pmc; 2773 pcd->pcd_write_pmc = iap_write_pmc; 2774 2775 md->pmd_npmc += npmc; 2776 } 2777 2778 static int 2779 core_intr(int cpu, struct trapframe *tf) 2780 { 2781 pmc_value_t v; 2782 struct pmc *pm; 2783 struct core_cpu *cc; 2784 int error, found_interrupt, ri; 2785 uint64_t msr; 2786 2787 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2788 TRAPF_USERMODE(tf)); 2789 2790 found_interrupt = 0; 2791 cc = core_pcpu[cpu]; 2792 2793 for (ri = 0; ri < core_iap_npmc; ri++) { 2794 2795 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2796 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2797 continue; 2798 2799 if (!iap_pmc_has_overflowed(ri)) 2800 continue; 2801 2802 found_interrupt = 1; 2803 2804 if (pm->pm_state != PMC_STATE_RUNNING) 2805 continue; 2806 2807 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2808 TRAPF_USERMODE(tf)); 2809 2810 v = pm->pm_sc.pm_reloadcount; 2811 v = iap_reload_count_to_perfctr_value(v); 2812 2813 /* 2814 * Stop the counter, reload it but only restart it if 2815 * the PMC is not stalled. 2816 */ 2817 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2818 wrmsr(IAP_EVSEL0 + ri, msr); 2819 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 2820 2821 if (error) 2822 continue; 2823 2824 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2825 IAP_EN)); 2826 } 2827 2828 if (found_interrupt) 2829 lapic_reenable_pmc(); 2830 2831 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2832 &pmc_stats.pm_intr_ignored, 1); 2833 2834 return (found_interrupt); 2835 } 2836 2837 static int 2838 core2_intr(int cpu, struct trapframe *tf) 2839 { 2840 int error, found_interrupt, n; 2841 uint64_t flag, intrstatus, intrenable, msr; 2842 struct pmc *pm; 2843 struct core_cpu *cc; 2844 pmc_value_t v; 2845 2846 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2847 TRAPF_USERMODE(tf)); 2848 2849 /* 2850 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2851 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2852 * the current set of interrupting PMCs and process these 2853 * after stopping them. 2854 */ 2855 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2856 intrenable = intrstatus & core_pmcmask; 2857 2858 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2859 (uintmax_t) intrstatus); 2860 2861 found_interrupt = 0; 2862 cc = core_pcpu[cpu]; 2863 2864 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2865 2866 cc->pc_globalctrl &= ~intrenable; 2867 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2868 2869 /* 2870 * Stop PMCs and clear overflow status bits. 2871 */ 2872 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2873 wrmsr(IA_GLOBAL_CTRL, msr); 2874 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2875 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2876 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2877 2878 /* 2879 * Look for interrupts from fixed function PMCs. 2880 */ 2881 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2882 n++, flag <<= 1) { 2883 2884 if ((intrstatus & flag) == 0) 2885 continue; 2886 2887 found_interrupt = 1; 2888 2889 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2890 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2891 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2892 continue; 2893 2894 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2895 TRAPF_USERMODE(tf)); 2896 if (error) 2897 intrenable &= ~flag; 2898 2899 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2900 2901 /* Reload sampling count. */ 2902 wrmsr(IAF_CTR0 + n, v); 2903 2904 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 2905 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2906 } 2907 2908 /* 2909 * Process interrupts from the programmable counters. 2910 */ 2911 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2912 if ((intrstatus & flag) == 0) 2913 continue; 2914 2915 found_interrupt = 1; 2916 2917 pm = cc->pc_corepmcs[n].phw_pmc; 2918 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2919 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2920 continue; 2921 2922 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2923 TRAPF_USERMODE(tf)); 2924 if (error) 2925 intrenable &= ~flag; 2926 2927 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2928 2929 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2930 (uintmax_t) v); 2931 2932 /* Reload sampling count. */ 2933 wrmsr(core_iap_wroffset + IAP_PMC0 + n, v); 2934 } 2935 2936 /* 2937 * Reenable all non-stalled PMCs. 2938 */ 2939 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2940 (uintmax_t) intrenable); 2941 2942 cc->pc_globalctrl |= intrenable; 2943 2944 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2945 2946 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2947 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2948 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2949 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2950 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2951 2952 if (found_interrupt) 2953 lapic_reenable_pmc(); 2954 2955 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2956 &pmc_stats.pm_intr_ignored, 1); 2957 2958 return (found_interrupt); 2959 } 2960 2961 int 2962 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 2963 { 2964 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2965 int ipa_version, flags, nflags; 2966 2967 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2968 2969 ipa_version = (version_override > 0) ? version_override : 2970 cpuid[CORE_CPUID_EAX] & 0xFF; 2971 core_cputype = md->pmd_cputype; 2972 2973 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2974 core_cputype, maxcpu, ipa_version); 2975 2976 if (ipa_version < 1 || ipa_version > 4 || 2977 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 2978 /* Unknown PMC architecture. */ 2979 printf("hwpc_core: unknown PMC architecture: %d\n", 2980 ipa_version); 2981 return (EPROGMISMATCH); 2982 } 2983 2984 core_iap_wroffset = 0; 2985 if (cpu_feature2 & CPUID2_PDCM) { 2986 if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) { 2987 PMCDBG0(MDP, INI, 1, 2988 "core-init full-width write supported"); 2989 core_iap_wroffset = IAP_A_PMC0 - IAP_PMC0; 2990 } else 2991 PMCDBG0(MDP, INI, 1, 2992 "core-init full-width write NOT supported"); 2993 } else 2994 PMCDBG0(MDP, INI, 1, "core-init pdcm not supported"); 2995 2996 core_pmcmask = 0; 2997 2998 /* 2999 * Initialize programmable counters. 3000 */ 3001 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 3002 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 3003 3004 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 3005 3006 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 3007 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 3008 3009 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 3010 3011 /* 3012 * Initialize fixed function counters, if present. 3013 */ 3014 if (core_cputype != PMC_CPU_INTEL_CORE) { 3015 core_iaf_ri = core_iap_npmc; 3016 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 3017 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 3018 3019 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 3020 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 3021 } 3022 3023 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 3024 core_iaf_ri); 3025 3026 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 3027 M_ZERO | M_WAITOK); 3028 3029 /* 3030 * Choose the appropriate interrupt handler. 3031 */ 3032 if (ipa_version == 1) 3033 md->pmd_intr = core_intr; 3034 else 3035 md->pmd_intr = core2_intr; 3036 3037 md->pmd_pcpu_fini = NULL; 3038 md->pmd_pcpu_init = NULL; 3039 3040 return (0); 3041 } 3042 3043 void 3044 pmc_core_finalize(struct pmc_mdep *md) 3045 { 3046 PMCDBG0(MDP,INI,1, "core-finalize"); 3047 3048 free(core_pcpu, M_PMC); 3049 core_pcpu = NULL; 3050 } 3051