1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #include <machine/apicvar.h> 42 #include <machine/cpu.h> 43 #include <machine/cpufunc.h> 44 #include <machine/specialreg.h> 45 46 #define CORE_CPUID_REQUEST 0xA 47 #define CORE_CPUID_REQUEST_SIZE 0x4 48 #define CORE_CPUID_EAX 0x0 49 #define CORE_CPUID_EBX 0x1 50 #define CORE_CPUID_ECX 0x2 51 #define CORE_CPUID_EDX 0x3 52 53 #define IAF_PMC_CAPS \ 54 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT) 55 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 56 57 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 58 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 59 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 60 61 /* 62 * "Architectural" events defined by Intel. The values of these 63 * symbols correspond to positions in the bitmask returned by 64 * the CPUID.0AH instruction. 65 */ 66 enum core_arch_events { 67 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 68 CORE_AE_BRANCH_MISSES_RETIRED = 6, 69 CORE_AE_INSTRUCTION_RETIRED = 1, 70 CORE_AE_LLC_MISSES = 4, 71 CORE_AE_LLC_REFERENCE = 3, 72 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 73 CORE_AE_UNHALTED_CORE_CYCLES = 0 74 }; 75 76 static enum pmc_cputype core_cputype; 77 78 struct core_cpu { 79 volatile uint32_t pc_resync; 80 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 81 volatile uint64_t pc_globalctrl; /* Global control register. */ 82 struct pmc_hw pc_corepmcs[]; 83 }; 84 85 static struct core_cpu **core_pcpu; 86 87 static uint32_t core_architectural_events; 88 static uint64_t core_pmcmask; 89 90 static int core_iaf_ri; /* relative index of fixed counters */ 91 static int core_iaf_width; 92 static int core_iaf_npmc; 93 94 static int core_iap_width; 95 static int core_iap_npmc; 96 97 static int 98 core_pcpu_noop(struct pmc_mdep *md, int cpu) 99 { 100 (void) md; 101 (void) cpu; 102 return (0); 103 } 104 105 static int 106 core_pcpu_init(struct pmc_mdep *md, int cpu) 107 { 108 struct pmc_cpu *pc; 109 struct core_cpu *cc; 110 struct pmc_hw *phw; 111 int core_ri, n, npmc; 112 113 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 114 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 115 116 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 117 118 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 119 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 120 121 if (core_cputype != PMC_CPU_INTEL_CORE) 122 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 123 124 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 125 M_PMC, M_WAITOK | M_ZERO); 126 127 core_pcpu[cpu] = cc; 128 pc = pmc_pcpu[cpu]; 129 130 KASSERT(pc != NULL && cc != NULL, 131 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 132 133 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 134 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 135 PMC_PHW_CPU_TO_STATE(cpu) | 136 PMC_PHW_INDEX_TO_STATE(n + core_ri); 137 phw->phw_pmc = NULL; 138 pc->pc_hwpmcs[n + core_ri] = phw; 139 } 140 141 return (0); 142 } 143 144 static int 145 core_pcpu_fini(struct pmc_mdep *md, int cpu) 146 { 147 int core_ri, n, npmc; 148 struct pmc_cpu *pc; 149 struct core_cpu *cc; 150 151 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 152 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 153 154 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 155 156 if ((cc = core_pcpu[cpu]) == NULL) 157 return (0); 158 159 core_pcpu[cpu] = NULL; 160 161 pc = pmc_pcpu[cpu]; 162 163 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 164 cpu)); 165 166 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 167 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 168 169 for (n = 0; n < npmc; n++) 170 wrmsr(IAP_EVSEL0 + n, 0); 171 172 if (core_cputype != PMC_CPU_INTEL_CORE) { 173 wrmsr(IAF_CTRL, 0); 174 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 175 } 176 177 for (n = 0; n < npmc; n++) 178 pc->pc_hwpmcs[n + core_ri] = NULL; 179 180 free(cc, M_PMC); 181 182 return (0); 183 } 184 185 /* 186 * Fixed function counters. 187 */ 188 189 static pmc_value_t 190 iaf_perfctr_value_to_reload_count(pmc_value_t v) 191 { 192 v &= (1ULL << core_iaf_width) - 1; 193 return (1ULL << core_iaf_width) - v; 194 } 195 196 static pmc_value_t 197 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 198 { 199 return (1ULL << core_iaf_width) - rlc; 200 } 201 202 static int 203 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 204 const struct pmc_op_pmcallocate *a) 205 { 206 enum pmc_event ev; 207 uint32_t caps, flags, validflags; 208 209 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 210 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 211 212 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 213 214 if (ri < 0 || ri > core_iaf_npmc) 215 return (EINVAL); 216 217 caps = a->pm_caps; 218 219 if (a->pm_class != PMC_CLASS_IAF || 220 (caps & IAF_PMC_CAPS) != caps) 221 return (EINVAL); 222 223 ev = pm->pm_event; 224 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 225 return (EINVAL); 226 227 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 228 return (EINVAL); 229 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 230 return (EINVAL); 231 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 232 return (EINVAL); 233 234 flags = a->pm_md.pm_iaf.pm_iaf_flags; 235 236 validflags = IAF_MASK; 237 238 if (core_cputype != PMC_CPU_INTEL_ATOM) 239 validflags &= ~IAF_ANY; 240 241 if ((flags & ~validflags) != 0) 242 return (EINVAL); 243 244 if (caps & PMC_CAP_INTERRUPT) 245 flags |= IAF_PMI; 246 if (caps & PMC_CAP_SYSTEM) 247 flags |= IAF_OS; 248 if (caps & PMC_CAP_USER) 249 flags |= IAF_USR; 250 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 251 flags |= (IAF_OS | IAF_USR); 252 253 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 254 255 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 256 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 257 258 return (0); 259 } 260 261 static int 262 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 263 { 264 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 265 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 266 267 KASSERT(ri >= 0 && ri < core_iaf_npmc, 268 ("[core,%d] illegal row-index %d", __LINE__, ri)); 269 270 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 271 272 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 273 cpu)); 274 275 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 276 277 return (0); 278 } 279 280 static int 281 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 282 { 283 int error; 284 struct pmc_hw *phw; 285 char iaf_name[PMC_NAME_MAX]; 286 287 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 288 289 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 290 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 291 NULL)) != 0) 292 return (error); 293 294 pi->pm_class = PMC_CLASS_IAF; 295 296 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 297 pi->pm_enabled = TRUE; 298 *ppmc = phw->phw_pmc; 299 } else { 300 pi->pm_enabled = FALSE; 301 *ppmc = NULL; 302 } 303 304 return (0); 305 } 306 307 static int 308 iaf_get_config(int cpu, int ri, struct pmc **ppm) 309 { 310 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 311 312 return (0); 313 } 314 315 static int 316 iaf_get_msr(int ri, uint32_t *msr) 317 { 318 KASSERT(ri >= 0 && ri < core_iaf_npmc, 319 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 320 321 *msr = IAF_RI_TO_MSR(ri); 322 323 return (0); 324 } 325 326 static int 327 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 328 { 329 struct pmc *pm; 330 pmc_value_t tmp; 331 332 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 333 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 334 KASSERT(ri >= 0 && ri < core_iaf_npmc, 335 ("[core,%d] illegal row-index %d", __LINE__, ri)); 336 337 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 338 339 KASSERT(pm, 340 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 341 ri, ri + core_iaf_ri)); 342 343 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 344 345 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 346 *v = iaf_perfctr_value_to_reload_count(tmp); 347 else 348 *v = tmp; 349 350 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 351 IAF_RI_TO_MSR(ri), *v); 352 353 return (0); 354 } 355 356 static int 357 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 358 { 359 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 360 361 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 362 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 363 KASSERT(ri >= 0 && ri < core_iaf_npmc, 364 ("[core,%d] illegal row-index %d", __LINE__, ri)); 365 366 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 367 ("[core,%d] PHW pmc non-NULL", __LINE__)); 368 369 return (0); 370 } 371 372 static int 373 iaf_start_pmc(int cpu, int ri) 374 { 375 struct pmc *pm; 376 struct core_cpu *iafc; 377 378 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 379 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 380 KASSERT(ri >= 0 && ri < core_iaf_npmc, 381 ("[core,%d] illegal row-index %d", __LINE__, ri)); 382 383 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 384 385 iafc = core_pcpu[cpu]; 386 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 387 388 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 389 390 wrmsr(IAF_CTRL, iafc->pc_iafctrl); 391 392 do { 393 iafc->pc_resync = 0; 394 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 395 wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl); 396 } while (iafc->pc_resync != 0); 397 398 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 399 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 400 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 401 402 return (0); 403 } 404 405 static int 406 iaf_stop_pmc(int cpu, int ri) 407 { 408 uint32_t fc; 409 struct core_cpu *iafc; 410 411 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 412 413 iafc = core_pcpu[cpu]; 414 415 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 416 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 417 KASSERT(ri >= 0 && ri < core_iaf_npmc, 418 ("[core,%d] illegal row-index %d", __LINE__, ri)); 419 420 fc = (IAF_MASK << (ri * 4)); 421 422 if (core_cputype != PMC_CPU_INTEL_ATOM) 423 fc &= ~IAF_ANY; 424 425 iafc->pc_iafctrl &= ~fc; 426 427 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 428 wrmsr(IAF_CTRL, iafc->pc_iafctrl); 429 430 do { 431 iafc->pc_resync = 0; 432 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 433 wrmsr(IA_GLOBAL_CTRL, iafc->pc_globalctrl); 434 } while (iafc->pc_resync != 0); 435 436 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 437 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 438 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 439 440 return (0); 441 } 442 443 static int 444 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 445 { 446 struct core_cpu *cc; 447 struct pmc *pm; 448 449 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 450 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 451 KASSERT(ri >= 0 && ri < core_iaf_npmc, 452 ("[core,%d] illegal row-index %d", __LINE__, ri)); 453 454 cc = core_pcpu[cpu]; 455 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 456 457 KASSERT(pm, 458 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 459 460 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 461 v = iaf_reload_count_to_perfctr_value(v); 462 463 wrmsr(IAF_CTRL, 0); /* Turn off fixed counters */ 464 wrmsr(IAF_CTR0 + ri, v); 465 wrmsr(IAF_CTRL, cc->pc_iafctrl); 466 467 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 468 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 469 (uintmax_t) rdmsr(IAF_CTRL), 470 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 471 472 return (0); 473 } 474 475 476 static void 477 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 478 { 479 struct pmc_classdep *pcd; 480 481 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 482 483 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 484 485 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 486 487 pcd->pcd_caps = IAF_PMC_CAPS; 488 pcd->pcd_class = PMC_CLASS_IAF; 489 pcd->pcd_num = npmc; 490 pcd->pcd_ri = md->pmd_npmc; 491 pcd->pcd_width = pmcwidth; 492 493 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 494 pcd->pcd_config_pmc = iaf_config_pmc; 495 pcd->pcd_describe = iaf_describe; 496 pcd->pcd_get_config = iaf_get_config; 497 pcd->pcd_get_msr = iaf_get_msr; 498 pcd->pcd_pcpu_fini = core_pcpu_noop; 499 pcd->pcd_pcpu_init = core_pcpu_noop; 500 pcd->pcd_read_pmc = iaf_read_pmc; 501 pcd->pcd_release_pmc = iaf_release_pmc; 502 pcd->pcd_start_pmc = iaf_start_pmc; 503 pcd->pcd_stop_pmc = iaf_stop_pmc; 504 pcd->pcd_write_pmc = iaf_write_pmc; 505 506 md->pmd_npmc += npmc; 507 } 508 509 /* 510 * Intel programmable PMCs. 511 */ 512 513 /* 514 * Event descriptor tables. 515 * 516 * For each event id, we track: 517 * 518 * 1. The CPUs that the event is valid for. 519 * 520 * 2. If the event uses a fixed UMASK, the value of the umask field. 521 * If the event doesn't use a fixed UMASK, a mask of legal bits 522 * to check against. 523 */ 524 525 struct iap_event_descr { 526 enum pmc_event iap_ev; 527 unsigned char iap_evcode; 528 unsigned char iap_umask; 529 unsigned char iap_flags; 530 }; 531 532 #define IAP_F_CC (1 << 0) /* CPU: Core */ 533 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 534 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 535 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 536 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 537 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 538 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 539 #define IAP_F_FM (1 << 6) /* Fixed mask */ 540 541 #define IAP_F_ALLCPUSCORE2 \ 542 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 543 544 /* Sub fields of UMASK that this event supports. */ 545 #define IAP_M_CORE (1 << 0) /* Core specificity */ 546 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 547 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 548 #define IAP_M_MESI (1 << 3) /* MESI */ 549 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 550 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 551 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 552 553 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 554 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 555 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 556 #define IAP_F_MESI (0xF << 8) /* MESI */ 557 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 558 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 559 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 560 561 #define IAP_PREFETCH_RESERVED (0x2 << 12) 562 #define IAP_CORE_THIS (0x1 << 14) 563 #define IAP_CORE_ALL (0x3 << 14) 564 #define IAP_F_CMASK 0xFF000000 565 566 static struct iap_event_descr iap_events[] = { 567 #undef IAPDESCR 568 #define IAPDESCR(N,EV,UM,FLAGS) { \ 569 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 570 .iap_evcode = (EV), \ 571 .iap_umask = (UM), \ 572 .iap_flags = (FLAGS) \ 573 } 574 575 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 576 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 577 578 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 579 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O), 580 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_WM), 581 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 582 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 583 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 584 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 585 586 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 587 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 588 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 589 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 590 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 591 592 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 593 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O), 594 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM), 595 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), 596 597 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 598 IAP_F_CC2E | IAP_F_CA), 599 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 600 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 601 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 602 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 603 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 604 605 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 606 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_WM), 607 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 608 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 609 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 610 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA), 611 612 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 613 IAP_F_I7 | IAP_F_WM), 614 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 615 IAP_F_I7 | IAP_F_WM), 616 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 617 IAP_F_WM), 618 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 619 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 620 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 621 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 622 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 623 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 624 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 625 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7), 626 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), 627 628 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 629 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 630 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 631 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 632 633 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 634 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 635 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 636 637 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 638 IAP_F_WM), 639 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 640 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 641 642 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 643 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 644 645 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 646 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 647 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 648 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 649 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 650 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 651 652 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 653 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 654 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 655 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 656 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 657 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 658 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 659 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 660 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 661 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 662 663 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 664 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA), 665 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 666 667 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 668 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 669 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 670 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 671 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 672 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 673 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 674 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 675 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 676 677 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 678 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 679 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 680 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 681 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 682 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 683 684 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 685 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 686 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 687 688 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 689 690 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 691 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 692 693 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 694 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 695 IAP_F_I7 | IAP_F_WM), 696 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 697 698 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 699 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 700 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 701 702 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 703 704 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 705 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 706 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 707 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 708 709 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 710 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 711 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 712 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 713 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 714 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 715 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 716 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 717 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 718 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 719 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 720 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 721 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 722 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 723 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 724 725 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 726 727 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 728 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 729 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 730 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 731 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 732 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 733 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 734 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 735 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 736 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 737 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 738 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 739 740 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 741 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 742 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 743 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O), 744 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 745 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 746 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 747 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 748 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 749 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 750 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 751 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 752 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 753 754 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 755 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 756 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 757 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 758 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 759 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 760 761 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 762 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 763 IAP_F_CA | IAP_F_CC2), 764 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 765 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 766 767 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 768 IAP_F_ALLCPUSCORE2), 769 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 770 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 771 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7), 772 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7), 773 774 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 775 IAP_F_ALLCPUSCORE2), 776 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 777 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 778 779 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 780 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 781 782 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 783 784 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 785 IAP_F_I7 | IAP_F_WM), 786 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 787 IAP_F_I7 | IAP_F_WM), 788 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 789 790 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 791 792 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 793 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 794 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 795 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 796 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 797 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 798 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 799 800 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 801 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 802 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 803 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 804 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 805 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 806 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 807 808 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 809 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 810 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 811 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 812 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 813 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 814 815 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 816 IAP_F_I7), 817 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 818 IAP_F_CC2 | IAP_F_I7), 819 820 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 821 822 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 823 824 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 825 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 826 827 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 828 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7), 829 830 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 831 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 832 IAP_F_I7 | IAP_F_WM), 833 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 834 IAP_F_I7 | IAP_F_WM), 835 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM), 836 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 837 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7O), 838 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O), 839 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 840 841 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 842 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 843 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 844 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 845 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 846 847 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 848 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 849 850 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 851 852 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 853 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 854 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 855 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 856 857 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 858 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 859 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 860 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 861 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 862 863 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 864 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 865 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 866 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 867 868 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 869 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 870 871 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 872 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 873 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 874 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 875 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 876 877 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 878 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 879 880 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 881 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 882 883 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 884 IAP_F_CA | IAP_F_CC2), 885 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 886 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 887 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 888 889 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 890 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 891 892 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 893 IAP_F_CA | IAP_F_CC2), 894 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 895 896 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 897 898 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 899 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 900 901 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 902 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 903 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 904 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 905 906 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 907 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 908 909 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 910 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 911 912 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 913 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 914 915 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 916 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 917 918 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 919 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 920 921 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 922 IAP_F_CA | IAP_F_CC2), 923 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 924 925 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 926 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 927 928 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 929 930 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 931 932 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 933 934 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 935 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 936 937 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 938 939 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 940 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 941 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 942 IAP_F_WM), 943 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 944 IAP_F_WM), 945 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 946 947 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 948 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 949 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 950 951 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 952 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 953 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 954 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 955 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 956 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 957 958 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 959 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 960 961 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 962 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 963 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 964 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 965 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O), 966 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O), 967 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O), 968 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 969 970 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 971 972 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 973 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 974 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 975 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 976 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 977 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 978 979 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 980 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 981 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 982 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 983 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 984 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 985 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 986 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 987 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 988 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 989 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 990 991 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 992 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 993 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 994 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 995 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 996 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 997 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 998 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 999 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1000 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1001 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1002 1003 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1004 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1005 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1006 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1007 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1008 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1009 1010 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1011 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1012 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1013 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1014 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1015 1016 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1017 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1018 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1019 1020 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1021 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1022 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1023 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1024 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1025 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1026 1027 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1028 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1029 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1030 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1031 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1032 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1033 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1034 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1035 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1036 1037 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1038 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1039 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1040 1041 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1042 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1043 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1044 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1045 1046 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1047 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1048 1049 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1050 1051 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1052 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1053 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1054 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1055 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1056 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1057 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1058 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1059 1060 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1061 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1062 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1063 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1064 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1065 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1066 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1067 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1068 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1069 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1070 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1071 IAP_F_WM), 1072 1073 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1074 1075 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1076 IAP_F_WM | IAP_F_I7O), 1077 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1078 IAP_F_WM | IAP_F_I7O), 1079 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1080 IAP_F_WM | IAP_F_I7O), 1081 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1082 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1083 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1084 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1085 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1086 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1087 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1088 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1089 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1090 1091 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1092 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1093 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1094 1095 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1096 1097 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1098 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1099 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1100 1101 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1102 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1103 1104 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1105 1106 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1107 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1108 IAP_F_I7 | IAP_F_WM), 1109 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1110 IAP_F_I7 | IAP_F_WM), 1111 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1112 IAP_F_I7 | IAP_F_WM), 1113 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1114 1115 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1116 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1117 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1118 1119 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1120 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1121 IAP_F_I7 | IAP_F_WM), 1122 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1123 IAP_F_I7 | IAP_F_WM), 1124 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1125 IAP_F_I7 | IAP_F_WM), 1126 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1127 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1128 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1129 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 1130 1131 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1132 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1133 IAP_F_I7 | IAP_F_WM), 1134 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1135 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1136 IAP_F_I7 | IAP_F_WM), 1137 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1138 1139 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1140 IAP_F_I7 | IAP_F_WM), 1141 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1142 IAP_F_I7 | IAP_F_WM), 1143 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1144 IAP_F_I7 | IAP_F_WM), 1145 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1146 IAP_F_I7 | IAP_F_WM), 1147 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1148 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1149 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1150 1151 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1152 IAP_F_I7 | IAP_F_WM), 1153 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM), 1154 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1155 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM), 1156 1157 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1158 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1159 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1160 1161 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1162 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1163 IAP_F_I7 | IAP_F_WM), 1164 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1165 IAP_F_I7 | IAP_F_WM), 1166 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1167 IAP_F_I7 | IAP_F_WM), 1168 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1169 IAP_F_I7 | IAP_F_WM), 1170 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1171 IAP_F_I7 | IAP_F_WM), 1172 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1173 1174 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1175 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1176 1177 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1178 1179 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1180 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1181 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1182 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1183 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1184 1185 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1186 IAP_F_I7 | IAP_F_WM), 1187 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1188 IAP_F_I7 | IAP_F_WM), 1189 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1190 IAP_F_I7 | IAP_F_WM), 1191 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1192 IAP_F_I7 | IAP_F_WM), 1193 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1194 IAP_F_WM), 1195 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1196 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1197 1198 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1199 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1200 IAP_F_I7 | IAP_F_WM), 1201 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1202 IAP_F_I7 | IAP_F_WM), 1203 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1204 1205 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1206 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1207 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1208 1209 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1210 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1211 1212 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM), 1213 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1214 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1215 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1216 1217 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1218 IAP_F_I7 | IAP_F_WM), 1219 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1220 IAP_F_I7 | IAP_F_WM), 1221 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1222 IAP_F_I7 | IAP_F_WM), 1223 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1224 IAP_F_I7 | IAP_F_WM), 1225 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1226 IAP_F_I7 | IAP_F_WM), 1227 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1228 1229 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1230 IAP_F_I7 | IAP_F_WM), 1231 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1232 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1233 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1234 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1235 1236 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1237 IAP_F_I7 | IAP_F_WM), 1238 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1239 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1240 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1241 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1242 1243 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1244 1245 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1246 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1247 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1248 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1249 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1250 1251 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1252 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1253 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1254 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1255 1256 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1257 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1258 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1259 1260 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1261 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1262 1263 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1264 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1265 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1266 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1267 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1268 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1269 1270 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1271 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1272 IAP_F_WM), 1273 1274 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1275 1276 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1277 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1278 1279 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1280 1281 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1282 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1283 IAP_F_WM), 1284 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1285 1286 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1287 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1288 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7), 1289 1290 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1291 1292 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1293 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1294 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1295 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1296 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1297 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1298 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1299 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1300 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1301 1302 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1303 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1304 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1305 1306 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1307 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1308 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1309 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1310 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1311 1312 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1313 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1314 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1315 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1316 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1317 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1318 1319 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1320 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1321 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1322 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1323 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1324 1325 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1326 1327 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1328 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1329 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1330 1331 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1332 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1333 1334 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1335 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1336 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1337 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1338 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1339 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1340 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1341 }; 1342 1343 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1344 1345 static pmc_value_t 1346 iap_perfctr_value_to_reload_count(pmc_value_t v) 1347 { 1348 v &= (1ULL << core_iap_width) - 1; 1349 return (1ULL << core_iap_width) - v; 1350 } 1351 1352 static pmc_value_t 1353 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1354 { 1355 return (1ULL << core_iap_width) - rlc; 1356 } 1357 1358 static int 1359 iap_pmc_has_overflowed(int ri) 1360 { 1361 uint64_t v; 1362 1363 /* 1364 * We treat a Core (i.e., Intel architecture v1) PMC as has 1365 * having overflowed if its MSB is zero. 1366 */ 1367 v = rdpmc(ri); 1368 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1369 } 1370 1371 /* 1372 * Check an event against the set of supported architectural events. 1373 * 1374 * Returns 1 if the event is architectural and unsupported on this 1375 * CPU. Returns 0 otherwise. 1376 */ 1377 1378 static int 1379 iap_architectural_event_is_unsupported(enum pmc_event pe) 1380 { 1381 enum core_arch_events ae; 1382 1383 switch (pe) { 1384 case PMC_EV_IAP_EVENT_3CH_00H: 1385 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1386 break; 1387 case PMC_EV_IAP_EVENT_C0H_00H: 1388 ae = CORE_AE_INSTRUCTION_RETIRED; 1389 break; 1390 case PMC_EV_IAP_EVENT_3CH_01H: 1391 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1392 break; 1393 case PMC_EV_IAP_EVENT_2EH_4FH: 1394 ae = CORE_AE_LLC_REFERENCE; 1395 break; 1396 case PMC_EV_IAP_EVENT_2EH_41H: 1397 ae = CORE_AE_LLC_MISSES; 1398 break; 1399 case PMC_EV_IAP_EVENT_C4H_00H: 1400 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1401 break; 1402 case PMC_EV_IAP_EVENT_C5H_00H: 1403 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1404 break; 1405 1406 default: /* Non architectural event. */ 1407 return (0); 1408 } 1409 1410 return ((core_architectural_events & (1 << ae)) == 0); 1411 } 1412 1413 static int 1414 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1415 { 1416 uint32_t mask; 1417 1418 switch (pe) { 1419 /* 1420 * Events valid only on counter 0, 1. 1421 */ 1422 case PMC_EV_IAP_EVENT_40H_01H: 1423 case PMC_EV_IAP_EVENT_40H_02H: 1424 case PMC_EV_IAP_EVENT_40H_04H: 1425 case PMC_EV_IAP_EVENT_40H_08H: 1426 case PMC_EV_IAP_EVENT_40H_0FH: 1427 case PMC_EV_IAP_EVENT_41H_02H: 1428 case PMC_EV_IAP_EVENT_41H_04H: 1429 case PMC_EV_IAP_EVENT_41H_08H: 1430 case PMC_EV_IAP_EVENT_42H_01H: 1431 case PMC_EV_IAP_EVENT_42H_02H: 1432 case PMC_EV_IAP_EVENT_42H_04H: 1433 case PMC_EV_IAP_EVENT_42H_08H: 1434 case PMC_EV_IAP_EVENT_43H_01H: 1435 case PMC_EV_IAP_EVENT_43H_02H: 1436 case PMC_EV_IAP_EVENT_48H_02H: 1437 case PMC_EV_IAP_EVENT_51H_01H: 1438 case PMC_EV_IAP_EVENT_51H_02H: 1439 case PMC_EV_IAP_EVENT_51H_04H: 1440 case PMC_EV_IAP_EVENT_51H_08H: 1441 case PMC_EV_IAP_EVENT_63H_01H: 1442 case PMC_EV_IAP_EVENT_63H_02H: 1443 mask = 0x3; 1444 break; 1445 1446 default: 1447 mask = ~0; /* Any row index is ok. */ 1448 } 1449 1450 return (mask & (1 << ri)); 1451 } 1452 1453 static int 1454 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1455 { 1456 uint32_t mask; 1457 1458 switch (pe) { 1459 /* 1460 * Events valid only on counter 0. 1461 */ 1462 case PMC_EV_IAP_EVENT_B3H_01H: 1463 case PMC_EV_IAP_EVENT_B3H_02H: 1464 case PMC_EV_IAP_EVENT_B3H_04H: 1465 mask = 0x1; 1466 break; 1467 1468 /* 1469 * Events valid only on counter 0, 1. 1470 */ 1471 case PMC_EV_IAP_EVENT_51H_01H: 1472 case PMC_EV_IAP_EVENT_51H_02H: 1473 case PMC_EV_IAP_EVENT_51H_04H: 1474 case PMC_EV_IAP_EVENT_51H_08H: 1475 case PMC_EV_IAP_EVENT_63H_01H: 1476 case PMC_EV_IAP_EVENT_63H_02H: 1477 mask = 0x3; 1478 break; 1479 1480 default: 1481 mask = ~0; /* Any row index is ok. */ 1482 } 1483 1484 return (mask & (1 << ri)); 1485 } 1486 1487 static int 1488 iap_event_ok_on_counter(enum pmc_event pe, int ri) 1489 { 1490 uint32_t mask; 1491 1492 switch (pe) { 1493 /* 1494 * Events valid only on counter 0. 1495 */ 1496 case PMC_EV_IAP_EVENT_10H_00H: 1497 case PMC_EV_IAP_EVENT_14H_00H: 1498 case PMC_EV_IAP_EVENT_18H_00H: 1499 case PMC_EV_IAP_EVENT_B3H_01H: 1500 case PMC_EV_IAP_EVENT_B3H_02H: 1501 case PMC_EV_IAP_EVENT_B3H_04H: 1502 case PMC_EV_IAP_EVENT_C1H_00H: 1503 case PMC_EV_IAP_EVENT_CBH_01H: 1504 case PMC_EV_IAP_EVENT_CBH_02H: 1505 mask = (1 << 0); 1506 break; 1507 1508 /* 1509 * Events valid only on counter 1. 1510 */ 1511 case PMC_EV_IAP_EVENT_11H_00H: 1512 case PMC_EV_IAP_EVENT_12H_00H: 1513 case PMC_EV_IAP_EVENT_13H_00H: 1514 mask = (1 << 1); 1515 break; 1516 1517 default: 1518 mask = ~0; /* Any row index is ok. */ 1519 } 1520 1521 return (mask & (1 << ri)); 1522 } 1523 1524 static int 1525 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1526 const struct pmc_op_pmcallocate *a) 1527 { 1528 int n; 1529 enum pmc_event ev; 1530 struct iap_event_descr *ie; 1531 uint32_t c, caps, config, cpuflag, evsel, mask; 1532 1533 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1534 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1535 KASSERT(ri >= 0 && ri < core_iap_npmc, 1536 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1537 1538 /* check requested capabilities */ 1539 caps = a->pm_caps; 1540 if ((IAP_PMC_CAPS & caps) != caps) 1541 return (EPERM); 1542 1543 ev = pm->pm_event; 1544 1545 if (iap_architectural_event_is_unsupported(ev)) 1546 return (EOPNOTSUPP); 1547 1548 switch (core_cputype) { 1549 case PMC_CPU_INTEL_COREI7: 1550 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 1551 return (EINVAL); 1552 break; 1553 case PMC_CPU_INTEL_WESTMERE: 1554 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 1555 return (EINVAL); 1556 break; 1557 default: 1558 if (iap_event_ok_on_counter(ev, ri) == 0) 1559 return (EINVAL); 1560 } 1561 1562 /* 1563 * Look for an event descriptor with matching CPU and event id 1564 * fields. 1565 */ 1566 1567 switch (core_cputype) { 1568 default: 1569 case PMC_CPU_INTEL_ATOM: 1570 cpuflag = IAP_F_CA; 1571 break; 1572 case PMC_CPU_INTEL_CORE: 1573 cpuflag = IAP_F_CC; 1574 break; 1575 case PMC_CPU_INTEL_CORE2: 1576 cpuflag = IAP_F_CC2; 1577 break; 1578 case PMC_CPU_INTEL_CORE2EXTREME: 1579 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1580 break; 1581 case PMC_CPU_INTEL_COREI7: 1582 cpuflag = IAP_F_I7; 1583 break; 1584 case PMC_CPU_INTEL_WESTMERE: 1585 cpuflag = IAP_F_WM; 1586 break; 1587 } 1588 1589 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 1590 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 1591 break; 1592 1593 if (n == niap_events) 1594 return (EINVAL); 1595 1596 /* 1597 * A matching event descriptor has been found, so start 1598 * assembling the contents of the event select register. 1599 */ 1600 evsel = ie->iap_evcode; 1601 1602 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 1603 1604 /* 1605 * If the event uses a fixed umask value, reject any umask 1606 * bits set by the user. 1607 */ 1608 if (ie->iap_flags & IAP_F_FM) { 1609 1610 if (IAP_UMASK(config) != 0) 1611 return (EINVAL); 1612 1613 evsel |= (ie->iap_umask << 8); 1614 1615 } else { 1616 1617 /* 1618 * Otherwise, the UMASK value needs to be taken from 1619 * the MD fields of the allocation request. Reject 1620 * requests that specify reserved bits. 1621 */ 1622 1623 mask = 0; 1624 1625 if (ie->iap_umask & IAP_M_CORE) { 1626 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 1627 c != IAP_CORE_THIS) 1628 return (EINVAL); 1629 mask |= IAP_F_CORE; 1630 } 1631 1632 if (ie->iap_umask & IAP_M_AGENT) 1633 mask |= IAP_F_AGENT; 1634 1635 if (ie->iap_umask & IAP_M_PREFETCH) { 1636 1637 if ((c = (config & IAP_F_PREFETCH)) == 1638 IAP_PREFETCH_RESERVED) 1639 return (EINVAL); 1640 1641 mask |= IAP_F_PREFETCH; 1642 } 1643 1644 if (ie->iap_umask & IAP_M_MESI) 1645 mask |= IAP_F_MESI; 1646 1647 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 1648 mask |= IAP_F_SNOOPRESPONSE; 1649 1650 if (ie->iap_umask & IAP_M_SNOOPTYPE) 1651 mask |= IAP_F_SNOOPTYPE; 1652 1653 if (ie->iap_umask & IAP_M_TRANSITION) 1654 mask |= IAP_F_TRANSITION; 1655 1656 /* 1657 * If bits outside of the allowed set of umask bits 1658 * are set, reject the request. 1659 */ 1660 if (config & ~mask) 1661 return (EINVAL); 1662 1663 evsel |= (config & mask); 1664 1665 } 1666 1667 /* 1668 * Only Atom CPUs support the 'ANY' qualifier. 1669 */ 1670 if (core_cputype == PMC_CPU_INTEL_ATOM) 1671 evsel |= (config & IAP_ANY); 1672 else if (config & IAP_ANY) 1673 return (EINVAL); 1674 1675 /* 1676 * Check offcore response configuration. 1677 */ 1678 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 1679 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 1680 ev != PMC_EV_IAP_EVENT_BBH_01H) 1681 return (EINVAL); 1682 if (core_cputype == PMC_CPU_INTEL_COREI7 && 1683 ev == PMC_EV_IAP_EVENT_BBH_01H) 1684 return (EINVAL); 1685 if ( a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK) 1686 return (EINVAL); 1687 pm->pm_md.pm_iap.pm_iap_rsp = 1688 a->pm_md.pm_iap.pm_iap_rsp & IA_OFFCORE_RSP_MASK; 1689 } 1690 1691 if (caps & PMC_CAP_THRESHOLD) 1692 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 1693 if (caps & PMC_CAP_USER) 1694 evsel |= IAP_USR; 1695 if (caps & PMC_CAP_SYSTEM) 1696 evsel |= IAP_OS; 1697 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 1698 evsel |= (IAP_OS | IAP_USR); 1699 if (caps & PMC_CAP_EDGE) 1700 evsel |= IAP_EDGE; 1701 if (caps & PMC_CAP_INVERT) 1702 evsel |= IAP_INV; 1703 if (caps & PMC_CAP_INTERRUPT) 1704 evsel |= IAP_INT; 1705 1706 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 1707 1708 return (0); 1709 } 1710 1711 static int 1712 iap_config_pmc(int cpu, int ri, struct pmc *pm) 1713 { 1714 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1715 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1716 1717 KASSERT(ri >= 0 && ri < core_iap_npmc, 1718 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1719 1720 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 1721 1722 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 1723 cpu)); 1724 1725 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 1726 1727 return (0); 1728 } 1729 1730 static int 1731 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 1732 { 1733 int error; 1734 struct pmc_hw *phw; 1735 char iap_name[PMC_NAME_MAX]; 1736 1737 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 1738 1739 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 1740 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 1741 NULL)) != 0) 1742 return (error); 1743 1744 pi->pm_class = PMC_CLASS_IAP; 1745 1746 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 1747 pi->pm_enabled = TRUE; 1748 *ppmc = phw->phw_pmc; 1749 } else { 1750 pi->pm_enabled = FALSE; 1751 *ppmc = NULL; 1752 } 1753 1754 return (0); 1755 } 1756 1757 static int 1758 iap_get_config(int cpu, int ri, struct pmc **ppm) 1759 { 1760 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1761 1762 return (0); 1763 } 1764 1765 static int 1766 iap_get_msr(int ri, uint32_t *msr) 1767 { 1768 KASSERT(ri >= 0 && ri < core_iap_npmc, 1769 ("[iap,%d] ri %d out of range", __LINE__, ri)); 1770 1771 *msr = ri; 1772 1773 return (0); 1774 } 1775 1776 static int 1777 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 1778 { 1779 struct pmc *pm; 1780 pmc_value_t tmp; 1781 1782 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1783 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1784 KASSERT(ri >= 0 && ri < core_iap_npmc, 1785 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1786 1787 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 1788 1789 KASSERT(pm, 1790 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 1791 ri)); 1792 1793 tmp = rdpmc(ri); 1794 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1795 *v = iap_perfctr_value_to_reload_count(tmp); 1796 else 1797 *v = tmp; 1798 1799 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 1800 ri, *v); 1801 1802 return (0); 1803 } 1804 1805 static int 1806 iap_release_pmc(int cpu, int ri, struct pmc *pm) 1807 { 1808 (void) pm; 1809 1810 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 1811 pm); 1812 1813 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1814 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1815 KASSERT(ri >= 0 && ri < core_iap_npmc, 1816 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1817 1818 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 1819 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 1820 1821 return (0); 1822 } 1823 1824 static int 1825 iap_start_pmc(int cpu, int ri) 1826 { 1827 struct pmc *pm; 1828 uint32_t evsel; 1829 struct core_cpu *cc; 1830 1831 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1832 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 1833 KASSERT(ri >= 0 && ri < core_iap_npmc, 1834 ("[core,%d] illegal row-index %d", __LINE__, ri)); 1835 1836 cc = core_pcpu[cpu]; 1837 pm = cc->pc_corepmcs[ri].phw_pmc; 1838 1839 KASSERT(pm, 1840 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 1841 __LINE__, cpu, ri)); 1842 1843 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 1844 1845 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 1846 1847 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 1848 cpu, ri, IAP_EVSEL0 + ri, evsel); 1849 1850 /* Event specific configuration. */ 1851 switch (pm->pm_event) { 1852 case PMC_EV_IAP_EVENT_B7H_01H: 1853 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 1854 break; 1855 case PMC_EV_IAP_EVENT_BBH_01H: 1856 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 1857 break; 1858 default: 1859 break; 1860 } 1861 1862 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 1863 1864 if (core_cputype == PMC_CPU_INTEL_CORE) 1865 return (0); 1866 1867 do { 1868 cc->pc_resync = 0; 1869 cc->pc_globalctrl |= (1ULL << ri); 1870 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1871 } while (cc->pc_resync != 0); 1872 1873 return (0); 1874 } 1875 1876 static int 1877 iap_stop_pmc(int cpu, int ri) 1878 { 1879 struct pmc *pm; 1880 struct core_cpu *cc; 1881 1882 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1883 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1884 KASSERT(ri >= 0 && ri < core_iap_npmc, 1885 ("[core,%d] illegal row index %d", __LINE__, ri)); 1886 1887 cc = core_pcpu[cpu]; 1888 pm = cc->pc_corepmcs[ri].phw_pmc; 1889 1890 KASSERT(pm, 1891 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1892 cpu, ri)); 1893 1894 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 1895 1896 wrmsr(IAP_EVSEL0 + ri, 0); /* stop hw */ 1897 1898 if (core_cputype == PMC_CPU_INTEL_CORE) 1899 return (0); 1900 1901 do { 1902 cc->pc_resync = 0; 1903 cc->pc_globalctrl &= ~(1ULL << ri); 1904 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 1905 } while (cc->pc_resync != 0); 1906 1907 return (0); 1908 } 1909 1910 static int 1911 iap_write_pmc(int cpu, int ri, pmc_value_t v) 1912 { 1913 struct pmc *pm; 1914 struct core_cpu *cc; 1915 1916 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1917 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 1918 KASSERT(ri >= 0 && ri < core_iap_npmc, 1919 ("[core,%d] illegal row index %d", __LINE__, ri)); 1920 1921 cc = core_pcpu[cpu]; 1922 pm = cc->pc_corepmcs[ri].phw_pmc; 1923 1924 KASSERT(pm, 1925 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 1926 cpu, ri)); 1927 1928 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 1929 IAP_PMC0 + ri, v); 1930 1931 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 1932 v = iap_reload_count_to_perfctr_value(v); 1933 1934 /* 1935 * Write the new value to the counter. The counter will be in 1936 * a stopped state when the pcd_write() entry point is called. 1937 */ 1938 1939 wrmsr(IAP_PMC0 + ri, v); 1940 1941 return (0); 1942 } 1943 1944 1945 static void 1946 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 1947 int flags) 1948 { 1949 struct pmc_classdep *pcd; 1950 1951 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 1952 1953 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 1954 1955 /* Remember the set of architectural events supported. */ 1956 core_architectural_events = ~flags; 1957 1958 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 1959 1960 pcd->pcd_caps = IAP_PMC_CAPS; 1961 pcd->pcd_class = PMC_CLASS_IAP; 1962 pcd->pcd_num = npmc; 1963 pcd->pcd_ri = md->pmd_npmc; 1964 pcd->pcd_width = pmcwidth; 1965 1966 pcd->pcd_allocate_pmc = iap_allocate_pmc; 1967 pcd->pcd_config_pmc = iap_config_pmc; 1968 pcd->pcd_describe = iap_describe; 1969 pcd->pcd_get_config = iap_get_config; 1970 pcd->pcd_get_msr = iap_get_msr; 1971 pcd->pcd_pcpu_fini = core_pcpu_fini; 1972 pcd->pcd_pcpu_init = core_pcpu_init; 1973 pcd->pcd_read_pmc = iap_read_pmc; 1974 pcd->pcd_release_pmc = iap_release_pmc; 1975 pcd->pcd_start_pmc = iap_start_pmc; 1976 pcd->pcd_stop_pmc = iap_stop_pmc; 1977 pcd->pcd_write_pmc = iap_write_pmc; 1978 1979 md->pmd_npmc += npmc; 1980 } 1981 1982 static int 1983 core_intr(int cpu, struct trapframe *tf) 1984 { 1985 pmc_value_t v; 1986 struct pmc *pm; 1987 struct core_cpu *cc; 1988 int error, found_interrupt, ri; 1989 1990 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 1991 TRAPF_USERMODE(tf)); 1992 1993 found_interrupt = 0; 1994 cc = core_pcpu[cpu]; 1995 1996 for (ri = 0; ri < core_iap_npmc; ri++) { 1997 1998 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 1999 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2000 continue; 2001 2002 if (!iap_pmc_has_overflowed(ri)) 2003 continue; 2004 2005 found_interrupt = 1; 2006 2007 if (pm->pm_state != PMC_STATE_RUNNING) 2008 continue; 2009 2010 error = pmc_process_interrupt(cpu, pm, tf, 2011 TRAPF_USERMODE(tf)); 2012 2013 v = pm->pm_sc.pm_reloadcount; 2014 v = iaf_reload_count_to_perfctr_value(v); 2015 2016 /* 2017 * Stop the counter, reload it but only restart it if 2018 * the PMC is not stalled. 2019 */ 2020 wrmsr(IAP_EVSEL0 + ri, 0); 2021 wrmsr(IAP_PMC0 + ri, v); 2022 2023 if (error) 2024 continue; 2025 2026 wrmsr(IAP_EVSEL0 + ri, 2027 pm->pm_md.pm_iap.pm_iap_evsel | IAP_EN); 2028 } 2029 2030 if (found_interrupt) 2031 lapic_reenable_pmc(); 2032 2033 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2034 &pmc_stats.pm_intr_ignored, 1); 2035 2036 return (found_interrupt); 2037 } 2038 2039 static int 2040 core2_intr(int cpu, struct trapframe *tf) 2041 { 2042 int error, found_interrupt, n; 2043 uint64_t flag, intrstatus, intrenable; 2044 struct pmc *pm; 2045 struct core_cpu *cc; 2046 pmc_value_t v; 2047 2048 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2049 TRAPF_USERMODE(tf)); 2050 2051 /* 2052 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2053 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2054 * the current set of interrupting PMCs and process these 2055 * after stopping them. 2056 */ 2057 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2058 intrenable = intrstatus & core_pmcmask; 2059 2060 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2061 (uintmax_t) intrstatus); 2062 2063 found_interrupt = 0; 2064 cc = core_pcpu[cpu]; 2065 2066 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2067 2068 cc->pc_globalctrl &= ~intrenable; 2069 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2070 2071 /* 2072 * Stop PMCs and clear overflow status bits. 2073 */ 2074 wrmsr(IA_GLOBAL_CTRL, 0); 2075 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2076 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2077 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2078 2079 /* 2080 * Look for interrupts from fixed function PMCs. 2081 */ 2082 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2083 n++, flag <<= 1) { 2084 2085 if ((intrstatus & flag) == 0) 2086 continue; 2087 2088 found_interrupt = 1; 2089 2090 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2091 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2092 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2093 continue; 2094 2095 error = pmc_process_interrupt(cpu, pm, tf, 2096 TRAPF_USERMODE(tf)); 2097 if (error) 2098 intrenable &= ~flag; 2099 2100 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2101 2102 /* Reload sampling count. */ 2103 wrmsr(IAF_CTR0 + n, v); 2104 2105 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 2106 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2107 } 2108 2109 /* 2110 * Process interrupts from the programmable counters. 2111 */ 2112 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2113 if ((intrstatus & flag) == 0) 2114 continue; 2115 2116 found_interrupt = 1; 2117 2118 pm = cc->pc_corepmcs[n].phw_pmc; 2119 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2120 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2121 continue; 2122 2123 error = pmc_process_interrupt(cpu, pm, tf, 2124 TRAPF_USERMODE(tf)); 2125 if (error) 2126 intrenable &= ~flag; 2127 2128 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2129 2130 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2131 (uintmax_t) v); 2132 2133 /* Reload sampling count. */ 2134 wrmsr(IAP_PMC0 + n, v); 2135 } 2136 2137 /* 2138 * Reenable all non-stalled PMCs. 2139 */ 2140 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2141 (uintmax_t) intrenable); 2142 2143 cc->pc_globalctrl |= intrenable; 2144 2145 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2146 2147 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2148 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2149 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2150 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2151 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2152 2153 if (found_interrupt) 2154 lapic_reenable_pmc(); 2155 2156 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2157 &pmc_stats.pm_intr_ignored, 1); 2158 2159 return (found_interrupt); 2160 } 2161 2162 int 2163 pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 2164 { 2165 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2166 int ipa_version, flags, nflags; 2167 2168 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2169 2170 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 2171 2172 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2173 md->pmd_cputype, maxcpu, ipa_version); 2174 2175 if (ipa_version < 1 || ipa_version > 3) /* Unknown PMC architecture. */ 2176 return (EPROGMISMATCH); 2177 2178 core_cputype = md->pmd_cputype; 2179 2180 core_pmcmask = 0; 2181 2182 /* 2183 * Initialize programmable counters. 2184 */ 2185 KASSERT(ipa_version >= 1, 2186 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 2187 2188 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2189 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2190 2191 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2192 2193 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2194 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2195 2196 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2197 2198 /* 2199 * Initialize fixed function counters, if present. 2200 */ 2201 if (core_cputype != PMC_CPU_INTEL_CORE) { 2202 KASSERT(ipa_version >= 2, 2203 ("[core,%d] ipa_version %d too small", __LINE__, 2204 ipa_version)); 2205 2206 core_iaf_ri = core_iap_npmc; 2207 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2208 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2209 2210 if (core_iaf_npmc > 0) { 2211 iaf_initialize(md, maxcpu, core_iaf_npmc, 2212 core_iaf_width); 2213 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << 2214 IAF_OFFSET; 2215 } else { 2216 /* 2217 * Adjust the number of classes exported to 2218 * user space. 2219 */ 2220 md->pmd_nclass--; 2221 KASSERT(md->pmd_nclass == 2, 2222 ("[core,%d] unexpected nclass %d", __LINE__, 2223 md->pmd_nclass)); 2224 } 2225 } 2226 2227 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2228 core_iaf_ri); 2229 2230 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 2231 M_ZERO | M_WAITOK); 2232 2233 /* 2234 * Choose the appropriate interrupt handler. 2235 */ 2236 if (ipa_version == 1) 2237 md->pmd_intr = core_intr; 2238 else 2239 md->pmd_intr = core2_intr; 2240 2241 md->pmd_pcpu_fini = NULL; 2242 md->pmd_pcpu_init = NULL; 2243 2244 return (0); 2245 } 2246 2247 void 2248 pmc_core_finalize(struct pmc_mdep *md) 2249 { 2250 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2251 2252 free(core_pcpu, M_PMC); 2253 core_pcpu = NULL; 2254 } 2255