1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #if (__FreeBSD_version >= 1100000) 42 #include <x86/apicvar.h> 43 #else 44 #include <machine/apicvar.h> 45 #endif 46 #include <machine/cpu.h> 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #define CORE_CPUID_REQUEST 0xA 52 #define CORE_CPUID_REQUEST_SIZE 0x4 53 #define CORE_CPUID_EAX 0x0 54 #define CORE_CPUID_EBX 0x1 55 #define CORE_CPUID_ECX 0x2 56 #define CORE_CPUID_EDX 0x3 57 58 #define IAF_PMC_CAPS \ 59 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 60 PMC_CAP_USER | PMC_CAP_SYSTEM) 61 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 62 63 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 64 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 65 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 66 67 #define EV_IS_NOTARCH 0 68 #define EV_IS_ARCH_SUPP 1 69 #define EV_IS_ARCH_NOTSUPP -1 70 71 /* 72 * "Architectural" events defined by Intel. The values of these 73 * symbols correspond to positions in the bitmask returned by 74 * the CPUID.0AH instruction. 75 */ 76 enum core_arch_events { 77 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 78 CORE_AE_BRANCH_MISSES_RETIRED = 6, 79 CORE_AE_INSTRUCTION_RETIRED = 1, 80 CORE_AE_LLC_MISSES = 4, 81 CORE_AE_LLC_REFERENCE = 3, 82 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 83 CORE_AE_UNHALTED_CORE_CYCLES = 0 84 }; 85 86 static enum pmc_cputype core_cputype; 87 88 struct core_cpu { 89 volatile uint32_t pc_resync; 90 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 91 volatile uint64_t pc_globalctrl; /* Global control register. */ 92 struct pmc_hw pc_corepmcs[]; 93 }; 94 95 static struct core_cpu **core_pcpu; 96 97 static uint32_t core_architectural_events; 98 static uint64_t core_pmcmask; 99 100 static int core_iaf_ri; /* relative index of fixed counters */ 101 static int core_iaf_width; 102 static int core_iaf_npmc; 103 104 static int core_iap_width; 105 static int core_iap_npmc; 106 static int core_iap_wroffset; 107 108 static int 109 core_pcpu_noop(struct pmc_mdep *md, int cpu) 110 { 111 (void) md; 112 (void) cpu; 113 return (0); 114 } 115 116 static int 117 core_pcpu_init(struct pmc_mdep *md, int cpu) 118 { 119 struct pmc_cpu *pc; 120 struct core_cpu *cc; 121 struct pmc_hw *phw; 122 int core_ri, n, npmc; 123 124 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 125 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 126 127 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu); 128 129 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 130 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 131 132 if (core_cputype != PMC_CPU_INTEL_CORE) 133 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 134 135 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 136 M_PMC, M_WAITOK | M_ZERO); 137 138 core_pcpu[cpu] = cc; 139 pc = pmc_pcpu[cpu]; 140 141 KASSERT(pc != NULL && cc != NULL, 142 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 143 144 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 145 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 146 PMC_PHW_CPU_TO_STATE(cpu) | 147 PMC_PHW_INDEX_TO_STATE(n + core_ri); 148 phw->phw_pmc = NULL; 149 pc->pc_hwpmcs[n + core_ri] = phw; 150 } 151 152 return (0); 153 } 154 155 static int 156 core_pcpu_fini(struct pmc_mdep *md, int cpu) 157 { 158 int core_ri, n, npmc; 159 struct pmc_cpu *pc; 160 struct core_cpu *cc; 161 uint64_t msr = 0; 162 163 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 164 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 165 166 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 167 168 if ((cc = core_pcpu[cpu]) == NULL) 169 return (0); 170 171 core_pcpu[cpu] = NULL; 172 173 pc = pmc_pcpu[cpu]; 174 175 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 176 cpu)); 177 178 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 179 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 180 181 for (n = 0; n < npmc; n++) { 182 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 183 wrmsr(IAP_EVSEL0 + n, msr); 184 } 185 186 if (core_cputype != PMC_CPU_INTEL_CORE) { 187 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 188 wrmsr(IAF_CTRL, msr); 189 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 190 } 191 192 for (n = 0; n < npmc; n++) 193 pc->pc_hwpmcs[n + core_ri] = NULL; 194 195 free(cc, M_PMC); 196 197 return (0); 198 } 199 200 /* 201 * Fixed function counters. 202 */ 203 204 static pmc_value_t 205 iaf_perfctr_value_to_reload_count(pmc_value_t v) 206 { 207 208 /* If the PMC has overflowed, return a reload count of zero. */ 209 if ((v & (1ULL << (core_iaf_width - 1))) == 0) 210 return (0); 211 v &= (1ULL << core_iaf_width) - 1; 212 return (1ULL << core_iaf_width) - v; 213 } 214 215 static pmc_value_t 216 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 217 { 218 return (1ULL << core_iaf_width) - rlc; 219 } 220 221 static int 222 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 223 const struct pmc_op_pmcallocate *a) 224 { 225 enum pmc_event ev; 226 uint32_t caps, flags, validflags; 227 228 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 229 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 230 231 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 232 233 if (ri < 0 || ri > core_iaf_npmc) 234 return (EINVAL); 235 236 caps = a->pm_caps; 237 238 if (a->pm_class != PMC_CLASS_IAF || 239 (caps & IAF_PMC_CAPS) != caps) 240 return (EINVAL); 241 242 ev = pm->pm_event; 243 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 244 return (EINVAL); 245 246 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 247 return (EINVAL); 248 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 249 return (EINVAL); 250 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 251 return (EINVAL); 252 253 flags = a->pm_md.pm_iaf.pm_iaf_flags; 254 255 validflags = IAF_MASK; 256 257 if (core_cputype != PMC_CPU_INTEL_ATOM && 258 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 259 validflags &= ~IAF_ANY; 260 261 if ((flags & ~validflags) != 0) 262 return (EINVAL); 263 264 if (caps & PMC_CAP_INTERRUPT) 265 flags |= IAF_PMI; 266 if (caps & PMC_CAP_SYSTEM) 267 flags |= IAF_OS; 268 if (caps & PMC_CAP_USER) 269 flags |= IAF_USR; 270 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 271 flags |= (IAF_OS | IAF_USR); 272 273 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 274 275 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx", 276 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 277 278 return (0); 279 } 280 281 static int 282 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 283 { 284 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 285 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 286 287 KASSERT(ri >= 0 && ri < core_iaf_npmc, 288 ("[core,%d] illegal row-index %d", __LINE__, ri)); 289 290 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 291 292 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 293 cpu)); 294 295 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 296 297 return (0); 298 } 299 300 static int 301 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 302 { 303 int error; 304 struct pmc_hw *phw; 305 char iaf_name[PMC_NAME_MAX]; 306 307 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 308 309 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 310 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 311 NULL)) != 0) 312 return (error); 313 314 pi->pm_class = PMC_CLASS_IAF; 315 316 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 317 pi->pm_enabled = TRUE; 318 *ppmc = phw->phw_pmc; 319 } else { 320 pi->pm_enabled = FALSE; 321 *ppmc = NULL; 322 } 323 324 return (0); 325 } 326 327 static int 328 iaf_get_config(int cpu, int ri, struct pmc **ppm) 329 { 330 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 331 332 return (0); 333 } 334 335 static int 336 iaf_get_msr(int ri, uint32_t *msr) 337 { 338 KASSERT(ri >= 0 && ri < core_iaf_npmc, 339 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 340 341 *msr = IAF_RI_TO_MSR(ri); 342 343 return (0); 344 } 345 346 static int 347 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 348 { 349 struct pmc *pm; 350 pmc_value_t tmp; 351 352 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 353 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 354 KASSERT(ri >= 0 && ri < core_iaf_npmc, 355 ("[core,%d] illegal row-index %d", __LINE__, ri)); 356 357 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 358 359 KASSERT(pm, 360 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 361 ri, ri + core_iaf_ri)); 362 363 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 364 365 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 366 *v = iaf_perfctr_value_to_reload_count(tmp); 367 else 368 *v = tmp & ((1ULL << core_iaf_width) - 1); 369 370 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 371 IAF_RI_TO_MSR(ri), *v); 372 373 return (0); 374 } 375 376 static int 377 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 378 { 379 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 380 381 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 382 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 383 KASSERT(ri >= 0 && ri < core_iaf_npmc, 384 ("[core,%d] illegal row-index %d", __LINE__, ri)); 385 386 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 387 ("[core,%d] PHW pmc non-NULL", __LINE__)); 388 389 return (0); 390 } 391 392 static int 393 iaf_start_pmc(int cpu, int ri) 394 { 395 struct pmc *pm; 396 struct core_cpu *iafc; 397 uint64_t msr = 0; 398 399 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 400 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 401 KASSERT(ri >= 0 && ri < core_iaf_npmc, 402 ("[core,%d] illegal row-index %d", __LINE__, ri)); 403 404 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 405 406 iafc = core_pcpu[cpu]; 407 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 408 409 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 410 411 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 412 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 413 414 do { 415 iafc->pc_resync = 0; 416 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 417 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 418 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 419 IAF_GLOBAL_CTRL_MASK)); 420 } while (iafc->pc_resync != 0); 421 422 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 423 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 424 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 425 426 return (0); 427 } 428 429 static int 430 iaf_stop_pmc(int cpu, int ri) 431 { 432 uint32_t fc; 433 struct core_cpu *iafc; 434 uint64_t msr = 0; 435 436 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 437 438 iafc = core_pcpu[cpu]; 439 440 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 441 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 442 KASSERT(ri >= 0 && ri < core_iaf_npmc, 443 ("[core,%d] illegal row-index %d", __LINE__, ri)); 444 445 fc = (IAF_MASK << (ri * 4)); 446 447 if (core_cputype != PMC_CPU_INTEL_ATOM && 448 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 449 fc &= ~IAF_ANY; 450 451 iafc->pc_iafctrl &= ~fc; 452 453 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 454 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 455 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 456 457 do { 458 iafc->pc_resync = 0; 459 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 460 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 461 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 462 IAF_GLOBAL_CTRL_MASK)); 463 } while (iafc->pc_resync != 0); 464 465 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 466 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 467 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 468 469 return (0); 470 } 471 472 static int 473 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 474 { 475 struct core_cpu *cc; 476 struct pmc *pm; 477 uint64_t msr; 478 479 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 480 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 481 KASSERT(ri >= 0 && ri < core_iaf_npmc, 482 ("[core,%d] illegal row-index %d", __LINE__, ri)); 483 484 cc = core_pcpu[cpu]; 485 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 486 487 KASSERT(pm, 488 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 489 490 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 491 v = iaf_reload_count_to_perfctr_value(v); 492 493 /* Turn off fixed counters */ 494 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 495 wrmsr(IAF_CTRL, msr); 496 497 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 498 499 /* Turn on fixed counters */ 500 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 501 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 502 503 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 504 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 505 (uintmax_t) rdmsr(IAF_CTRL), 506 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 507 508 return (0); 509 } 510 511 512 static void 513 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 514 { 515 struct pmc_classdep *pcd; 516 517 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 518 519 PMCDBG0(MDP,INI,1, "iaf-initialize"); 520 521 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 522 523 pcd->pcd_caps = IAF_PMC_CAPS; 524 pcd->pcd_class = PMC_CLASS_IAF; 525 pcd->pcd_num = npmc; 526 pcd->pcd_ri = md->pmd_npmc; 527 pcd->pcd_width = pmcwidth; 528 529 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 530 pcd->pcd_config_pmc = iaf_config_pmc; 531 pcd->pcd_describe = iaf_describe; 532 pcd->pcd_get_config = iaf_get_config; 533 pcd->pcd_get_msr = iaf_get_msr; 534 pcd->pcd_pcpu_fini = core_pcpu_noop; 535 pcd->pcd_pcpu_init = core_pcpu_noop; 536 pcd->pcd_read_pmc = iaf_read_pmc; 537 pcd->pcd_release_pmc = iaf_release_pmc; 538 pcd->pcd_start_pmc = iaf_start_pmc; 539 pcd->pcd_stop_pmc = iaf_stop_pmc; 540 pcd->pcd_write_pmc = iaf_write_pmc; 541 542 md->pmd_npmc += npmc; 543 } 544 545 /* 546 * Intel programmable PMCs. 547 */ 548 549 /* 550 * Event descriptor tables. 551 * 552 * For each event id, we track: 553 * 554 * 1. The CPUs that the event is valid for. 555 * 556 * 2. If the event uses a fixed UMASK, the value of the umask field. 557 * If the event doesn't use a fixed UMASK, a mask of legal bits 558 * to check against. 559 */ 560 561 struct iap_event_descr { 562 enum pmc_event iap_ev; 563 unsigned char iap_evcode; 564 unsigned char iap_umask; 565 unsigned int iap_flags; 566 }; 567 568 #define IAP_F_CC (1 << 0) /* CPU: Core */ 569 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 570 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 571 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 572 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 573 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 574 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 575 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 576 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 577 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 578 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ 579 #define IAP_F_HW (1 << 10) /* CPU: Haswell */ 580 #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ 581 #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ 582 #define IAP_F_BW (1 << 13) /* CPU: Broadwell */ 583 #define IAP_F_BWX (1 << 14) /* CPU: Broadwell Xeon */ 584 #define IAP_F_SL (1 << 15) /* CPU: Skylake */ 585 #define IAP_F_FM (1 << 18) /* Fixed mask */ 586 587 #define IAP_F_ALLCPUSCORE2 \ 588 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 589 590 /* Sub fields of UMASK that this event supports. */ 591 #define IAP_M_CORE (1 << 0) /* Core specificity */ 592 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 593 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 594 #define IAP_M_MESI (1 << 3) /* MESI */ 595 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 596 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 597 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 598 599 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 600 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 601 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 602 #define IAP_F_MESI (0xF << 8) /* MESI */ 603 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 604 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 605 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 606 607 #define IAP_PREFETCH_RESERVED (0x2 << 12) 608 #define IAP_CORE_THIS (0x1 << 14) 609 #define IAP_CORE_ALL (0x3 << 14) 610 #define IAP_F_CMASK 0xFF000000 611 612 static struct iap_event_descr iap_events[] = { 613 #undef IAPDESCR 614 #define IAPDESCR(N,EV,UM,FLAGS) { \ 615 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 616 .iap_evcode = (EV), \ 617 .iap_umask = (UM), \ 618 .iap_flags = (FLAGS) \ 619 } 620 621 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 622 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 623 624 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 625 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 626 IAP_F_SBX | IAP_F_CAS), 627 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 628 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 629 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 630 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 631 IAP_F_CAS), 632 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 633 IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 634 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 635 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 636 IAP_F_SBX | IAP_F_CAS), 637 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 638 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_FM | IAP_F_CAS), 639 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_FM | IAP_F_CAS), 640 641 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), 642 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 643 IAP_F_CAS), 644 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 645 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_FM | IAP_F_CAS), 646 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 647 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 648 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_FM | IAP_F_CAS), 649 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_FM | IAP_F_CAS), 650 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_FM | IAP_F_CAS), 651 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_FM | IAP_F_CAS), 652 653 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 654 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 655 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | 656 IAP_F_BWX), 657 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | 658 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | 659 IAP_F_BW | IAP_F_BWX), 660 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), 661 662 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 663 IAP_F_CC2E | IAP_F_CA), 664 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 665 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 666 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 667 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 668 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 669 670 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 671 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 672 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 673 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 674 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 675 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 676 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 677 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 678 IAP_F_SBX), 679 680 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 681 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | 682 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 683 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 684 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | 685 IAP_F_BW | IAP_F_BWX), 686 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 687 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 688 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 689 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 690 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 691 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 692 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 693 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 694 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 695 IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 696 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 697 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 698 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 699 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 700 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 701 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 702 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 703 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 704 IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 705 706 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 707 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 708 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 709 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 710 711 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 712 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 713 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 714 715 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 716 IAP_F_WM | IAP_F_SL), 717 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 718 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 719 720 IAPDESCR(0DH_03H, 0x0D, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | 721 IAP_F_IB | IAP_F_IBX | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 722 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 723 IAPDESCR(0DH_80H, 0x0D, 0x80, IAP_F_FM | IAP_F_SL), 724 725 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 726 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 727 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 728 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SL), 729 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 730 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 731 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 732 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 733 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 734 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 735 736 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 737 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 738 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 739 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 740 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 741 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 742 743 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 744 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 745 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ), 746 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 747 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 748 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 749 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 750 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 751 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 752 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 753 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 754 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 755 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 756 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 757 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 758 759 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 760 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 761 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 762 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 763 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 764 765 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 766 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 767 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 768 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 769 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 770 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 771 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 772 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 773 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 774 775 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 776 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 777 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 778 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 779 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 780 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 781 782 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 783 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 784 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 785 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 786 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 787 788 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 789 IAP_F_SBX), 790 791 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 792 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 793 794 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 795 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 796 IAP_F_I7 | IAP_F_WM), 797 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 798 799 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 800 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 801 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 802 803 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 804 805 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 806 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 807 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 808 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 809 810 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 811 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 812 IAP_F_IB | IAP_F_SBX | IAP_F_IBX ), 813 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 814 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 815 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 816 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 817 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 818 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 819 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 820 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 821 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 822 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 823 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 824 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 825 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 826 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 827 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 828 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 829 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 830 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 831 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 832 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 833 IAP_F_BW | IAP_F_BWX), 834 IAPDESCR(24H_38H, 0x24, 0x38, IAP_F_FM | IAP_F_SL), 835 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 836 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 837 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 838 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 839 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 840 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 841 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 842 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 843 IAP_F_BW | IAP_F_BWX), 844 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 845 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 846 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 847 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 848 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 849 IAPDESCR(24H_D8H, 0x24, 0xD8, IAP_F_FM | IAP_F_SL), 850 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 851 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 852 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 853 IAP_F_SL), 854 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 855 IAP_F_SL), 856 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 857 IAPDESCR(24H_EFH, 0x24, 0xEF, IAP_F_FM | IAP_F_SL), 858 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 859 IAP_F_SL), 860 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 861 IAP_F_HWX), 862 863 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 864 865 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 866 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 867 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 868 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 869 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 870 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 871 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 872 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 873 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 874 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 875 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 876 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 877 878 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 879 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 880 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 881 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 882 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 883 IAP_F_SBX), 884 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 885 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 886 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 887 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 888 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 889 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 890 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 891 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 892 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 893 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 894 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 895 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 896 897 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 898 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 899 IAP_F_SBX | IAP_F_IBX), 900 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 901 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 902 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 903 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 904 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 905 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 906 IAP_F_SBX | IAP_F_IBX), 907 908 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 909 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 910 IAP_F_CA | IAP_F_CC2), 911 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 912 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 913 914 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 915 IAP_F_ALLCPUSCORE2), 916 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 917 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 918 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 919 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 920 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 921 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 922 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 923 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 924 925 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 926 IAP_F_ALLCPUSCORE2), 927 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_FM | IAP_F_CAS), 928 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_FM | IAP_F_CAS), 929 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 930 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 931 932 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 933 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 934 935 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 936 937 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 938 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 939 IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 940 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 941 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 942 IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 943 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_SL), 944 945 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 946 947 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 948 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 949 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 950 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 951 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 952 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 953 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 954 955 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 956 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 957 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 958 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 959 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 960 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 961 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 962 963 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 964 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 965 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 966 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 967 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 968 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 969 970 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 971 IAP_F_I7), 972 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 973 IAP_F_CC2 | IAP_F_I7), 974 975 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 976 977 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 978 979 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 980 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 981 982 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 983 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 984 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 985 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_SL), 986 987 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 988 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 989 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 990 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 991 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 992 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 993 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 994 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 995 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 996 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 997 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 998 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 999 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1000 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX | 1001 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1002 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1003 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1004 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | 1005 IAP_F_HWX), 1006 1007 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1008 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 1009 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1010 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 1011 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 1012 1013 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1014 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1015 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 1016 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1017 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1018 1019 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 1020 1021 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1022 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1023 IAP_F_SB | IAP_F_SBX), 1024 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1025 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1026 1027 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 1028 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 1029 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 1030 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 1031 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1032 1033 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1034 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1035 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1036 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1037 IAP_F_SB | IAP_F_SBX), 1038 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1039 IAP_F_SB | IAP_F_SBX), 1040 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1041 IAP_F_SB | IAP_F_SBX), 1042 1043 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1044 1045 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1046 1047 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1048 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1049 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1050 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1051 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1052 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1053 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1054 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1055 1056 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1057 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1058 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1059 1060 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1061 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1062 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1063 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1064 1065 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1066 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1067 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1068 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1069 1070 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1071 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1072 1073 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */ 1074 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_FM | IAP_F_IBX | IAP_F_IB), 1075 1076 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1077 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1078 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1079 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1080 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1081 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1082 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM |IAP_F_I7O | 1083 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1084 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1085 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM |IAP_F_I7O | 1086 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1087 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1088 IAPDESCR(60H_10H, 0x60, 0x10, IAP_F_FM | IAP_F_SL), 1089 1090 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1091 1092 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1093 1094 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1095 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1096 1097 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1098 IAP_F_CA | IAP_F_CC2), 1099 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1100 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1101 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1102 IAP_F_BW | IAP_F_BWX ), 1103 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1104 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1105 IAP_F_BW | IAP_F_BWX), 1106 1107 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1108 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1109 1110 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1111 IAP_F_CA | IAP_F_CC2), 1112 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1113 1114 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1115 1116 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1117 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1118 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1119 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1120 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1121 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1122 1123 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1124 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1125 1126 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1127 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1128 1129 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1130 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1131 1132 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1133 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1134 1135 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1136 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1137 1138 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1139 IAP_F_CA | IAP_F_CC2), 1140 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1141 1142 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1143 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1144 1145 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1146 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1147 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1148 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1149 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1150 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_BW | IAP_F_BWX), 1151 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1152 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1153 1154 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1155 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1156 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1157 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1158 1159 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1160 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1161 1162 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1163 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1164 1165 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1166 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1167 1168 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1169 1170 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1171 1172 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1173 1174 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1175 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1176 1177 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1178 1179 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1180 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1181 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1182 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1183 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1184 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1185 IAP_F_WM | IAP_F_CAS), 1186 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1187 IAP_F_IBX | IAP_F_SL), /* SL may have a spec bug two with same entry no cmask */ 1188 1189 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1190 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1191 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1192 1193 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1194 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1195 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1196 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1197 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1198 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1199 1200 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SL), 1201 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SL), 1202 1203 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1204 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1205 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1206 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1207 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1208 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1209 IAP_F_BW | IAP_F_BWX), 1210 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1211 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1212 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 1213 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1214 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1215 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX | 1216 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1217 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1218 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1219 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1220 1221 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1222 1223 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1224 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1225 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1226 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1227 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1228 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1229 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1230 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1231 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1232 1233 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1234 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1235 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1236 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1237 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1238 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1239 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1240 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1241 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1242 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1243 IAPDESCR(88H_41H, 0x88, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1244 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1245 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1246 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_BW | IAP_F_BWX), 1247 IAPDESCR(88H_81H, 0x88, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1248 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1249 IAPDESCR(88H_82H, 0x88, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1250 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1251 IAPDESCR(88H_84H, 0x88, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1252 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1253 IAPDESCR(88H_88H, 0x88, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1254 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1255 IAPDESCR(88H_90H, 0x88, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1256 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1257 IAPDESCR(88H_A0H, 0x88, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1258 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1259 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1260 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1261 1262 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1263 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1264 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1265 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1266 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1267 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1268 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1269 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1270 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1271 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1272 IAPDESCR(89H_41H, 0x89, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1273 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1274 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1275 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_BW | IAP_F_BWX), 1276 IAPDESCR(89H_81H, 0x89, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1277 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1278 IAPDESCR(89H_82H, 0x89, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1279 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1280 IAPDESCR(89H_84H, 0x89, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1281 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1282 IAPDESCR(89H_88H, 0x89, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1283 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1284 IAPDESCR(89H_90H, 0x89, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1285 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1286 IAPDESCR(89H_A0H, 0x89, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1287 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1288 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1289 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1290 1291 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1292 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1293 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1294 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1295 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1296 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1297 1298 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1299 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1300 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1301 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1302 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1303 1304 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1305 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1306 1307 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1308 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1309 1310 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1311 1312 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1313 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1314 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1315 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1316 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1317 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1318 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1319 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1320 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1321 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1322 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1323 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1324 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1325 IAP_F_SBX | IAP_F_IBX), 1326 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1327 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1328 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1329 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1330 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1331 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1332 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1333 IAP_F_SBX | IAP_F_IBX), 1334 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1335 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1336 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1337 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1338 1339 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1340 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1341 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1342 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1343 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1344 IAP_F_SB | IAP_F_SBX), 1345 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1346 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1347 IAP_F_BW | IAP_F_BWX), 1348 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1349 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1350 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1351 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1352 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1353 IAP_F_BW | IAP_F_BWX), 1354 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1355 IAP_F_SB | IAP_F_SBX), 1356 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1357 IAP_F_SB | IAP_F_SBX), 1358 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1359 IAP_F_SB | IAP_F_SBX), 1360 1361 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | 1362 IAP_F_HWX | IAP_F_SL), 1363 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | 1364 IAP_F_HWX | IAP_F_SL), 1365 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_SL), 1366 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 1367 IAPDESCR(A3H_06H, 0xA3, 0x06, IAP_F_FM | IAP_F_SL), 1368 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | IAP_F_HWX | 1369 IAP_F_SL), 1370 IAPDESCR(A3H_0CH, 0xA3, 0x0C, IAP_F_FM | IAP_F_HW | IAP_F_HW | IAP_F_SL), 1371 IAPDESCR(A3H_10H, 0xA3, 0x10, IAP_F_FM | IAP_F_SL), 1372 IAPDESCR(A3H_14H, 0xA3, 0x14, IAP_F_FM | IAP_F_SL), 1373 1374 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1375 IAPDESCR(A6H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SL), 1376 IAPDESCR(A6H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SL), 1377 IAPDESCR(A6H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_SL), 1378 IAPDESCR(A6H_10H, 0xA3, 0x10, IAP_F_FM | IAP_F_SL), 1379 IAPDESCR(A6H_40H, 0xA3, 0x40, IAP_F_FM | IAP_F_SL), 1380 1381 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM ), 1382 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX | 1383 IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1384 IAP_F_SL), 1385 1386 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1387 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1388 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1389 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1390 1391 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1392 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1393 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1394 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_BW | IAP_F_BWX), 1395 1396 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_SL), 1397 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1398 IAP_F_SBX | IAP_F_IBX), 1399 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1400 1401 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1402 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1403 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1404 1405 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1406 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1407 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1408 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1409 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1410 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1411 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1412 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1413 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1414 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1415 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1416 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1417 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SL), 1418 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1419 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1420 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O | IAP_F_SL), 1421 1422 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1423 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1424 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1425 IAPDESCR(B1H_02H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1426 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1427 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1428 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1429 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1430 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1431 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1432 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1433 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1434 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1435 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1436 IAP_F_WM), 1437 1438 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1439 IAP_F_SB | IAP_F_SBX), 1440 1441 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1442 IAP_F_WM | IAP_F_I7O), 1443 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1444 IAP_F_WM | IAP_F_I7O), 1445 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1446 IAP_F_WM | IAP_F_I7O), 1447 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1448 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1449 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1450 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1451 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1452 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1453 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1454 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1455 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1456 1457 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1458 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1459 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1460 1461 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1462 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_FM | IAP_F_CAS), 1463 1464 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1465 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | 1466 IAP_F_HWX |IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1467 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), 1468 1469 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1470 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1471 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1472 1473 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1474 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1475 1476 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1477 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1478 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1479 1480 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1481 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1482 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1483 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1484 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1485 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1486 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1487 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1488 1489 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1490 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL), /* spec bug SL? */ 1491 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1492 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1493 1494 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1495 1496 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1497 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1498 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1499 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1500 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1501 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1502 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1503 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_BW | IAP_F_BWX), 1504 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1505 IAP_F_I7 | IAP_F_WM), 1506 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1507 1508 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1509 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1510 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1511 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1512 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1513 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1514 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1515 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1516 IAP_F_SBX | IAP_F_IBX), 1517 IAPDESCR(C1H_3FH, 0xC1, 0x3F, IAP_F_FM | IAP_F_SL), 1518 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1519 IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_FM |IAP_F_IB | IAP_F_IBX), 1520 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1521 1522 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1523 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1524 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1525 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1526 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1527 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1528 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1529 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1530 IAP_F_I7 | IAP_F_WM), 1531 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1532 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1533 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1534 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), 1535 1536 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1537 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1538 IAP_F_I7 | IAP_F_WM | IAP_F_CAS | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1539 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1540 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1541 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1542 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1543 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1544 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1545 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_FM | IAP_F_CAS), 1546 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1547 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1548 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1549 1550 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1551 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1552 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1553 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1554 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1555 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1556 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1557 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1558 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1559 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1560 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1561 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1562 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1563 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1564 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1565 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1566 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1567 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1568 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1569 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1570 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1571 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1572 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1573 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_FM | IAP_F_CAS), 1574 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_FM | IAP_F_CAS), 1575 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_FM | IAP_F_CAS), 1576 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_FM | IAP_F_CAS), 1577 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_FM | IAP_F_CAS), 1578 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_FM | IAP_F_CAS), 1579 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_FM | IAP_F_CAS), 1580 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_FM | IAP_F_CAS), 1581 1582 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1583 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1584 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1585 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1586 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1587 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1588 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SL), 1589 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1590 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1591 IAP_F_SL), 1592 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1593 IAP_F_SBX | IAP_F_IBX), 1594 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1595 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 1596 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_FM | IAP_F_CAS), 1597 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_FM | IAP_F_CAS), 1598 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_FM | IAP_F_CAS), 1599 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_FM | IAP_F_CAS), 1600 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_FM | IAP_F_CAS), 1601 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_FM | IAP_F_CAS), 1602 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_FM | IAP_F_CAS), 1603 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_FM | IAP_F_CAS), 1604 1605 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1606 /* For SL C6_01 needs EV_SEL? 0x11, 0x12, 0x13, 0x14, 0x15? */ 1607 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SL), 1608 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1609 1610 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1611 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1612 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1613 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1614 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1615 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1616 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1617 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1618 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1619 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1620 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1621 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1622 IAPDESCR(C7H_20H, 0xC7, 0x20, IAP_F_FM | IAP_F_SL), 1623 1624 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1625 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1626 1627 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1628 1629 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1630 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 1631 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1632 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1633 IAP_F_BW | IAP_F_BWX), 1634 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1635 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1636 IAP_F_BW | IAP_F_BWX), 1637 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1638 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1639 IAP_F_BW | IAP_F_BWX), 1640 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1641 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1642 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1643 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1644 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_FM | IAP_F_CAS | IAP_F_BW | IAP_F_BWX), 1645 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_FM | IAP_F_CAS), 1646 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_FM | IAP_F_CAS), 1647 1648 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1649 IAP_F_I7 | IAP_F_WM | IAP_F_CAS | IAP_F_SL), 1650 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1651 IAP_F_I7 | IAP_F_WM), 1652 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1653 IAP_F_I7 | IAP_F_WM), 1654 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1655 IAP_F_I7 | IAP_F_WM), 1656 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1657 IAP_F_WM), 1658 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_FM | IAP_F_CAS), 1659 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1660 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1661 1662 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1663 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1664 IAP_F_I7 | IAP_F_WM), 1665 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1666 IAP_F_I7 | IAP_F_WM), 1667 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1668 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1669 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1670 1671 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1672 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1673 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1674 IAP_F_SL), 1675 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1676 IAP_F_SBX | IAP_F_IBX), 1677 1678 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1679 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1680 1681 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ 1682 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1683 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1684 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1685 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1686 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1687 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1688 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_BW | IAP_F_BWX | 1689 IAP_F_SL), 1690 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1691 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1692 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1693 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1694 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1695 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1696 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1697 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1698 1699 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1700 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1701 IAP_F_BWX | IAP_F_SL), 1702 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1703 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1704 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1705 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1706 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1707 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1708 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1709 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1710 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX | 1711 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1712 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1713 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1714 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1715 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1716 1717 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1718 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1719 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1720 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1721 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1722 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1723 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1724 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1725 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1726 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1727 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1728 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1729 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1730 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1731 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1732 1733 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1734 1735 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1736 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1737 IAPDESCR(D3H_03H, 0xD3, 0x03, IAP_F_FM | IAP_F_IBX), 1738 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), /* Not defined for IBX */ 1739 IAPDESCR(D3H_0CH, 0xD3, 0x0C, IAP_F_FM | IAP_F_IBX), 1740 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_FM | IAP_F_IBX ), 1741 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_FM | IAP_F_IBX ), 1742 1743 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1744 IAP_F_I7 | IAP_F_WM), 1745 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1746 IAP_F_SB | IAP_F_SBX), 1747 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1748 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1749 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1750 1751 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1752 IAP_F_I7 | IAP_F_WM), 1753 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1754 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1755 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1756 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1757 1758 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1759 1760 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1761 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1762 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1763 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1764 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1765 1766 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1767 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1768 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1769 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1770 1771 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1772 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1773 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1774 1775 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1776 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1777 1778 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1779 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1780 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1781 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1782 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1783 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1784 1785 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1786 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1787 IAP_F_WM), 1788 1789 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1790 1791 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1792 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1793 1794 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1795 1796 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1797 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1798 IAP_F_WM | IAP_F_SBX | IAP_F_CAS | IAP_F_SL), 1799 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1800 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_FM | IAP_F_CAS), 1801 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_FM | IAP_F_CAS), 1802 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB | 1803 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1804 1805 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_FM | IAP_F_CAS), 1806 1807 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1808 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1809 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1810 1811 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1812 1813 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1814 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1815 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1816 IAP_F_BW | IAP_F_BWX), 1817 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1818 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1819 IAP_F_BW | IAP_F_BWX), 1820 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1821 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1822 IAP_F_BW | IAP_F_BWX), 1823 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1824 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1825 IAP_F_BW | IAP_F_BWX), 1826 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1827 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1828 IAP_F_BW | IAP_F_BWX), 1829 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1830 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1831 IAP_F_BW | IAP_F_BWX), 1832 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1833 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1834 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1835 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1836 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1837 IAP_F_BW | IAP_F_BWX), 1838 1839 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1840 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1841 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1842 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1843 IAP_F_BW | IAP_F_BWX), 1844 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1845 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1846 IAP_F_BW | IAP_F_BWX ), 1847 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1848 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1849 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1850 1851 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1852 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1853 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1854 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1855 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1856 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1857 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1858 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1859 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1860 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1861 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1862 IAP_F_IBX), 1863 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1864 1865 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1866 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1867 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1868 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1869 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1870 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1871 1872 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1873 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1874 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1875 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1876 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1877 IAP_F_SB | IAP_F_SBX), 1878 1879 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1880 1881 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1882 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1883 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1884 1885 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1886 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1887 1888 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1889 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1890 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1891 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1892 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1893 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1894 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1895 }; 1896 1897 static pmc_value_t 1898 iap_perfctr_value_to_reload_count(pmc_value_t v) 1899 { 1900 1901 /* If the PMC has overflowed, return a reload count of zero. */ 1902 if ((v & (1ULL << (core_iap_width - 1))) == 0) 1903 return (0); 1904 v &= (1ULL << core_iap_width) - 1; 1905 return (1ULL << core_iap_width) - v; 1906 } 1907 1908 static pmc_value_t 1909 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1910 { 1911 return (1ULL << core_iap_width) - rlc; 1912 } 1913 1914 static int 1915 iap_pmc_has_overflowed(int ri) 1916 { 1917 uint64_t v; 1918 1919 /* 1920 * We treat a Core (i.e., Intel architecture v1) PMC as has 1921 * having overflowed if its MSB is zero. 1922 */ 1923 v = rdpmc(ri); 1924 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1925 } 1926 1927 /* 1928 * Check an event against the set of supported architectural events. 1929 * 1930 * If the event is not architectural EV_IS_NOTARCH is returned. 1931 * If the event is architectural and supported on this CPU, the correct 1932 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. 1933 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. 1934 */ 1935 1936 static int 1937 iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) 1938 { 1939 enum core_arch_events ae; 1940 1941 switch (pe) { 1942 case PMC_EV_IAP_ARCH_UNH_COR_CYC: 1943 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1944 *map = PMC_EV_IAP_EVENT_3CH_00H; 1945 break; 1946 case PMC_EV_IAP_ARCH_INS_RET: 1947 ae = CORE_AE_INSTRUCTION_RETIRED; 1948 *map = PMC_EV_IAP_EVENT_C0H_00H; 1949 break; 1950 case PMC_EV_IAP_ARCH_UNH_REF_CYC: 1951 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1952 *map = PMC_EV_IAP_EVENT_3CH_01H; 1953 break; 1954 case PMC_EV_IAP_ARCH_LLC_REF: 1955 ae = CORE_AE_LLC_REFERENCE; 1956 *map = PMC_EV_IAP_EVENT_2EH_4FH; 1957 break; 1958 case PMC_EV_IAP_ARCH_LLC_MIS: 1959 ae = CORE_AE_LLC_MISSES; 1960 *map = PMC_EV_IAP_EVENT_2EH_41H; 1961 break; 1962 case PMC_EV_IAP_ARCH_BR_INS_RET: 1963 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1964 *map = PMC_EV_IAP_EVENT_C4H_00H; 1965 break; 1966 case PMC_EV_IAP_ARCH_BR_MIS_RET: 1967 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1968 *map = PMC_EV_IAP_EVENT_C5H_00H; 1969 break; 1970 1971 default: /* Non architectural event. */ 1972 return (EV_IS_NOTARCH); 1973 } 1974 1975 return (((core_architectural_events & (1 << ae)) == 0) ? 1976 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); 1977 } 1978 1979 static int 1980 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1981 { 1982 uint32_t mask; 1983 1984 switch (pe) { 1985 /* 1986 * Events valid only on counter 0, 1. 1987 */ 1988 case PMC_EV_IAP_EVENT_40H_01H: 1989 case PMC_EV_IAP_EVENT_40H_02H: 1990 case PMC_EV_IAP_EVENT_40H_04H: 1991 case PMC_EV_IAP_EVENT_40H_08H: 1992 case PMC_EV_IAP_EVENT_40H_0FH: 1993 case PMC_EV_IAP_EVENT_41H_02H: 1994 case PMC_EV_IAP_EVENT_41H_04H: 1995 case PMC_EV_IAP_EVENT_41H_08H: 1996 case PMC_EV_IAP_EVENT_42H_01H: 1997 case PMC_EV_IAP_EVENT_42H_02H: 1998 case PMC_EV_IAP_EVENT_42H_04H: 1999 case PMC_EV_IAP_EVENT_42H_08H: 2000 case PMC_EV_IAP_EVENT_43H_01H: 2001 case PMC_EV_IAP_EVENT_43H_02H: 2002 case PMC_EV_IAP_EVENT_51H_01H: 2003 case PMC_EV_IAP_EVENT_51H_02H: 2004 case PMC_EV_IAP_EVENT_51H_04H: 2005 case PMC_EV_IAP_EVENT_51H_08H: 2006 case PMC_EV_IAP_EVENT_63H_01H: 2007 case PMC_EV_IAP_EVENT_63H_02H: 2008 mask = 0x3; 2009 break; 2010 2011 default: 2012 mask = ~0; /* Any row index is ok. */ 2013 } 2014 2015 return (mask & (1 << ri)); 2016 } 2017 2018 static int 2019 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 2020 { 2021 uint32_t mask; 2022 2023 switch (pe) { 2024 /* 2025 * Events valid only on counter 0. 2026 */ 2027 case PMC_EV_IAP_EVENT_60H_01H: 2028 case PMC_EV_IAP_EVENT_60H_02H: 2029 case PMC_EV_IAP_EVENT_60H_04H: 2030 case PMC_EV_IAP_EVENT_60H_08H: 2031 case PMC_EV_IAP_EVENT_B3H_01H: 2032 case PMC_EV_IAP_EVENT_B3H_02H: 2033 case PMC_EV_IAP_EVENT_B3H_04H: 2034 mask = 0x1; 2035 break; 2036 2037 /* 2038 * Events valid only on counter 0, 1. 2039 */ 2040 case PMC_EV_IAP_EVENT_4CH_01H: 2041 case PMC_EV_IAP_EVENT_4EH_01H: 2042 case PMC_EV_IAP_EVENT_4EH_02H: 2043 case PMC_EV_IAP_EVENT_4EH_04H: 2044 case PMC_EV_IAP_EVENT_51H_01H: 2045 case PMC_EV_IAP_EVENT_51H_02H: 2046 case PMC_EV_IAP_EVENT_51H_04H: 2047 case PMC_EV_IAP_EVENT_51H_08H: 2048 case PMC_EV_IAP_EVENT_63H_01H: 2049 case PMC_EV_IAP_EVENT_63H_02H: 2050 mask = 0x3; 2051 break; 2052 2053 default: 2054 mask = ~0; /* Any row index is ok. */ 2055 } 2056 2057 return (mask & (1 << ri)); 2058 } 2059 2060 static int 2061 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 2062 { 2063 uint32_t mask; 2064 2065 switch (pe) { 2066 /* Events valid only on counter 0. */ 2067 case PMC_EV_IAP_EVENT_B7H_01H: 2068 mask = 0x1; 2069 break; 2070 /* Events valid only on counter 1. */ 2071 case PMC_EV_IAP_EVENT_C0H_01H: 2072 mask = 0x2; 2073 break; 2074 /* Events valid only on counter 2. */ 2075 case PMC_EV_IAP_EVENT_48H_01H: 2076 case PMC_EV_IAP_EVENT_A2H_02H: 2077 case PMC_EV_IAP_EVENT_A3H_08H: 2078 mask = 0x4; 2079 break; 2080 /* Events valid only on counter 3. */ 2081 case PMC_EV_IAP_EVENT_BBH_01H: 2082 case PMC_EV_IAP_EVENT_CDH_01H: 2083 case PMC_EV_IAP_EVENT_CDH_02H: 2084 mask = 0x8; 2085 break; 2086 default: 2087 mask = ~0; /* Any row index is ok. */ 2088 } 2089 2090 return (mask & (1 << ri)); 2091 } 2092 2093 static int 2094 iap_event_ok_on_counter(enum pmc_event pe, int ri) 2095 { 2096 uint32_t mask; 2097 2098 switch (pe) { 2099 /* 2100 * Events valid only on counter 0. 2101 */ 2102 case PMC_EV_IAP_EVENT_10H_00H: 2103 case PMC_EV_IAP_EVENT_14H_00H: 2104 case PMC_EV_IAP_EVENT_18H_00H: 2105 case PMC_EV_IAP_EVENT_B3H_01H: 2106 case PMC_EV_IAP_EVENT_B3H_02H: 2107 case PMC_EV_IAP_EVENT_B3H_04H: 2108 case PMC_EV_IAP_EVENT_C1H_00H: 2109 case PMC_EV_IAP_EVENT_CBH_01H: 2110 case PMC_EV_IAP_EVENT_CBH_02H: 2111 mask = (1 << 0); 2112 break; 2113 2114 /* 2115 * Events valid only on counter 1. 2116 */ 2117 case PMC_EV_IAP_EVENT_11H_00H: 2118 case PMC_EV_IAP_EVENT_12H_00H: 2119 case PMC_EV_IAP_EVENT_13H_00H: 2120 mask = (1 << 1); 2121 break; 2122 2123 default: 2124 mask = ~0; /* Any row index is ok. */ 2125 } 2126 2127 return (mask & (1 << ri)); 2128 } 2129 2130 static int 2131 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 2132 const struct pmc_op_pmcallocate *a) 2133 { 2134 int arch, n, model; 2135 enum pmc_event ev, map; 2136 struct iap_event_descr *ie; 2137 uint32_t c, caps, config, cpuflag, evsel, mask; 2138 2139 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2140 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2141 KASSERT(ri >= 0 && ri < core_iap_npmc, 2142 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 2143 2144 /* check requested capabilities */ 2145 caps = a->pm_caps; 2146 if ((IAP_PMC_CAPS & caps) != caps) 2147 return (EPERM); 2148 map = 0; /* XXX: silent GCC warning */ 2149 arch = iap_is_event_architectural(pm->pm_event, &map); 2150 if (arch == EV_IS_ARCH_NOTSUPP) 2151 return (EOPNOTSUPP); 2152 else if (arch == EV_IS_ARCH_SUPP) 2153 ev = map; 2154 else 2155 ev = pm->pm_event; 2156 2157 /* 2158 * A small number of events are not supported in all the 2159 * processors based on a given microarchitecture. 2160 */ 2161 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 2162 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 2163 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 2164 return (EINVAL); 2165 } 2166 2167 switch (core_cputype) { 2168 case PMC_CPU_INTEL_COREI7: 2169 case PMC_CPU_INTEL_NEHALEM_EX: 2170 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 2171 return (EINVAL); 2172 break; 2173 case PMC_CPU_INTEL_SKYLAKE: 2174 case PMC_CPU_INTEL_BROADWELL: 2175 case PMC_CPU_INTEL_BROADWELL_XEON: 2176 case PMC_CPU_INTEL_SANDYBRIDGE: 2177 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2178 case PMC_CPU_INTEL_IVYBRIDGE: 2179 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2180 case PMC_CPU_INTEL_HASWELL: 2181 case PMC_CPU_INTEL_HASWELL_XEON: 2182 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 2183 return (EINVAL); 2184 break; 2185 case PMC_CPU_INTEL_WESTMERE: 2186 case PMC_CPU_INTEL_WESTMERE_EX: 2187 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 2188 return (EINVAL); 2189 break; 2190 default: 2191 if (iap_event_ok_on_counter(ev, ri) == 0) 2192 return (EINVAL); 2193 } 2194 2195 /* 2196 * Look for an event descriptor with matching CPU and event id 2197 * fields. 2198 */ 2199 2200 switch (core_cputype) { 2201 default: 2202 case PMC_CPU_INTEL_ATOM: 2203 cpuflag = IAP_F_CA; 2204 break; 2205 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2206 cpuflag = IAP_F_CAS; 2207 break; 2208 case PMC_CPU_INTEL_SKYLAKE: 2209 cpuflag = IAP_F_SL; 2210 break; 2211 case PMC_CPU_INTEL_BROADWELL_XEON: 2212 cpuflag = IAP_F_BWX; 2213 break; 2214 case PMC_CPU_INTEL_BROADWELL: 2215 cpuflag = IAP_F_BW; 2216 break; 2217 case PMC_CPU_INTEL_CORE: 2218 cpuflag = IAP_F_CC; 2219 break; 2220 case PMC_CPU_INTEL_CORE2: 2221 cpuflag = IAP_F_CC2; 2222 break; 2223 case PMC_CPU_INTEL_CORE2EXTREME: 2224 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 2225 break; 2226 case PMC_CPU_INTEL_COREI7: 2227 cpuflag = IAP_F_I7; 2228 break; 2229 case PMC_CPU_INTEL_HASWELL: 2230 cpuflag = IAP_F_HW; 2231 break; 2232 case PMC_CPU_INTEL_HASWELL_XEON: 2233 cpuflag = IAP_F_HWX; 2234 break; 2235 case PMC_CPU_INTEL_IVYBRIDGE: 2236 cpuflag = IAP_F_IB; 2237 break; 2238 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2239 cpuflag = IAP_F_IBX; 2240 break; 2241 case PMC_CPU_INTEL_SANDYBRIDGE: 2242 cpuflag = IAP_F_SB; 2243 break; 2244 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2245 cpuflag = IAP_F_SBX; 2246 break; 2247 case PMC_CPU_INTEL_WESTMERE: 2248 cpuflag = IAP_F_WM; 2249 break; 2250 } 2251 2252 for (n = 0, ie = iap_events; n < nitems(iap_events); n++, ie++) 2253 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2254 break; 2255 2256 if (n == nitems(iap_events)) 2257 return (EINVAL); 2258 2259 /* 2260 * A matching event descriptor has been found, so start 2261 * assembling the contents of the event select register. 2262 */ 2263 evsel = ie->iap_evcode; 2264 2265 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2266 2267 /* 2268 * If the event uses a fixed umask value, reject any umask 2269 * bits set by the user. 2270 */ 2271 if (ie->iap_flags & IAP_F_FM) { 2272 2273 if (IAP_UMASK(config) != 0) 2274 return (EINVAL); 2275 2276 evsel |= (ie->iap_umask << 8); 2277 2278 } else { 2279 2280 /* 2281 * Otherwise, the UMASK value needs to be taken from 2282 * the MD fields of the allocation request. Reject 2283 * requests that specify reserved bits. 2284 */ 2285 2286 mask = 0; 2287 2288 if (ie->iap_umask & IAP_M_CORE) { 2289 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2290 c != IAP_CORE_THIS) 2291 return (EINVAL); 2292 mask |= IAP_F_CORE; 2293 } 2294 2295 if (ie->iap_umask & IAP_M_AGENT) 2296 mask |= IAP_F_AGENT; 2297 2298 if (ie->iap_umask & IAP_M_PREFETCH) { 2299 2300 if ((c = (config & IAP_F_PREFETCH)) == 2301 IAP_PREFETCH_RESERVED) 2302 return (EINVAL); 2303 2304 mask |= IAP_F_PREFETCH; 2305 } 2306 2307 if (ie->iap_umask & IAP_M_MESI) 2308 mask |= IAP_F_MESI; 2309 2310 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2311 mask |= IAP_F_SNOOPRESPONSE; 2312 2313 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2314 mask |= IAP_F_SNOOPTYPE; 2315 2316 if (ie->iap_umask & IAP_M_TRANSITION) 2317 mask |= IAP_F_TRANSITION; 2318 2319 /* 2320 * If bits outside of the allowed set of umask bits 2321 * are set, reject the request. 2322 */ 2323 if (config & ~mask) 2324 return (EINVAL); 2325 2326 evsel |= (config & mask); 2327 2328 } 2329 2330 /* 2331 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2332 */ 2333 if (core_cputype == PMC_CPU_INTEL_ATOM || 2334 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 2335 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2336 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2337 evsel |= (config & IAP_ANY); 2338 else if (config & IAP_ANY) 2339 return (EINVAL); 2340 2341 /* 2342 * Check offcore response configuration. 2343 */ 2344 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2345 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2346 ev != PMC_EV_IAP_EVENT_BBH_01H) 2347 return (EINVAL); 2348 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2349 ev == PMC_EV_IAP_EVENT_BBH_01H) 2350 return (EINVAL); 2351 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2352 core_cputype == PMC_CPU_INTEL_WESTMERE || 2353 core_cputype == PMC_CPU_INTEL_NEHALEM_EX || 2354 core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && 2355 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2356 return (EINVAL); 2357 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2358 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2359 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2360 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2361 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2362 return (EINVAL); 2363 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2364 } 2365 2366 if (caps & PMC_CAP_THRESHOLD) 2367 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2368 if (caps & PMC_CAP_USER) 2369 evsel |= IAP_USR; 2370 if (caps & PMC_CAP_SYSTEM) 2371 evsel |= IAP_OS; 2372 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2373 evsel |= (IAP_OS | IAP_USR); 2374 if (caps & PMC_CAP_EDGE) 2375 evsel |= IAP_EDGE; 2376 if (caps & PMC_CAP_INVERT) 2377 evsel |= IAP_INV; 2378 if (caps & PMC_CAP_INTERRUPT) 2379 evsel |= IAP_INT; 2380 2381 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2382 2383 return (0); 2384 } 2385 2386 static int 2387 iap_config_pmc(int cpu, int ri, struct pmc *pm) 2388 { 2389 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2390 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2391 2392 KASSERT(ri >= 0 && ri < core_iap_npmc, 2393 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2394 2395 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2396 2397 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2398 cpu)); 2399 2400 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2401 2402 return (0); 2403 } 2404 2405 static int 2406 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2407 { 2408 int error; 2409 struct pmc_hw *phw; 2410 char iap_name[PMC_NAME_MAX]; 2411 2412 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2413 2414 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2415 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2416 NULL)) != 0) 2417 return (error); 2418 2419 pi->pm_class = PMC_CLASS_IAP; 2420 2421 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2422 pi->pm_enabled = TRUE; 2423 *ppmc = phw->phw_pmc; 2424 } else { 2425 pi->pm_enabled = FALSE; 2426 *ppmc = NULL; 2427 } 2428 2429 return (0); 2430 } 2431 2432 static int 2433 iap_get_config(int cpu, int ri, struct pmc **ppm) 2434 { 2435 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2436 2437 return (0); 2438 } 2439 2440 static int 2441 iap_get_msr(int ri, uint32_t *msr) 2442 { 2443 KASSERT(ri >= 0 && ri < core_iap_npmc, 2444 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2445 2446 *msr = ri; 2447 2448 return (0); 2449 } 2450 2451 static int 2452 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2453 { 2454 struct pmc *pm; 2455 pmc_value_t tmp; 2456 2457 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2458 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2459 KASSERT(ri >= 0 && ri < core_iap_npmc, 2460 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2461 2462 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2463 2464 KASSERT(pm, 2465 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2466 ri)); 2467 2468 tmp = rdpmc(ri); 2469 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2470 *v = iap_perfctr_value_to_reload_count(tmp); 2471 else 2472 *v = tmp & ((1ULL << core_iap_width) - 1); 2473 2474 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2475 IAP_PMC0 + ri, *v); 2476 2477 return (0); 2478 } 2479 2480 static int 2481 iap_release_pmc(int cpu, int ri, struct pmc *pm) 2482 { 2483 (void) pm; 2484 2485 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2486 pm); 2487 2488 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2489 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2490 KASSERT(ri >= 0 && ri < core_iap_npmc, 2491 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2492 2493 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2494 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2495 2496 return (0); 2497 } 2498 2499 static int 2500 iap_start_pmc(int cpu, int ri) 2501 { 2502 struct pmc *pm; 2503 uint32_t evsel; 2504 struct core_cpu *cc; 2505 2506 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2507 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2508 KASSERT(ri >= 0 && ri < core_iap_npmc, 2509 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2510 2511 cc = core_pcpu[cpu]; 2512 pm = cc->pc_corepmcs[ri].phw_pmc; 2513 2514 KASSERT(pm, 2515 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2516 __LINE__, cpu, ri)); 2517 2518 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2519 2520 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2521 2522 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2523 cpu, ri, IAP_EVSEL0 + ri, evsel); 2524 2525 /* Event specific configuration. */ 2526 switch (pm->pm_event) { 2527 case PMC_EV_IAP_EVENT_B7H_01H: 2528 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2529 break; 2530 case PMC_EV_IAP_EVENT_BBH_01H: 2531 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2532 break; 2533 default: 2534 break; 2535 } 2536 2537 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2538 2539 if (core_cputype == PMC_CPU_INTEL_CORE) 2540 return (0); 2541 2542 do { 2543 cc->pc_resync = 0; 2544 cc->pc_globalctrl |= (1ULL << ri); 2545 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2546 } while (cc->pc_resync != 0); 2547 2548 return (0); 2549 } 2550 2551 static int 2552 iap_stop_pmc(int cpu, int ri) 2553 { 2554 struct pmc *pm; 2555 struct core_cpu *cc; 2556 uint64_t msr; 2557 2558 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2559 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2560 KASSERT(ri >= 0 && ri < core_iap_npmc, 2561 ("[core,%d] illegal row index %d", __LINE__, ri)); 2562 2563 cc = core_pcpu[cpu]; 2564 pm = cc->pc_corepmcs[ri].phw_pmc; 2565 2566 KASSERT(pm, 2567 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2568 cpu, ri)); 2569 2570 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2571 2572 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2573 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2574 2575 if (core_cputype == PMC_CPU_INTEL_CORE) 2576 return (0); 2577 2578 msr = 0; 2579 do { 2580 cc->pc_resync = 0; 2581 cc->pc_globalctrl &= ~(1ULL << ri); 2582 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2583 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2584 } while (cc->pc_resync != 0); 2585 2586 return (0); 2587 } 2588 2589 static int 2590 iap_write_pmc(int cpu, int ri, pmc_value_t v) 2591 { 2592 struct pmc *pm; 2593 struct core_cpu *cc; 2594 2595 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2596 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2597 KASSERT(ri >= 0 && ri < core_iap_npmc, 2598 ("[core,%d] illegal row index %d", __LINE__, ri)); 2599 2600 cc = core_pcpu[cpu]; 2601 pm = cc->pc_corepmcs[ri].phw_pmc; 2602 2603 KASSERT(pm, 2604 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2605 cpu, ri)); 2606 2607 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2608 v = iap_reload_count_to_perfctr_value(v); 2609 2610 v &= (1ULL << core_iap_width) - 1; 2611 2612 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2613 IAP_PMC0 + ri, v); 2614 2615 /* 2616 * Write the new value to the counter (or it's alias). The 2617 * counter will be in a stopped state when the pcd_write() 2618 * entry point is called. 2619 */ 2620 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 2621 return (0); 2622 } 2623 2624 2625 static void 2626 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2627 int flags) 2628 { 2629 struct pmc_classdep *pcd; 2630 2631 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2632 2633 PMCDBG0(MDP,INI,1, "iap-initialize"); 2634 2635 /* Remember the set of architectural events supported. */ 2636 core_architectural_events = ~flags; 2637 2638 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2639 2640 pcd->pcd_caps = IAP_PMC_CAPS; 2641 pcd->pcd_class = PMC_CLASS_IAP; 2642 pcd->pcd_num = npmc; 2643 pcd->pcd_ri = md->pmd_npmc; 2644 pcd->pcd_width = pmcwidth; 2645 2646 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2647 pcd->pcd_config_pmc = iap_config_pmc; 2648 pcd->pcd_describe = iap_describe; 2649 pcd->pcd_get_config = iap_get_config; 2650 pcd->pcd_get_msr = iap_get_msr; 2651 pcd->pcd_pcpu_fini = core_pcpu_fini; 2652 pcd->pcd_pcpu_init = core_pcpu_init; 2653 pcd->pcd_read_pmc = iap_read_pmc; 2654 pcd->pcd_release_pmc = iap_release_pmc; 2655 pcd->pcd_start_pmc = iap_start_pmc; 2656 pcd->pcd_stop_pmc = iap_stop_pmc; 2657 pcd->pcd_write_pmc = iap_write_pmc; 2658 2659 md->pmd_npmc += npmc; 2660 } 2661 2662 static int 2663 core_intr(int cpu, struct trapframe *tf) 2664 { 2665 pmc_value_t v; 2666 struct pmc *pm; 2667 struct core_cpu *cc; 2668 int error, found_interrupt, ri; 2669 uint64_t msr; 2670 2671 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2672 TRAPF_USERMODE(tf)); 2673 2674 found_interrupt = 0; 2675 cc = core_pcpu[cpu]; 2676 2677 for (ri = 0; ri < core_iap_npmc; ri++) { 2678 2679 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2680 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2681 continue; 2682 2683 if (!iap_pmc_has_overflowed(ri)) 2684 continue; 2685 2686 found_interrupt = 1; 2687 2688 if (pm->pm_state != PMC_STATE_RUNNING) 2689 continue; 2690 2691 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2692 TRAPF_USERMODE(tf)); 2693 2694 v = pm->pm_sc.pm_reloadcount; 2695 v = iap_reload_count_to_perfctr_value(v); 2696 2697 /* 2698 * Stop the counter, reload it but only restart it if 2699 * the PMC is not stalled. 2700 */ 2701 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2702 wrmsr(IAP_EVSEL0 + ri, msr); 2703 wrmsr(core_iap_wroffset + IAP_PMC0 + ri, v); 2704 2705 if (error) 2706 continue; 2707 2708 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2709 IAP_EN)); 2710 } 2711 2712 if (found_interrupt) 2713 lapic_reenable_pmc(); 2714 2715 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2716 &pmc_stats.pm_intr_ignored, 1); 2717 2718 return (found_interrupt); 2719 } 2720 2721 static int 2722 core2_intr(int cpu, struct trapframe *tf) 2723 { 2724 int error, found_interrupt, n; 2725 uint64_t flag, intrstatus, intrenable, msr; 2726 struct pmc *pm; 2727 struct core_cpu *cc; 2728 pmc_value_t v; 2729 2730 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2731 TRAPF_USERMODE(tf)); 2732 2733 /* 2734 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2735 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2736 * the current set of interrupting PMCs and process these 2737 * after stopping them. 2738 */ 2739 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2740 intrenable = intrstatus & core_pmcmask; 2741 2742 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2743 (uintmax_t) intrstatus); 2744 2745 found_interrupt = 0; 2746 cc = core_pcpu[cpu]; 2747 2748 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2749 2750 cc->pc_globalctrl &= ~intrenable; 2751 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2752 2753 /* 2754 * Stop PMCs and clear overflow status bits. 2755 */ 2756 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2757 wrmsr(IA_GLOBAL_CTRL, msr); 2758 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2759 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2760 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2761 2762 /* 2763 * Look for interrupts from fixed function PMCs. 2764 */ 2765 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2766 n++, flag <<= 1) { 2767 2768 if ((intrstatus & flag) == 0) 2769 continue; 2770 2771 found_interrupt = 1; 2772 2773 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2774 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2775 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2776 continue; 2777 2778 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2779 TRAPF_USERMODE(tf)); 2780 if (error) 2781 intrenable &= ~flag; 2782 2783 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2784 2785 /* Reload sampling count. */ 2786 wrmsr(IAF_CTR0 + n, v); 2787 2788 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 2789 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2790 } 2791 2792 /* 2793 * Process interrupts from the programmable counters. 2794 */ 2795 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2796 if ((intrstatus & flag) == 0) 2797 continue; 2798 2799 found_interrupt = 1; 2800 2801 pm = cc->pc_corepmcs[n].phw_pmc; 2802 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2803 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2804 continue; 2805 2806 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2807 TRAPF_USERMODE(tf)); 2808 if (error) 2809 intrenable &= ~flag; 2810 2811 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2812 2813 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2814 (uintmax_t) v); 2815 2816 /* Reload sampling count. */ 2817 wrmsr(core_iap_wroffset + IAP_PMC0 + n, v); 2818 } 2819 2820 /* 2821 * Reenable all non-stalled PMCs. 2822 */ 2823 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2824 (uintmax_t) intrenable); 2825 2826 cc->pc_globalctrl |= intrenable; 2827 2828 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2829 2830 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2831 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2832 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2833 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2834 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2835 2836 if (found_interrupt) 2837 lapic_reenable_pmc(); 2838 2839 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2840 &pmc_stats.pm_intr_ignored, 1); 2841 2842 return (found_interrupt); 2843 } 2844 2845 int 2846 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 2847 { 2848 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2849 int ipa_version, flags, nflags; 2850 2851 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2852 2853 ipa_version = (version_override > 0) ? version_override : 2854 cpuid[CORE_CPUID_EAX] & 0xFF; 2855 core_cputype = md->pmd_cputype; 2856 2857 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2858 core_cputype, maxcpu, ipa_version); 2859 2860 if (ipa_version < 1 || ipa_version > 3 || 2861 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 2862 /* Unknown PMC architecture. */ 2863 printf("hwpc_core: unknown PMC architecture: %d\n", 2864 ipa_version); 2865 return (EPROGMISMATCH); 2866 } 2867 2868 core_iap_wroffset = 0; 2869 if (cpu_feature2 & CPUID2_PDCM) { 2870 if (rdmsr(IA32_PERF_CAPABILITIES) & PERFCAP_FW_WRITE) { 2871 PMCDBG0(MDP, INI, 1, 2872 "core-init full-width write supported"); 2873 core_iap_wroffset = IAP_A_PMC0 - IAP_PMC0; 2874 } else 2875 PMCDBG0(MDP, INI, 1, 2876 "core-init full-width write NOT supported"); 2877 } else 2878 PMCDBG0(MDP, INI, 1, "core-init pdcm not supported"); 2879 2880 core_pmcmask = 0; 2881 2882 /* 2883 * Initialize programmable counters. 2884 */ 2885 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2886 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2887 2888 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2889 2890 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2891 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2892 2893 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2894 2895 /* 2896 * Initialize fixed function counters, if present. 2897 */ 2898 if (core_cputype != PMC_CPU_INTEL_CORE) { 2899 core_iaf_ri = core_iap_npmc; 2900 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2901 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2902 2903 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2904 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2905 } 2906 2907 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2908 core_iaf_ri); 2909 2910 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 2911 M_ZERO | M_WAITOK); 2912 2913 /* 2914 * Choose the appropriate interrupt handler. 2915 */ 2916 if (ipa_version == 1) 2917 md->pmd_intr = core_intr; 2918 else 2919 md->pmd_intr = core2_intr; 2920 2921 md->pmd_pcpu_fini = NULL; 2922 md->pmd_pcpu_init = NULL; 2923 2924 return (0); 2925 } 2926 2927 void 2928 pmc_core_finalize(struct pmc_mdep *md) 2929 { 2930 PMCDBG0(MDP,INI,1, "core-finalize"); 2931 2932 free(core_pcpu, M_PMC); 2933 core_pcpu = NULL; 2934 } 2935