1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #if (__FreeBSD_version >= 1100000) 42 #include <x86/apicvar.h> 43 #else 44 #include <machine/apicvar.h> 45 #endif 46 #include <machine/cpu.h> 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #define CORE_CPUID_REQUEST 0xA 52 #define CORE_CPUID_REQUEST_SIZE 0x4 53 #define CORE_CPUID_EAX 0x0 54 #define CORE_CPUID_EBX 0x1 55 #define CORE_CPUID_ECX 0x2 56 #define CORE_CPUID_EDX 0x3 57 58 #define IAF_PMC_CAPS \ 59 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 60 PMC_CAP_USER | PMC_CAP_SYSTEM) 61 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 62 63 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 64 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 65 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 66 67 #define EV_IS_NOTARCH 0 68 #define EV_IS_ARCH_SUPP 1 69 #define EV_IS_ARCH_NOTSUPP -1 70 71 /* 72 * "Architectural" events defined by Intel. The values of these 73 * symbols correspond to positions in the bitmask returned by 74 * the CPUID.0AH instruction. 75 */ 76 enum core_arch_events { 77 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 78 CORE_AE_BRANCH_MISSES_RETIRED = 6, 79 CORE_AE_INSTRUCTION_RETIRED = 1, 80 CORE_AE_LLC_MISSES = 4, 81 CORE_AE_LLC_REFERENCE = 3, 82 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 83 CORE_AE_UNHALTED_CORE_CYCLES = 0 84 }; 85 86 static enum pmc_cputype core_cputype; 87 88 struct core_cpu { 89 volatile uint32_t pc_resync; 90 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 91 volatile uint64_t pc_globalctrl; /* Global control register. */ 92 struct pmc_hw pc_corepmcs[]; 93 }; 94 95 static struct core_cpu **core_pcpu; 96 97 static uint32_t core_architectural_events; 98 static uint64_t core_pmcmask; 99 100 static int core_iaf_ri; /* relative index of fixed counters */ 101 static int core_iaf_width; 102 static int core_iaf_npmc; 103 104 static int core_iap_width; 105 static int core_iap_npmc; 106 107 static int 108 core_pcpu_noop(struct pmc_mdep *md, int cpu) 109 { 110 (void) md; 111 (void) cpu; 112 return (0); 113 } 114 115 static int 116 core_pcpu_init(struct pmc_mdep *md, int cpu) 117 { 118 struct pmc_cpu *pc; 119 struct core_cpu *cc; 120 struct pmc_hw *phw; 121 int core_ri, n, npmc; 122 123 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 124 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 125 126 PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu); 127 128 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 129 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 130 131 if (core_cputype != PMC_CPU_INTEL_CORE) 132 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 133 134 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 135 M_PMC, M_WAITOK | M_ZERO); 136 137 core_pcpu[cpu] = cc; 138 pc = pmc_pcpu[cpu]; 139 140 KASSERT(pc != NULL && cc != NULL, 141 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 142 143 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 144 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 145 PMC_PHW_CPU_TO_STATE(cpu) | 146 PMC_PHW_INDEX_TO_STATE(n + core_ri); 147 phw->phw_pmc = NULL; 148 pc->pc_hwpmcs[n + core_ri] = phw; 149 } 150 151 return (0); 152 } 153 154 static int 155 core_pcpu_fini(struct pmc_mdep *md, int cpu) 156 { 157 int core_ri, n, npmc; 158 struct pmc_cpu *pc; 159 struct core_cpu *cc; 160 uint64_t msr = 0; 161 162 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 163 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 164 165 PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 166 167 if ((cc = core_pcpu[cpu]) == NULL) 168 return (0); 169 170 core_pcpu[cpu] = NULL; 171 172 pc = pmc_pcpu[cpu]; 173 174 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 175 cpu)); 176 177 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 178 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 179 180 for (n = 0; n < npmc; n++) { 181 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 182 wrmsr(IAP_EVSEL0 + n, msr); 183 } 184 185 if (core_cputype != PMC_CPU_INTEL_CORE) { 186 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 187 wrmsr(IAF_CTRL, msr); 188 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 189 } 190 191 for (n = 0; n < npmc; n++) 192 pc->pc_hwpmcs[n + core_ri] = NULL; 193 194 free(cc, M_PMC); 195 196 return (0); 197 } 198 199 /* 200 * Fixed function counters. 201 */ 202 203 static pmc_value_t 204 iaf_perfctr_value_to_reload_count(pmc_value_t v) 205 { 206 207 /* If the PMC has overflowed, return a reload count of zero. */ 208 if ((v & (1ULL << (core_iaf_width - 1))) == 0) 209 return (0); 210 v &= (1ULL << core_iaf_width) - 1; 211 return (1ULL << core_iaf_width) - v; 212 } 213 214 static pmc_value_t 215 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 216 { 217 return (1ULL << core_iaf_width) - rlc; 218 } 219 220 static int 221 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 222 const struct pmc_op_pmcallocate *a) 223 { 224 enum pmc_event ev; 225 uint32_t caps, flags, validflags; 226 227 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 228 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 229 230 PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 231 232 if (ri < 0 || ri > core_iaf_npmc) 233 return (EINVAL); 234 235 caps = a->pm_caps; 236 237 if (a->pm_class != PMC_CLASS_IAF || 238 (caps & IAF_PMC_CAPS) != caps) 239 return (EINVAL); 240 241 ev = pm->pm_event; 242 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 243 return (EINVAL); 244 245 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 246 return (EINVAL); 247 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 248 return (EINVAL); 249 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 250 return (EINVAL); 251 252 flags = a->pm_md.pm_iaf.pm_iaf_flags; 253 254 validflags = IAF_MASK; 255 256 if (core_cputype != PMC_CPU_INTEL_ATOM && 257 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 258 validflags &= ~IAF_ANY; 259 260 if ((flags & ~validflags) != 0) 261 return (EINVAL); 262 263 if (caps & PMC_CAP_INTERRUPT) 264 flags |= IAF_PMI; 265 if (caps & PMC_CAP_SYSTEM) 266 flags |= IAF_OS; 267 if (caps & PMC_CAP_USER) 268 flags |= IAF_USR; 269 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 270 flags |= (IAF_OS | IAF_USR); 271 272 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 273 274 PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx", 275 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 276 277 return (0); 278 } 279 280 static int 281 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 282 { 283 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 284 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 285 286 KASSERT(ri >= 0 && ri < core_iaf_npmc, 287 ("[core,%d] illegal row-index %d", __LINE__, ri)); 288 289 PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 290 291 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 292 cpu)); 293 294 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 295 296 return (0); 297 } 298 299 static int 300 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 301 { 302 int error; 303 struct pmc_hw *phw; 304 char iaf_name[PMC_NAME_MAX]; 305 306 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 307 308 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 309 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 310 NULL)) != 0) 311 return (error); 312 313 pi->pm_class = PMC_CLASS_IAF; 314 315 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 316 pi->pm_enabled = TRUE; 317 *ppmc = phw->phw_pmc; 318 } else { 319 pi->pm_enabled = FALSE; 320 *ppmc = NULL; 321 } 322 323 return (0); 324 } 325 326 static int 327 iaf_get_config(int cpu, int ri, struct pmc **ppm) 328 { 329 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 330 331 return (0); 332 } 333 334 static int 335 iaf_get_msr(int ri, uint32_t *msr) 336 { 337 KASSERT(ri >= 0 && ri < core_iaf_npmc, 338 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 339 340 *msr = IAF_RI_TO_MSR(ri); 341 342 return (0); 343 } 344 345 static int 346 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 347 { 348 struct pmc *pm; 349 pmc_value_t tmp; 350 351 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 352 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 353 KASSERT(ri >= 0 && ri < core_iaf_npmc, 354 ("[core,%d] illegal row-index %d", __LINE__, ri)); 355 356 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 357 358 KASSERT(pm, 359 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 360 ri, ri + core_iaf_ri)); 361 362 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 363 364 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 365 *v = iaf_perfctr_value_to_reload_count(tmp); 366 else 367 *v = tmp; 368 369 PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 370 IAF_RI_TO_MSR(ri), *v); 371 372 return (0); 373 } 374 375 static int 376 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 377 { 378 PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 379 380 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 381 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 382 KASSERT(ri >= 0 && ri < core_iaf_npmc, 383 ("[core,%d] illegal row-index %d", __LINE__, ri)); 384 385 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 386 ("[core,%d] PHW pmc non-NULL", __LINE__)); 387 388 return (0); 389 } 390 391 static int 392 iaf_start_pmc(int cpu, int ri) 393 { 394 struct pmc *pm; 395 struct core_cpu *iafc; 396 uint64_t msr = 0; 397 398 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 399 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 400 KASSERT(ri >= 0 && ri < core_iaf_npmc, 401 ("[core,%d] illegal row-index %d", __LINE__, ri)); 402 403 PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 404 405 iafc = core_pcpu[cpu]; 406 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 407 408 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 409 410 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 411 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 412 413 do { 414 iafc->pc_resync = 0; 415 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 416 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 417 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 418 IAF_GLOBAL_CTRL_MASK)); 419 } while (iafc->pc_resync != 0); 420 421 PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 422 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 423 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 424 425 return (0); 426 } 427 428 static int 429 iaf_stop_pmc(int cpu, int ri) 430 { 431 uint32_t fc; 432 struct core_cpu *iafc; 433 uint64_t msr = 0; 434 435 PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 436 437 iafc = core_pcpu[cpu]; 438 439 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 440 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 441 KASSERT(ri >= 0 && ri < core_iaf_npmc, 442 ("[core,%d] illegal row-index %d", __LINE__, ri)); 443 444 fc = (IAF_MASK << (ri * 4)); 445 446 if (core_cputype != PMC_CPU_INTEL_ATOM && 447 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 448 fc &= ~IAF_ANY; 449 450 iafc->pc_iafctrl &= ~fc; 451 452 PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 453 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 454 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 455 456 do { 457 iafc->pc_resync = 0; 458 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 459 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 460 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 461 IAF_GLOBAL_CTRL_MASK)); 462 } while (iafc->pc_resync != 0); 463 464 PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 465 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 466 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 467 468 return (0); 469 } 470 471 static int 472 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 473 { 474 struct core_cpu *cc; 475 struct pmc *pm; 476 uint64_t msr; 477 478 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 479 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 480 KASSERT(ri >= 0 && ri < core_iaf_npmc, 481 ("[core,%d] illegal row-index %d", __LINE__, ri)); 482 483 cc = core_pcpu[cpu]; 484 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 485 486 KASSERT(pm, 487 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 488 489 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 490 v = iaf_reload_count_to_perfctr_value(v); 491 492 /* Turn off fixed counters */ 493 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 494 wrmsr(IAF_CTRL, msr); 495 496 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 497 498 /* Turn on fixed counters */ 499 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 500 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 501 502 PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 503 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 504 (uintmax_t) rdmsr(IAF_CTRL), 505 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 506 507 return (0); 508 } 509 510 511 static void 512 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 513 { 514 struct pmc_classdep *pcd; 515 516 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 517 518 PMCDBG0(MDP,INI,1, "iaf-initialize"); 519 520 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 521 522 pcd->pcd_caps = IAF_PMC_CAPS; 523 pcd->pcd_class = PMC_CLASS_IAF; 524 pcd->pcd_num = npmc; 525 pcd->pcd_ri = md->pmd_npmc; 526 pcd->pcd_width = pmcwidth; 527 528 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 529 pcd->pcd_config_pmc = iaf_config_pmc; 530 pcd->pcd_describe = iaf_describe; 531 pcd->pcd_get_config = iaf_get_config; 532 pcd->pcd_get_msr = iaf_get_msr; 533 pcd->pcd_pcpu_fini = core_pcpu_noop; 534 pcd->pcd_pcpu_init = core_pcpu_noop; 535 pcd->pcd_read_pmc = iaf_read_pmc; 536 pcd->pcd_release_pmc = iaf_release_pmc; 537 pcd->pcd_start_pmc = iaf_start_pmc; 538 pcd->pcd_stop_pmc = iaf_stop_pmc; 539 pcd->pcd_write_pmc = iaf_write_pmc; 540 541 md->pmd_npmc += npmc; 542 } 543 544 /* 545 * Intel programmable PMCs. 546 */ 547 548 /* 549 * Event descriptor tables. 550 * 551 * For each event id, we track: 552 * 553 * 1. The CPUs that the event is valid for. 554 * 555 * 2. If the event uses a fixed UMASK, the value of the umask field. 556 * If the event doesn't use a fixed UMASK, a mask of legal bits 557 * to check against. 558 */ 559 560 struct iap_event_descr { 561 enum pmc_event iap_ev; 562 unsigned char iap_evcode; 563 unsigned char iap_umask; 564 unsigned int iap_flags; 565 }; 566 567 #define IAP_F_CC (1 << 0) /* CPU: Core */ 568 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 569 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 570 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 571 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 572 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 573 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 574 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 575 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 576 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 577 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ 578 #define IAP_F_HW (1 << 10) /* CPU: Haswell */ 579 #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ 580 #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ 581 #define IAP_F_BW (1 << 13) /* CPU: Broadwell */ 582 #define IAP_F_BWX (1 << 14) /* CPU: Broadwell Xeon */ 583 #define IAP_F_SL (1 << 15) /* CPU: Skylake */ 584 #define IAP_F_FM (1 << 18) /* Fixed mask */ 585 586 #define IAP_F_ALLCPUSCORE2 \ 587 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 588 589 /* Sub fields of UMASK that this event supports. */ 590 #define IAP_M_CORE (1 << 0) /* Core specificity */ 591 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 592 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 593 #define IAP_M_MESI (1 << 3) /* MESI */ 594 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 595 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 596 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 597 598 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 599 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 600 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 601 #define IAP_F_MESI (0xF << 8) /* MESI */ 602 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 603 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 604 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 605 606 #define IAP_PREFETCH_RESERVED (0x2 << 12) 607 #define IAP_CORE_THIS (0x1 << 14) 608 #define IAP_CORE_ALL (0x3 << 14) 609 #define IAP_F_CMASK 0xFF000000 610 611 static struct iap_event_descr iap_events[] = { 612 #undef IAPDESCR 613 #define IAPDESCR(N,EV,UM,FLAGS) { \ 614 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 615 .iap_evcode = (EV), \ 616 .iap_umask = (UM), \ 617 .iap_flags = (FLAGS) \ 618 } 619 620 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 621 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 622 623 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 624 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 625 IAP_F_SBX | IAP_F_CAS), 626 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 627 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 628 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 629 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 630 IAP_F_CAS), 631 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 632 IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 633 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 634 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 635 IAP_F_SBX | IAP_F_CAS), 636 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 637 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_FM | IAP_F_CAS), 638 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_FM | IAP_F_CAS), 639 640 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), 641 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 642 IAP_F_CAS), 643 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 644 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_FM | IAP_F_CAS), 645 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 646 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 647 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_FM | IAP_F_CAS), 648 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_FM | IAP_F_CAS), 649 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_FM | IAP_F_CAS), 650 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_FM | IAP_F_CAS), 651 652 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 653 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 654 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | 655 IAP_F_BWX), 656 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | 657 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | 658 IAP_F_BW | IAP_F_BWX), 659 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), 660 661 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 662 IAP_F_CC2E | IAP_F_CA), 663 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 664 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 665 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 666 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 667 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 668 669 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 670 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 671 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 672 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 673 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 674 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 675 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 676 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 677 IAP_F_SBX), 678 679 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 680 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | 681 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 682 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 683 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | 684 IAP_F_BW | IAP_F_BWX), 685 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 686 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 687 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 688 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 689 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 690 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 691 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 692 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 693 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 694 IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 695 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 696 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 697 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 698 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 699 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 700 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 701 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 702 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 703 IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 704 705 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 706 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 707 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 708 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 709 710 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 711 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 712 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 713 714 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 715 IAP_F_WM | IAP_F_SL), 716 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 717 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 718 719 IAPDESCR(0DH_03H, 0x0D, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | 720 IAP_F_IB | IAP_F_IBX | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 721 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 722 IAPDESCR(0DH_80H, 0x0D, 0x80, IAP_F_FM | IAP_F_SL), 723 724 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 725 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 726 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 727 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SL), 728 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 729 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 730 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 731 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 732 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 733 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 734 735 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 736 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 737 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 738 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 739 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 740 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 741 742 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 743 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 744 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ), 745 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 746 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 747 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 748 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 749 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 750 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 751 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 752 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 753 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 754 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 755 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 756 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 757 758 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 759 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 760 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 761 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 762 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 763 764 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 765 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 766 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 767 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 768 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 769 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 770 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 771 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 772 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 773 774 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 775 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 776 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 777 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 778 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 779 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 780 781 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 782 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 783 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 784 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 785 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 786 787 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 788 IAP_F_SBX), 789 790 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 791 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 792 793 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 794 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 795 IAP_F_I7 | IAP_F_WM), 796 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 797 798 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 799 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 800 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 801 802 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 803 804 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 805 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 806 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 807 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 808 809 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 810 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 811 IAP_F_IB | IAP_F_SBX | IAP_F_IBX ), 812 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 813 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 814 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 815 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 816 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 817 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 818 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 819 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 820 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 821 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 822 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 823 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 824 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 825 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 826 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 827 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 828 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 829 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 830 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 831 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 832 IAP_F_BW | IAP_F_BWX), 833 IAPDESCR(24H_38H, 0x24, 0x38, IAP_F_FM | IAP_F_SL), 834 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 835 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 836 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 837 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 838 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 839 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 840 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 841 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 842 IAP_F_BW | IAP_F_BWX), 843 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 844 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 845 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 846 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 847 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 848 IAPDESCR(24H_D8H, 0x24, 0xD8, IAP_F_FM | IAP_F_SL), 849 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX | 850 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 851 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 852 IAP_F_SL), 853 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 854 IAP_F_SL), 855 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 856 IAPDESCR(24H_EFH, 0x24, 0xEF, IAP_F_FM | IAP_F_SL), 857 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 858 IAP_F_SL), 859 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 860 IAP_F_HWX), 861 862 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 863 864 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 865 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 866 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 867 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 868 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 869 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 870 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 871 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 872 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 873 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 874 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 875 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 876 877 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 878 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 879 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 880 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 881 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 882 IAP_F_SBX), 883 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 884 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 885 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 886 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 887 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 888 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 889 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 890 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 891 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 892 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 893 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 894 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 895 896 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 897 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 898 IAP_F_SBX | IAP_F_IBX), 899 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 900 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 901 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 902 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 903 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 904 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 905 IAP_F_SBX | IAP_F_IBX), 906 907 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 908 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 909 IAP_F_CA | IAP_F_CC2), 910 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 911 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 912 913 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 914 IAP_F_ALLCPUSCORE2), 915 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 916 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 917 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 918 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 919 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 920 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 921 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 922 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 923 924 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 925 IAP_F_ALLCPUSCORE2), 926 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_FM | IAP_F_CAS), 927 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_FM | IAP_F_CAS), 928 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 929 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 930 931 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 932 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 933 934 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 935 936 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 937 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 938 IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 939 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 940 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 941 IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 942 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_SL), 943 944 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 945 946 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 947 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 948 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 949 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 950 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 951 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 952 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 953 954 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 955 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 956 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 957 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 958 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 959 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 960 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 961 962 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 963 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 964 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 965 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 966 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 967 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 968 969 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 970 IAP_F_I7), 971 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 972 IAP_F_CC2 | IAP_F_I7), 973 974 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 975 976 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 977 978 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 979 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 980 981 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 982 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 983 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 984 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_SL), 985 986 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 987 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 988 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 989 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 990 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 991 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 992 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 993 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 994 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 995 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 996 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 997 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 998 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 999 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX | 1000 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1001 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1002 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1003 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | 1004 IAP_F_HWX), 1005 1006 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1007 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 1008 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1009 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 1010 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 1011 1012 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1013 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1014 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 1015 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1016 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1017 1018 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 1019 1020 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1021 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1022 IAP_F_SB | IAP_F_SBX), 1023 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1024 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1025 1026 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 1027 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 1028 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 1029 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 1030 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1031 1032 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1033 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1034 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1035 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1036 IAP_F_SB | IAP_F_SBX), 1037 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1038 IAP_F_SB | IAP_F_SBX), 1039 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1040 IAP_F_SB | IAP_F_SBX), 1041 1042 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1043 1044 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1045 1046 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1047 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1048 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1049 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1050 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1051 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1052 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1053 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1054 1055 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1056 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1057 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1058 1059 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1060 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1061 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1062 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1063 1064 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1065 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1066 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1067 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1068 1069 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1070 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1071 1072 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */ 1073 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_FM | IAP_F_IBX | IAP_F_IB), 1074 1075 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1076 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1077 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1078 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1079 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1080 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1081 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM |IAP_F_I7O | 1082 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1083 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1084 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM |IAP_F_I7O | 1085 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1086 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1087 IAPDESCR(60H_10H, 0x60, 0x10, IAP_F_FM | IAP_F_SL), 1088 1089 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1090 1091 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1092 1093 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1094 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1095 1096 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1097 IAP_F_CA | IAP_F_CC2), 1098 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1099 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1100 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1101 IAP_F_BW | IAP_F_BWX ), 1102 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1103 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1104 IAP_F_BW | IAP_F_BWX), 1105 1106 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1107 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1108 1109 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1110 IAP_F_CA | IAP_F_CC2), 1111 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1112 1113 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1114 1115 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1116 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1117 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1118 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1119 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1120 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1121 1122 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1123 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1124 1125 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1126 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1127 1128 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1129 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1130 1131 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1132 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1133 1134 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1135 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1136 1137 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1138 IAP_F_CA | IAP_F_CC2), 1139 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1140 1141 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1142 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1143 1144 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1145 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1146 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1147 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1148 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1149 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL | IAP_F_BW | IAP_F_BWX), 1150 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1151 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1152 1153 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1154 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1155 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1156 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1157 1158 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1159 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1160 1161 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1162 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1163 1164 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1165 IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1166 1167 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1168 1169 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1170 1171 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1172 1173 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1174 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1175 1176 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1177 1178 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1179 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1180 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1181 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1182 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1183 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1184 IAP_F_WM | IAP_F_CAS), 1185 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1186 IAP_F_IBX | IAP_F_SL), /* SL may have a spec bug two with same entry no cmask */ 1187 1188 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1189 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1190 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1191 1192 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1193 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1194 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1195 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1196 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1197 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1198 1199 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SL), 1200 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SL), 1201 1202 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1203 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1204 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1205 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1206 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1207 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1208 IAP_F_BW | IAP_F_BWX), 1209 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1210 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1211 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 1212 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1213 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1214 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX | 1215 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1216 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1217 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1218 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1219 1220 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1221 1222 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1223 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1224 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1225 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1226 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1227 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1228 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1229 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1230 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1231 1232 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1233 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1234 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1235 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1236 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1237 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1238 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1239 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1240 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1241 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1242 IAPDESCR(88H_41H, 0x88, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1243 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1244 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1245 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_BW | IAP_F_BWX), 1246 IAPDESCR(88H_81H, 0x88, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1247 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1248 IAPDESCR(88H_82H, 0x88, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1249 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1250 IAPDESCR(88H_84H, 0x88, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1251 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1252 IAPDESCR(88H_88H, 0x88, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1253 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1254 IAPDESCR(88H_90H, 0x88, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1255 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1256 IAPDESCR(88H_A0H, 0x88, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1257 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1258 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1259 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1260 1261 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1262 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1263 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1264 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1265 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1266 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1267 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1268 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1269 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1270 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_BW | IAP_F_BWX), 1271 IAPDESCR(89H_41H, 0x89, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1272 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1273 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1274 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_BW | IAP_F_BWX), 1275 IAPDESCR(89H_81H, 0x89, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1276 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1277 IAPDESCR(89H_82H, 0x89, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1278 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1279 IAPDESCR(89H_84H, 0x89, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1280 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1281 IAPDESCR(89H_88H, 0x89, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1282 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1283 IAPDESCR(89H_90H, 0x89, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1284 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1285 IAPDESCR(89H_A0H, 0x89, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1286 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1287 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1288 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1289 1290 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1291 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1292 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1293 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1294 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1295 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1296 1297 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1298 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1299 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1300 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1301 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1302 1303 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1304 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1305 1306 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1307 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1308 1309 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1310 1311 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1312 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1313 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1314 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1315 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1316 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1317 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1318 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1319 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1320 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1321 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1322 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1323 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1324 IAP_F_SBX | IAP_F_IBX), 1325 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1326 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1327 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1328 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1329 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1330 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1331 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1332 IAP_F_SBX | IAP_F_IBX), 1333 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1334 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1335 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1336 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1337 1338 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1339 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1340 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1341 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1342 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1343 IAP_F_SB | IAP_F_SBX), 1344 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1345 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1346 IAP_F_BW | IAP_F_BWX), 1347 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1348 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1349 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1350 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1351 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1352 IAP_F_BW | IAP_F_BWX), 1353 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1354 IAP_F_SB | IAP_F_SBX), 1355 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1356 IAP_F_SB | IAP_F_SBX), 1357 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1358 IAP_F_SB | IAP_F_SBX), 1359 1360 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | 1361 IAP_F_HWX | IAP_F_SL), 1362 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | 1363 IAP_F_HWX | IAP_F_SL), 1364 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_SL), 1365 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 1366 IAPDESCR(A3H_06H, 0xA3, 0x06, IAP_F_FM | IAP_F_SL), 1367 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | IAP_F_HWX | 1368 IAP_F_SL), 1369 IAPDESCR(A3H_0CH, 0xA3, 0x0C, IAP_F_FM | IAP_F_HW | IAP_F_HW | IAP_F_SL), 1370 IAPDESCR(A3H_10H, 0xA3, 0x10, IAP_F_FM | IAP_F_SL), 1371 IAPDESCR(A3H_14H, 0xA3, 0x14, IAP_F_FM | IAP_F_SL), 1372 1373 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1374 IAPDESCR(A6H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SL), 1375 IAPDESCR(A6H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SL), 1376 IAPDESCR(A6H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_SL), 1377 IAPDESCR(A6H_10H, 0xA3, 0x10, IAP_F_FM | IAP_F_SL), 1378 IAPDESCR(A6H_40H, 0xA3, 0x40, IAP_F_FM | IAP_F_SL), 1379 1380 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM ), 1381 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX | 1382 IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1383 IAP_F_SL), 1384 1385 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1386 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1387 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1388 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1389 1390 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1391 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1392 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1393 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_BW | IAP_F_BWX), 1394 1395 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_SL), 1396 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1397 IAP_F_SBX | IAP_F_IBX), 1398 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1399 1400 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1401 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1402 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1403 1404 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1405 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1406 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1407 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1408 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1409 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1410 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1411 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1412 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1413 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1414 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1415 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1416 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SL), 1417 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1418 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1419 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O | IAP_F_SL), 1420 1421 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1422 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1423 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1424 IAPDESCR(B1H_02H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1425 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1426 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1427 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1428 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1429 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1430 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1431 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1432 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1433 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1434 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1435 IAP_F_WM), 1436 1437 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1438 IAP_F_SB | IAP_F_SBX), 1439 1440 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1441 IAP_F_WM | IAP_F_I7O), 1442 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1443 IAP_F_WM | IAP_F_I7O), 1444 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1445 IAP_F_WM | IAP_F_I7O), 1446 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1447 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1448 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1449 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1450 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1451 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1452 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1453 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1454 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1455 1456 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1457 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1458 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1459 1460 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1461 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_FM | IAP_F_CAS), 1462 1463 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1464 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | 1465 IAP_F_HWX |IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1466 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), 1467 1468 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1469 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1470 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1471 1472 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1473 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1474 1475 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1476 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1477 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1478 1479 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1480 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1481 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1482 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1483 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1484 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1485 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1486 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1487 1488 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1489 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL), /* spec bug SL? */ 1490 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1491 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1492 1493 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1494 1495 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1496 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1497 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1498 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1499 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1500 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1501 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1502 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_BW | IAP_F_BWX), 1503 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1504 IAP_F_I7 | IAP_F_WM), 1505 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1506 1507 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1508 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1509 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1510 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1511 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1512 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1513 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1514 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1515 IAP_F_SBX | IAP_F_IBX), 1516 IAPDESCR(C1H_3FH, 0xC1, 0x3F, IAP_F_FM | IAP_F_SL), 1517 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1518 IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_FM |IAP_F_IB | IAP_F_IBX), 1519 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1520 1521 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1522 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1523 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1524 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1525 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1526 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1527 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1528 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1529 IAP_F_I7 | IAP_F_WM), 1530 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1531 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1532 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1533 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), 1534 1535 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1536 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1537 IAP_F_I7 | IAP_F_WM | IAP_F_CAS | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1538 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1539 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1540 IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1541 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1542 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1543 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1544 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_FM | IAP_F_CAS), 1545 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1546 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1547 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1548 1549 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1550 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1551 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1552 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1553 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1554 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1555 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1556 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1557 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1558 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1559 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1560 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1561 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1562 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1563 IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1564 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1565 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1566 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1567 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1568 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1569 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1570 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1571 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1572 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_FM | IAP_F_CAS), 1573 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_FM | IAP_F_CAS), 1574 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_FM | IAP_F_CAS), 1575 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_FM | IAP_F_CAS), 1576 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_FM | IAP_F_CAS), 1577 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_FM | IAP_F_CAS), 1578 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_FM | IAP_F_CAS), 1579 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_FM | IAP_F_CAS), 1580 1581 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1582 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1583 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1584 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1585 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1586 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1587 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_SL), 1588 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1589 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1590 IAP_F_SL), 1591 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1592 IAP_F_SBX | IAP_F_IBX), 1593 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1594 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_SL), 1595 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_FM | IAP_F_CAS), 1596 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_FM | IAP_F_CAS), 1597 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_FM | IAP_F_CAS), 1598 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_FM | IAP_F_CAS), 1599 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_FM | IAP_F_CAS), 1600 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_FM | IAP_F_CAS), 1601 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_FM | IAP_F_CAS), 1602 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_FM | IAP_F_CAS), 1603 1604 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1605 /* For SL C6_01 needs EV_SEL? 0x11, 0x12, 0x13, 0x14, 0x15? */ 1606 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SL), 1607 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1608 1609 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1610 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1611 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1612 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1613 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1614 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1615 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1616 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1617 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1618 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1619 IAP_F_I7 | IAP_F_WM | IAP_F_SL), 1620 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1621 IAPDESCR(C7H_20H, 0xC7, 0x20, IAP_F_FM | IAP_F_SL), 1622 1623 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1624 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1625 1626 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1627 1628 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1629 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 1630 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1631 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1632 IAP_F_BW | IAP_F_BWX), 1633 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1634 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1635 IAP_F_BW | IAP_F_BWX), 1636 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1637 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1638 IAP_F_BW | IAP_F_BWX), 1639 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1640 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1641 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1642 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1643 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_FM | IAP_F_CAS | IAP_F_BW | IAP_F_BWX), 1644 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_FM | IAP_F_CAS), 1645 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_FM | IAP_F_CAS), 1646 1647 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1648 IAP_F_I7 | IAP_F_WM | IAP_F_CAS | IAP_F_SL), 1649 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1650 IAP_F_I7 | IAP_F_WM), 1651 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1652 IAP_F_I7 | IAP_F_WM), 1653 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1654 IAP_F_I7 | IAP_F_WM), 1655 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1656 IAP_F_WM), 1657 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_FM | IAP_F_CAS), 1658 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1659 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1660 1661 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1662 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1663 IAP_F_I7 | IAP_F_WM), 1664 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1665 IAP_F_I7 | IAP_F_WM), 1666 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1667 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1668 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1669 1670 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1671 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1672 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | 1673 IAP_F_SL), 1674 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1675 IAP_F_SBX | IAP_F_IBX), 1676 1677 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1678 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1679 1680 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ 1681 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1682 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1683 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1684 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1685 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1686 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1687 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_BW | IAP_F_BWX | 1688 IAP_F_SL), 1689 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1690 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1691 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1692 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1693 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1694 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1695 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1696 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1697 1698 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1699 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | 1700 IAP_F_BWX | IAP_F_SL), 1701 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1702 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1703 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1704 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1705 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1706 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1707 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1708 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1709 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX | 1710 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1711 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1712 IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1713 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1714 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1715 1716 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1717 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1718 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1719 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1720 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1721 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1722 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1723 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1724 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1725 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1726 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1727 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1728 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1729 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1730 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1731 1732 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1733 1734 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1735 IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1736 IAPDESCR(D3H_03H, 0xD3, 0x03, IAP_F_FM | IAP_F_IBX), 1737 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), /* Not defined for IBX */ 1738 IAPDESCR(D3H_0CH, 0xD3, 0x0C, IAP_F_FM | IAP_F_IBX), 1739 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_FM | IAP_F_IBX ), 1740 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_FM | IAP_F_IBX ), 1741 1742 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1743 IAP_F_I7 | IAP_F_WM), 1744 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1745 IAP_F_SB | IAP_F_SBX), 1746 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1747 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1748 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1749 1750 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1751 IAP_F_I7 | IAP_F_WM), 1752 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1753 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1754 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1755 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1756 1757 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1758 1759 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1760 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1761 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1762 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1763 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1764 1765 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1766 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1767 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1768 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1769 1770 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1771 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1772 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1773 1774 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1775 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1776 1777 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1778 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1779 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1780 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1781 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1782 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1783 1784 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1785 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1786 IAP_F_WM), 1787 1788 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1789 1790 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1791 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1792 1793 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1794 1795 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1796 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1797 IAP_F_WM | IAP_F_SBX | IAP_F_CAS | IAP_F_SL), 1798 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1799 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_FM | IAP_F_CAS), 1800 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_FM | IAP_F_CAS), 1801 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB | 1802 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1803 1804 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_FM | IAP_F_CAS), 1805 1806 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1807 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1808 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1809 1810 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1811 1812 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1813 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1814 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1815 IAP_F_BW | IAP_F_BWX), 1816 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1817 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1818 IAP_F_BW | IAP_F_BWX), 1819 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1820 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1821 IAP_F_BW | IAP_F_BWX), 1822 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1823 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1824 IAP_F_BW | IAP_F_BWX), 1825 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1826 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1827 IAP_F_BW | IAP_F_BWX), 1828 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1829 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1830 IAP_F_BW | IAP_F_BWX), 1831 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1832 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1833 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1834 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1835 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1836 IAP_F_BW | IAP_F_BWX), 1837 1838 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1839 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1840 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1841 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1842 IAP_F_BW | IAP_F_BWX), 1843 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1844 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1845 IAP_F_BW | IAP_F_BWX ), 1846 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1847 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX | 1848 IAP_F_BW | IAP_F_BWX | IAP_F_SL), 1849 1850 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1851 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1852 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1853 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1854 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1855 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1856 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX | IAP_F_BW | IAP_F_BWX), 1857 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1858 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1859 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1860 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1861 IAP_F_IBX), 1862 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1863 1864 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1865 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1866 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1867 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1868 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1869 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1870 1871 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1872 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1873 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1874 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1875 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1876 IAP_F_SB | IAP_F_SBX), 1877 1878 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1879 1880 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1881 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1882 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1883 1884 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1885 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1886 1887 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1888 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1889 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1890 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1891 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1892 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1893 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1894 }; 1895 1896 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1897 1898 static pmc_value_t 1899 iap_perfctr_value_to_reload_count(pmc_value_t v) 1900 { 1901 1902 /* If the PMC has overflowed, return a reload count of zero. */ 1903 if ((v & (1ULL << (core_iap_width - 1))) == 0) 1904 return (0); 1905 v &= (1ULL << core_iap_width) - 1; 1906 return (1ULL << core_iap_width) - v; 1907 } 1908 1909 static pmc_value_t 1910 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1911 { 1912 return (1ULL << core_iap_width) - rlc; 1913 } 1914 1915 static int 1916 iap_pmc_has_overflowed(int ri) 1917 { 1918 uint64_t v; 1919 1920 /* 1921 * We treat a Core (i.e., Intel architecture v1) PMC as has 1922 * having overflowed if its MSB is zero. 1923 */ 1924 v = rdpmc(ri); 1925 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1926 } 1927 1928 /* 1929 * Check an event against the set of supported architectural events. 1930 * 1931 * If the event is not architectural EV_IS_NOTARCH is returned. 1932 * If the event is architectural and supported on this CPU, the correct 1933 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. 1934 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. 1935 */ 1936 1937 static int 1938 iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) 1939 { 1940 enum core_arch_events ae; 1941 1942 switch (pe) { 1943 case PMC_EV_IAP_ARCH_UNH_COR_CYC: 1944 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1945 *map = PMC_EV_IAP_EVENT_3CH_00H; 1946 break; 1947 case PMC_EV_IAP_ARCH_INS_RET: 1948 ae = CORE_AE_INSTRUCTION_RETIRED; 1949 *map = PMC_EV_IAP_EVENT_C0H_00H; 1950 break; 1951 case PMC_EV_IAP_ARCH_UNH_REF_CYC: 1952 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1953 *map = PMC_EV_IAP_EVENT_3CH_01H; 1954 break; 1955 case PMC_EV_IAP_ARCH_LLC_REF: 1956 ae = CORE_AE_LLC_REFERENCE; 1957 *map = PMC_EV_IAP_EVENT_2EH_4FH; 1958 break; 1959 case PMC_EV_IAP_ARCH_LLC_MIS: 1960 ae = CORE_AE_LLC_MISSES; 1961 *map = PMC_EV_IAP_EVENT_2EH_41H; 1962 break; 1963 case PMC_EV_IAP_ARCH_BR_INS_RET: 1964 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1965 *map = PMC_EV_IAP_EVENT_C4H_00H; 1966 break; 1967 case PMC_EV_IAP_ARCH_BR_MIS_RET: 1968 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1969 *map = PMC_EV_IAP_EVENT_C5H_00H; 1970 break; 1971 1972 default: /* Non architectural event. */ 1973 return (EV_IS_NOTARCH); 1974 } 1975 1976 return (((core_architectural_events & (1 << ae)) == 0) ? 1977 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); 1978 } 1979 1980 static int 1981 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1982 { 1983 uint32_t mask; 1984 1985 switch (pe) { 1986 /* 1987 * Events valid only on counter 0, 1. 1988 */ 1989 case PMC_EV_IAP_EVENT_40H_01H: 1990 case PMC_EV_IAP_EVENT_40H_02H: 1991 case PMC_EV_IAP_EVENT_40H_04H: 1992 case PMC_EV_IAP_EVENT_40H_08H: 1993 case PMC_EV_IAP_EVENT_40H_0FH: 1994 case PMC_EV_IAP_EVENT_41H_02H: 1995 case PMC_EV_IAP_EVENT_41H_04H: 1996 case PMC_EV_IAP_EVENT_41H_08H: 1997 case PMC_EV_IAP_EVENT_42H_01H: 1998 case PMC_EV_IAP_EVENT_42H_02H: 1999 case PMC_EV_IAP_EVENT_42H_04H: 2000 case PMC_EV_IAP_EVENT_42H_08H: 2001 case PMC_EV_IAP_EVENT_43H_01H: 2002 case PMC_EV_IAP_EVENT_43H_02H: 2003 case PMC_EV_IAP_EVENT_51H_01H: 2004 case PMC_EV_IAP_EVENT_51H_02H: 2005 case PMC_EV_IAP_EVENT_51H_04H: 2006 case PMC_EV_IAP_EVENT_51H_08H: 2007 case PMC_EV_IAP_EVENT_63H_01H: 2008 case PMC_EV_IAP_EVENT_63H_02H: 2009 mask = 0x3; 2010 break; 2011 2012 default: 2013 mask = ~0; /* Any row index is ok. */ 2014 } 2015 2016 return (mask & (1 << ri)); 2017 } 2018 2019 static int 2020 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 2021 { 2022 uint32_t mask; 2023 2024 switch (pe) { 2025 /* 2026 * Events valid only on counter 0. 2027 */ 2028 case PMC_EV_IAP_EVENT_60H_01H: 2029 case PMC_EV_IAP_EVENT_60H_02H: 2030 case PMC_EV_IAP_EVENT_60H_04H: 2031 case PMC_EV_IAP_EVENT_60H_08H: 2032 case PMC_EV_IAP_EVENT_B3H_01H: 2033 case PMC_EV_IAP_EVENT_B3H_02H: 2034 case PMC_EV_IAP_EVENT_B3H_04H: 2035 mask = 0x1; 2036 break; 2037 2038 /* 2039 * Events valid only on counter 0, 1. 2040 */ 2041 case PMC_EV_IAP_EVENT_4CH_01H: 2042 case PMC_EV_IAP_EVENT_4EH_01H: 2043 case PMC_EV_IAP_EVENT_4EH_02H: 2044 case PMC_EV_IAP_EVENT_4EH_04H: 2045 case PMC_EV_IAP_EVENT_51H_01H: 2046 case PMC_EV_IAP_EVENT_51H_02H: 2047 case PMC_EV_IAP_EVENT_51H_04H: 2048 case PMC_EV_IAP_EVENT_51H_08H: 2049 case PMC_EV_IAP_EVENT_63H_01H: 2050 case PMC_EV_IAP_EVENT_63H_02H: 2051 mask = 0x3; 2052 break; 2053 2054 default: 2055 mask = ~0; /* Any row index is ok. */ 2056 } 2057 2058 return (mask & (1 << ri)); 2059 } 2060 2061 static int 2062 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 2063 { 2064 uint32_t mask; 2065 2066 switch (pe) { 2067 /* Events valid only on counter 0. */ 2068 case PMC_EV_IAP_EVENT_B7H_01H: 2069 mask = 0x1; 2070 break; 2071 /* Events valid only on counter 1. */ 2072 case PMC_EV_IAP_EVENT_C0H_01H: 2073 mask = 0x2; 2074 break; 2075 /* Events valid only on counter 2. */ 2076 case PMC_EV_IAP_EVENT_48H_01H: 2077 case PMC_EV_IAP_EVENT_A2H_02H: 2078 case PMC_EV_IAP_EVENT_A3H_08H: 2079 mask = 0x4; 2080 break; 2081 /* Events valid only on counter 3. */ 2082 case PMC_EV_IAP_EVENT_BBH_01H: 2083 case PMC_EV_IAP_EVENT_CDH_01H: 2084 case PMC_EV_IAP_EVENT_CDH_02H: 2085 mask = 0x8; 2086 break; 2087 default: 2088 mask = ~0; /* Any row index is ok. */ 2089 } 2090 2091 return (mask & (1 << ri)); 2092 } 2093 2094 static int 2095 iap_event_ok_on_counter(enum pmc_event pe, int ri) 2096 { 2097 uint32_t mask; 2098 2099 switch (pe) { 2100 /* 2101 * Events valid only on counter 0. 2102 */ 2103 case PMC_EV_IAP_EVENT_10H_00H: 2104 case PMC_EV_IAP_EVENT_14H_00H: 2105 case PMC_EV_IAP_EVENT_18H_00H: 2106 case PMC_EV_IAP_EVENT_B3H_01H: 2107 case PMC_EV_IAP_EVENT_B3H_02H: 2108 case PMC_EV_IAP_EVENT_B3H_04H: 2109 case PMC_EV_IAP_EVENT_C1H_00H: 2110 case PMC_EV_IAP_EVENT_CBH_01H: 2111 case PMC_EV_IAP_EVENT_CBH_02H: 2112 mask = (1 << 0); 2113 break; 2114 2115 /* 2116 * Events valid only on counter 1. 2117 */ 2118 case PMC_EV_IAP_EVENT_11H_00H: 2119 case PMC_EV_IAP_EVENT_12H_00H: 2120 case PMC_EV_IAP_EVENT_13H_00H: 2121 mask = (1 << 1); 2122 break; 2123 2124 default: 2125 mask = ~0; /* Any row index is ok. */ 2126 } 2127 2128 return (mask & (1 << ri)); 2129 } 2130 2131 static int 2132 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 2133 const struct pmc_op_pmcallocate *a) 2134 { 2135 int arch, n, model; 2136 enum pmc_event ev, map; 2137 struct iap_event_descr *ie; 2138 uint32_t c, caps, config, cpuflag, evsel, mask; 2139 2140 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2141 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2142 KASSERT(ri >= 0 && ri < core_iap_npmc, 2143 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 2144 2145 /* check requested capabilities */ 2146 caps = a->pm_caps; 2147 if ((IAP_PMC_CAPS & caps) != caps) 2148 return (EPERM); 2149 map = 0; /* XXX: silent GCC warning */ 2150 arch = iap_is_event_architectural(pm->pm_event, &map); 2151 if (arch == EV_IS_ARCH_NOTSUPP) 2152 return (EOPNOTSUPP); 2153 else if (arch == EV_IS_ARCH_SUPP) 2154 ev = map; 2155 else 2156 ev = pm->pm_event; 2157 2158 /* 2159 * A small number of events are not supported in all the 2160 * processors based on a given microarchitecture. 2161 */ 2162 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 2163 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 2164 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 2165 return (EINVAL); 2166 } 2167 2168 switch (core_cputype) { 2169 case PMC_CPU_INTEL_COREI7: 2170 case PMC_CPU_INTEL_NEHALEM_EX: 2171 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 2172 return (EINVAL); 2173 break; 2174 case PMC_CPU_INTEL_SKYLAKE: 2175 case PMC_CPU_INTEL_BROADWELL: 2176 case PMC_CPU_INTEL_BROADWELL_XEON: 2177 case PMC_CPU_INTEL_SANDYBRIDGE: 2178 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2179 case PMC_CPU_INTEL_IVYBRIDGE: 2180 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2181 case PMC_CPU_INTEL_HASWELL: 2182 case PMC_CPU_INTEL_HASWELL_XEON: 2183 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 2184 return (EINVAL); 2185 break; 2186 case PMC_CPU_INTEL_WESTMERE: 2187 case PMC_CPU_INTEL_WESTMERE_EX: 2188 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 2189 return (EINVAL); 2190 break; 2191 default: 2192 if (iap_event_ok_on_counter(ev, ri) == 0) 2193 return (EINVAL); 2194 } 2195 2196 /* 2197 * Look for an event descriptor with matching CPU and event id 2198 * fields. 2199 */ 2200 2201 switch (core_cputype) { 2202 default: 2203 case PMC_CPU_INTEL_ATOM: 2204 cpuflag = IAP_F_CA; 2205 break; 2206 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2207 cpuflag = IAP_F_CAS; 2208 break; 2209 case PMC_CPU_INTEL_SKYLAKE: 2210 cpuflag = IAP_F_SL; 2211 break; 2212 case PMC_CPU_INTEL_BROADWELL_XEON: 2213 cpuflag = IAP_F_BWX; 2214 break; 2215 case PMC_CPU_INTEL_BROADWELL: 2216 cpuflag = IAP_F_BW; 2217 break; 2218 case PMC_CPU_INTEL_CORE: 2219 cpuflag = IAP_F_CC; 2220 break; 2221 case PMC_CPU_INTEL_CORE2: 2222 cpuflag = IAP_F_CC2; 2223 break; 2224 case PMC_CPU_INTEL_CORE2EXTREME: 2225 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 2226 break; 2227 case PMC_CPU_INTEL_COREI7: 2228 cpuflag = IAP_F_I7; 2229 break; 2230 case PMC_CPU_INTEL_HASWELL: 2231 cpuflag = IAP_F_HW; 2232 break; 2233 case PMC_CPU_INTEL_HASWELL_XEON: 2234 cpuflag = IAP_F_HWX; 2235 break; 2236 case PMC_CPU_INTEL_IVYBRIDGE: 2237 cpuflag = IAP_F_IB; 2238 break; 2239 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2240 cpuflag = IAP_F_IBX; 2241 break; 2242 case PMC_CPU_INTEL_SANDYBRIDGE: 2243 cpuflag = IAP_F_SB; 2244 break; 2245 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2246 cpuflag = IAP_F_SBX; 2247 break; 2248 case PMC_CPU_INTEL_WESTMERE: 2249 cpuflag = IAP_F_WM; 2250 break; 2251 } 2252 2253 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 2254 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2255 break; 2256 2257 if (n == niap_events) 2258 return (EINVAL); 2259 2260 /* 2261 * A matching event descriptor has been found, so start 2262 * assembling the contents of the event select register. 2263 */ 2264 evsel = ie->iap_evcode; 2265 2266 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2267 2268 /* 2269 * If the event uses a fixed umask value, reject any umask 2270 * bits set by the user. 2271 */ 2272 if (ie->iap_flags & IAP_F_FM) { 2273 2274 if (IAP_UMASK(config) != 0) 2275 return (EINVAL); 2276 2277 evsel |= (ie->iap_umask << 8); 2278 2279 } else { 2280 2281 /* 2282 * Otherwise, the UMASK value needs to be taken from 2283 * the MD fields of the allocation request. Reject 2284 * requests that specify reserved bits. 2285 */ 2286 2287 mask = 0; 2288 2289 if (ie->iap_umask & IAP_M_CORE) { 2290 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2291 c != IAP_CORE_THIS) 2292 return (EINVAL); 2293 mask |= IAP_F_CORE; 2294 } 2295 2296 if (ie->iap_umask & IAP_M_AGENT) 2297 mask |= IAP_F_AGENT; 2298 2299 if (ie->iap_umask & IAP_M_PREFETCH) { 2300 2301 if ((c = (config & IAP_F_PREFETCH)) == 2302 IAP_PREFETCH_RESERVED) 2303 return (EINVAL); 2304 2305 mask |= IAP_F_PREFETCH; 2306 } 2307 2308 if (ie->iap_umask & IAP_M_MESI) 2309 mask |= IAP_F_MESI; 2310 2311 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2312 mask |= IAP_F_SNOOPRESPONSE; 2313 2314 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2315 mask |= IAP_F_SNOOPTYPE; 2316 2317 if (ie->iap_umask & IAP_M_TRANSITION) 2318 mask |= IAP_F_TRANSITION; 2319 2320 /* 2321 * If bits outside of the allowed set of umask bits 2322 * are set, reject the request. 2323 */ 2324 if (config & ~mask) 2325 return (EINVAL); 2326 2327 evsel |= (config & mask); 2328 2329 } 2330 2331 /* 2332 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2333 */ 2334 if (core_cputype == PMC_CPU_INTEL_ATOM || 2335 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 2336 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2337 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2338 evsel |= (config & IAP_ANY); 2339 else if (config & IAP_ANY) 2340 return (EINVAL); 2341 2342 /* 2343 * Check offcore response configuration. 2344 */ 2345 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2346 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2347 ev != PMC_EV_IAP_EVENT_BBH_01H) 2348 return (EINVAL); 2349 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2350 ev == PMC_EV_IAP_EVENT_BBH_01H) 2351 return (EINVAL); 2352 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2353 core_cputype == PMC_CPU_INTEL_WESTMERE || 2354 core_cputype == PMC_CPU_INTEL_NEHALEM_EX || 2355 core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && 2356 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2357 return (EINVAL); 2358 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2359 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2360 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2361 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2362 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2363 return (EINVAL); 2364 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2365 } 2366 2367 if (caps & PMC_CAP_THRESHOLD) 2368 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2369 if (caps & PMC_CAP_USER) 2370 evsel |= IAP_USR; 2371 if (caps & PMC_CAP_SYSTEM) 2372 evsel |= IAP_OS; 2373 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2374 evsel |= (IAP_OS | IAP_USR); 2375 if (caps & PMC_CAP_EDGE) 2376 evsel |= IAP_EDGE; 2377 if (caps & PMC_CAP_INVERT) 2378 evsel |= IAP_INV; 2379 if (caps & PMC_CAP_INTERRUPT) 2380 evsel |= IAP_INT; 2381 2382 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2383 2384 return (0); 2385 } 2386 2387 static int 2388 iap_config_pmc(int cpu, int ri, struct pmc *pm) 2389 { 2390 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2391 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2392 2393 KASSERT(ri >= 0 && ri < core_iap_npmc, 2394 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2395 2396 PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2397 2398 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2399 cpu)); 2400 2401 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2402 2403 return (0); 2404 } 2405 2406 static int 2407 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2408 { 2409 int error; 2410 struct pmc_hw *phw; 2411 char iap_name[PMC_NAME_MAX]; 2412 2413 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2414 2415 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2416 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2417 NULL)) != 0) 2418 return (error); 2419 2420 pi->pm_class = PMC_CLASS_IAP; 2421 2422 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2423 pi->pm_enabled = TRUE; 2424 *ppmc = phw->phw_pmc; 2425 } else { 2426 pi->pm_enabled = FALSE; 2427 *ppmc = NULL; 2428 } 2429 2430 return (0); 2431 } 2432 2433 static int 2434 iap_get_config(int cpu, int ri, struct pmc **ppm) 2435 { 2436 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2437 2438 return (0); 2439 } 2440 2441 static int 2442 iap_get_msr(int ri, uint32_t *msr) 2443 { 2444 KASSERT(ri >= 0 && ri < core_iap_npmc, 2445 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2446 2447 *msr = ri; 2448 2449 return (0); 2450 } 2451 2452 static int 2453 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2454 { 2455 struct pmc *pm; 2456 pmc_value_t tmp; 2457 2458 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2459 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2460 KASSERT(ri >= 0 && ri < core_iap_npmc, 2461 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2462 2463 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2464 2465 KASSERT(pm, 2466 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2467 ri)); 2468 2469 tmp = rdpmc(ri); 2470 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2471 *v = iap_perfctr_value_to_reload_count(tmp); 2472 else 2473 *v = tmp & ((1ULL << core_iap_width) - 1); 2474 2475 PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2476 ri, *v); 2477 2478 return (0); 2479 } 2480 2481 static int 2482 iap_release_pmc(int cpu, int ri, struct pmc *pm) 2483 { 2484 (void) pm; 2485 2486 PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2487 pm); 2488 2489 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2490 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2491 KASSERT(ri >= 0 && ri < core_iap_npmc, 2492 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2493 2494 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2495 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2496 2497 return (0); 2498 } 2499 2500 static int 2501 iap_start_pmc(int cpu, int ri) 2502 { 2503 struct pmc *pm; 2504 uint32_t evsel; 2505 struct core_cpu *cc; 2506 2507 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2508 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2509 KASSERT(ri >= 0 && ri < core_iap_npmc, 2510 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2511 2512 cc = core_pcpu[cpu]; 2513 pm = cc->pc_corepmcs[ri].phw_pmc; 2514 2515 KASSERT(pm, 2516 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2517 __LINE__, cpu, ri)); 2518 2519 PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2520 2521 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2522 2523 PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2524 cpu, ri, IAP_EVSEL0 + ri, evsel); 2525 2526 /* Event specific configuration. */ 2527 switch (pm->pm_event) { 2528 case PMC_EV_IAP_EVENT_B7H_01H: 2529 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2530 break; 2531 case PMC_EV_IAP_EVENT_BBH_01H: 2532 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2533 break; 2534 default: 2535 break; 2536 } 2537 2538 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2539 2540 if (core_cputype == PMC_CPU_INTEL_CORE) 2541 return (0); 2542 2543 do { 2544 cc->pc_resync = 0; 2545 cc->pc_globalctrl |= (1ULL << ri); 2546 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2547 } while (cc->pc_resync != 0); 2548 2549 return (0); 2550 } 2551 2552 static int 2553 iap_stop_pmc(int cpu, int ri) 2554 { 2555 struct pmc *pm; 2556 struct core_cpu *cc; 2557 uint64_t msr; 2558 2559 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2560 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2561 KASSERT(ri >= 0 && ri < core_iap_npmc, 2562 ("[core,%d] illegal row index %d", __LINE__, ri)); 2563 2564 cc = core_pcpu[cpu]; 2565 pm = cc->pc_corepmcs[ri].phw_pmc; 2566 2567 KASSERT(pm, 2568 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2569 cpu, ri)); 2570 2571 PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2572 2573 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2574 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2575 2576 if (core_cputype == PMC_CPU_INTEL_CORE) 2577 return (0); 2578 2579 msr = 0; 2580 do { 2581 cc->pc_resync = 0; 2582 cc->pc_globalctrl &= ~(1ULL << ri); 2583 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2584 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2585 } while (cc->pc_resync != 0); 2586 2587 return (0); 2588 } 2589 2590 static int 2591 iap_write_pmc(int cpu, int ri, pmc_value_t v) 2592 { 2593 struct pmc *pm; 2594 struct core_cpu *cc; 2595 2596 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2597 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2598 KASSERT(ri >= 0 && ri < core_iap_npmc, 2599 ("[core,%d] illegal row index %d", __LINE__, ri)); 2600 2601 cc = core_pcpu[cpu]; 2602 pm = cc->pc_corepmcs[ri].phw_pmc; 2603 2604 KASSERT(pm, 2605 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2606 cpu, ri)); 2607 2608 PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2609 IAP_PMC0 + ri, v); 2610 2611 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2612 v = iap_reload_count_to_perfctr_value(v); 2613 2614 /* 2615 * Write the new value to the counter. The counter will be in 2616 * a stopped state when the pcd_write() entry point is called. 2617 */ 2618 2619 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2620 2621 return (0); 2622 } 2623 2624 2625 static void 2626 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2627 int flags) 2628 { 2629 struct pmc_classdep *pcd; 2630 2631 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2632 2633 PMCDBG0(MDP,INI,1, "iap-initialize"); 2634 2635 /* Remember the set of architectural events supported. */ 2636 core_architectural_events = ~flags; 2637 2638 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2639 2640 pcd->pcd_caps = IAP_PMC_CAPS; 2641 pcd->pcd_class = PMC_CLASS_IAP; 2642 pcd->pcd_num = npmc; 2643 pcd->pcd_ri = md->pmd_npmc; 2644 pcd->pcd_width = pmcwidth; 2645 2646 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2647 pcd->pcd_config_pmc = iap_config_pmc; 2648 pcd->pcd_describe = iap_describe; 2649 pcd->pcd_get_config = iap_get_config; 2650 pcd->pcd_get_msr = iap_get_msr; 2651 pcd->pcd_pcpu_fini = core_pcpu_fini; 2652 pcd->pcd_pcpu_init = core_pcpu_init; 2653 pcd->pcd_read_pmc = iap_read_pmc; 2654 pcd->pcd_release_pmc = iap_release_pmc; 2655 pcd->pcd_start_pmc = iap_start_pmc; 2656 pcd->pcd_stop_pmc = iap_stop_pmc; 2657 pcd->pcd_write_pmc = iap_write_pmc; 2658 2659 md->pmd_npmc += npmc; 2660 } 2661 2662 static int 2663 core_intr(int cpu, struct trapframe *tf) 2664 { 2665 pmc_value_t v; 2666 struct pmc *pm; 2667 struct core_cpu *cc; 2668 int error, found_interrupt, ri; 2669 uint64_t msr; 2670 2671 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2672 TRAPF_USERMODE(tf)); 2673 2674 found_interrupt = 0; 2675 cc = core_pcpu[cpu]; 2676 2677 for (ri = 0; ri < core_iap_npmc; ri++) { 2678 2679 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2680 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2681 continue; 2682 2683 if (!iap_pmc_has_overflowed(ri)) 2684 continue; 2685 2686 found_interrupt = 1; 2687 2688 if (pm->pm_state != PMC_STATE_RUNNING) 2689 continue; 2690 2691 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2692 TRAPF_USERMODE(tf)); 2693 2694 v = pm->pm_sc.pm_reloadcount; 2695 v = iap_reload_count_to_perfctr_value(v); 2696 2697 /* 2698 * Stop the counter, reload it but only restart it if 2699 * the PMC is not stalled. 2700 */ 2701 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2702 wrmsr(IAP_EVSEL0 + ri, msr); 2703 wrmsr(IAP_PMC0 + ri, v); 2704 2705 if (error) 2706 continue; 2707 2708 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2709 IAP_EN)); 2710 } 2711 2712 if (found_interrupt) 2713 lapic_reenable_pmc(); 2714 2715 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2716 &pmc_stats.pm_intr_ignored, 1); 2717 2718 return (found_interrupt); 2719 } 2720 2721 static int 2722 core2_intr(int cpu, struct trapframe *tf) 2723 { 2724 int error, found_interrupt, n; 2725 uint64_t flag, intrstatus, intrenable, msr; 2726 struct pmc *pm; 2727 struct core_cpu *cc; 2728 pmc_value_t v; 2729 2730 PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2731 TRAPF_USERMODE(tf)); 2732 2733 /* 2734 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2735 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2736 * the current set of interrupting PMCs and process these 2737 * after stopping them. 2738 */ 2739 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2740 intrenable = intrstatus & core_pmcmask; 2741 2742 PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2743 (uintmax_t) intrstatus); 2744 2745 found_interrupt = 0; 2746 cc = core_pcpu[cpu]; 2747 2748 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2749 2750 cc->pc_globalctrl &= ~intrenable; 2751 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2752 2753 /* 2754 * Stop PMCs and clear overflow status bits. 2755 */ 2756 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2757 wrmsr(IA_GLOBAL_CTRL, msr); 2758 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2759 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2760 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2761 2762 /* 2763 * Look for interrupts from fixed function PMCs. 2764 */ 2765 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2766 n++, flag <<= 1) { 2767 2768 if ((intrstatus & flag) == 0) 2769 continue; 2770 2771 found_interrupt = 1; 2772 2773 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2774 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2775 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2776 continue; 2777 2778 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2779 TRAPF_USERMODE(tf)); 2780 if (error) 2781 intrenable &= ~flag; 2782 2783 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2784 2785 /* Reload sampling count. */ 2786 wrmsr(IAF_CTR0 + n, v); 2787 2788 PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 2789 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2790 } 2791 2792 /* 2793 * Process interrupts from the programmable counters. 2794 */ 2795 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2796 if ((intrstatus & flag) == 0) 2797 continue; 2798 2799 found_interrupt = 1; 2800 2801 pm = cc->pc_corepmcs[n].phw_pmc; 2802 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2803 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2804 continue; 2805 2806 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2807 TRAPF_USERMODE(tf)); 2808 if (error) 2809 intrenable &= ~flag; 2810 2811 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2812 2813 PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2814 (uintmax_t) v); 2815 2816 /* Reload sampling count. */ 2817 wrmsr(IAP_PMC0 + n, v); 2818 } 2819 2820 /* 2821 * Reenable all non-stalled PMCs. 2822 */ 2823 PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2824 (uintmax_t) intrenable); 2825 2826 cc->pc_globalctrl |= intrenable; 2827 2828 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2829 2830 PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2831 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2832 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2833 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2834 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2835 2836 if (found_interrupt) 2837 lapic_reenable_pmc(); 2838 2839 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2840 &pmc_stats.pm_intr_ignored, 1); 2841 2842 return (found_interrupt); 2843 } 2844 2845 int 2846 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 2847 { 2848 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2849 int ipa_version, flags, nflags; 2850 2851 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2852 2853 ipa_version = (version_override > 0) ? version_override : 2854 cpuid[CORE_CPUID_EAX] & 0xFF; 2855 core_cputype = md->pmd_cputype; 2856 2857 PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2858 core_cputype, maxcpu, ipa_version); 2859 2860 if (ipa_version < 1 || ipa_version > 3 || 2861 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 2862 /* Unknown PMC architecture. */ 2863 printf("hwpc_core: unknown PMC architecture: %d\n", 2864 ipa_version); 2865 return (EPROGMISMATCH); 2866 } 2867 2868 core_pmcmask = 0; 2869 2870 /* 2871 * Initialize programmable counters. 2872 */ 2873 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2874 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2875 2876 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2877 2878 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2879 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2880 2881 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2882 2883 /* 2884 * Initialize fixed function counters, if present. 2885 */ 2886 if (core_cputype != PMC_CPU_INTEL_CORE) { 2887 core_iaf_ri = core_iap_npmc; 2888 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2889 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2890 2891 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2892 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2893 } 2894 2895 PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2896 core_iaf_ri); 2897 2898 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 2899 M_ZERO | M_WAITOK); 2900 2901 /* 2902 * Choose the appropriate interrupt handler. 2903 */ 2904 if (ipa_version == 1) 2905 md->pmd_intr = core_intr; 2906 else 2907 md->pmd_intr = core2_intr; 2908 2909 md->pmd_pcpu_fini = NULL; 2910 md->pmd_pcpu_init = NULL; 2911 2912 return (0); 2913 } 2914 2915 void 2916 pmc_core_finalize(struct pmc_mdep *md) 2917 { 2918 PMCDBG0(MDP,INI,1, "core-finalize"); 2919 2920 free(core_pcpu, M_PMC); 2921 core_pcpu = NULL; 2922 } 2923