1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core, Core 2 and Atom PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #include <machine/apicvar.h> 42 #include <machine/cpu.h> 43 #include <machine/cpufunc.h> 44 #include <machine/md_var.h> 45 #include <machine/specialreg.h> 46 47 #define CORE_CPUID_REQUEST 0xA 48 #define CORE_CPUID_REQUEST_SIZE 0x4 49 #define CORE_CPUID_EAX 0x0 50 #define CORE_CPUID_EBX 0x1 51 #define CORE_CPUID_ECX 0x2 52 #define CORE_CPUID_EDX 0x3 53 54 #define IAF_PMC_CAPS \ 55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 56 PMC_CAP_USER | PMC_CAP_SYSTEM) 57 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 58 59 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 62 63 /* 64 * "Architectural" events defined by Intel. The values of these 65 * symbols correspond to positions in the bitmask returned by 66 * the CPUID.0AH instruction. 67 */ 68 enum core_arch_events { 69 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 70 CORE_AE_BRANCH_MISSES_RETIRED = 6, 71 CORE_AE_INSTRUCTION_RETIRED = 1, 72 CORE_AE_LLC_MISSES = 4, 73 CORE_AE_LLC_REFERENCE = 3, 74 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 75 CORE_AE_UNHALTED_CORE_CYCLES = 0 76 }; 77 78 static enum pmc_cputype core_cputype; 79 80 struct core_cpu { 81 volatile uint32_t pc_resync; 82 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 83 volatile uint64_t pc_globalctrl; /* Global control register. */ 84 struct pmc_hw pc_corepmcs[]; 85 }; 86 87 static struct core_cpu **core_pcpu; 88 89 static uint32_t core_architectural_events; 90 static uint64_t core_pmcmask; 91 92 static int core_iaf_ri; /* relative index of fixed counters */ 93 static int core_iaf_width; 94 static int core_iaf_npmc; 95 96 static int core_iap_width; 97 static int core_iap_npmc; 98 99 static int 100 core_pcpu_noop(struct pmc_mdep *md, int cpu) 101 { 102 (void) md; 103 (void) cpu; 104 return (0); 105 } 106 107 static int 108 core_pcpu_init(struct pmc_mdep *md, int cpu) 109 { 110 struct pmc_cpu *pc; 111 struct core_cpu *cc; 112 struct pmc_hw *phw; 113 int core_ri, n, npmc; 114 115 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 116 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 117 118 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 119 120 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 121 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 122 123 if (core_cputype != PMC_CPU_INTEL_CORE) 124 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 125 126 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 127 M_PMC, M_WAITOK | M_ZERO); 128 129 core_pcpu[cpu] = cc; 130 pc = pmc_pcpu[cpu]; 131 132 KASSERT(pc != NULL && cc != NULL, 133 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 134 135 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 136 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 137 PMC_PHW_CPU_TO_STATE(cpu) | 138 PMC_PHW_INDEX_TO_STATE(n + core_ri); 139 phw->phw_pmc = NULL; 140 pc->pc_hwpmcs[n + core_ri] = phw; 141 } 142 143 return (0); 144 } 145 146 static int 147 core_pcpu_fini(struct pmc_mdep *md, int cpu) 148 { 149 int core_ri, n, npmc; 150 struct pmc_cpu *pc; 151 struct core_cpu *cc; 152 uint64_t msr = 0; 153 154 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 155 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 156 157 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 158 159 if ((cc = core_pcpu[cpu]) == NULL) 160 return (0); 161 162 core_pcpu[cpu] = NULL; 163 164 pc = pmc_pcpu[cpu]; 165 166 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 167 cpu)); 168 169 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 170 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 171 172 for (n = 0; n < npmc; n++) { 173 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 174 wrmsr(IAP_EVSEL0 + n, msr); 175 } 176 177 if (core_cputype != PMC_CPU_INTEL_CORE) { 178 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 179 wrmsr(IAF_CTRL, msr); 180 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 181 } 182 183 for (n = 0; n < npmc; n++) 184 pc->pc_hwpmcs[n + core_ri] = NULL; 185 186 free(cc, M_PMC); 187 188 return (0); 189 } 190 191 /* 192 * Fixed function counters. 193 */ 194 195 static pmc_value_t 196 iaf_perfctr_value_to_reload_count(pmc_value_t v) 197 { 198 v &= (1ULL << core_iaf_width) - 1; 199 return (1ULL << core_iaf_width) - v; 200 } 201 202 static pmc_value_t 203 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 204 { 205 return (1ULL << core_iaf_width) - rlc; 206 } 207 208 static int 209 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 210 const struct pmc_op_pmcallocate *a) 211 { 212 enum pmc_event ev; 213 uint32_t caps, flags, validflags; 214 215 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 216 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 217 218 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 219 220 if (ri < 0 || ri > core_iaf_npmc) 221 return (EINVAL); 222 223 caps = a->pm_caps; 224 225 if (a->pm_class != PMC_CLASS_IAF || 226 (caps & IAF_PMC_CAPS) != caps) 227 return (EINVAL); 228 229 ev = pm->pm_event; 230 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 231 return (EINVAL); 232 233 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 234 return (EINVAL); 235 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 236 return (EINVAL); 237 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 238 return (EINVAL); 239 240 flags = a->pm_md.pm_iaf.pm_iaf_flags; 241 242 validflags = IAF_MASK; 243 244 if (core_cputype != PMC_CPU_INTEL_ATOM) 245 validflags &= ~IAF_ANY; 246 247 if ((flags & ~validflags) != 0) 248 return (EINVAL); 249 250 if (caps & PMC_CAP_INTERRUPT) 251 flags |= IAF_PMI; 252 if (caps & PMC_CAP_SYSTEM) 253 flags |= IAF_OS; 254 if (caps & PMC_CAP_USER) 255 flags |= IAF_USR; 256 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 257 flags |= (IAF_OS | IAF_USR); 258 259 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 260 261 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 262 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 263 264 return (0); 265 } 266 267 static int 268 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 269 { 270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 271 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 272 273 KASSERT(ri >= 0 && ri < core_iaf_npmc, 274 ("[core,%d] illegal row-index %d", __LINE__, ri)); 275 276 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 277 278 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 279 cpu)); 280 281 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 282 283 return (0); 284 } 285 286 static int 287 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 288 { 289 int error; 290 struct pmc_hw *phw; 291 char iaf_name[PMC_NAME_MAX]; 292 293 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 294 295 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 296 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 297 NULL)) != 0) 298 return (error); 299 300 pi->pm_class = PMC_CLASS_IAF; 301 302 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 303 pi->pm_enabled = TRUE; 304 *ppmc = phw->phw_pmc; 305 } else { 306 pi->pm_enabled = FALSE; 307 *ppmc = NULL; 308 } 309 310 return (0); 311 } 312 313 static int 314 iaf_get_config(int cpu, int ri, struct pmc **ppm) 315 { 316 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 317 318 return (0); 319 } 320 321 static int 322 iaf_get_msr(int ri, uint32_t *msr) 323 { 324 KASSERT(ri >= 0 && ri < core_iaf_npmc, 325 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 326 327 *msr = IAF_RI_TO_MSR(ri); 328 329 return (0); 330 } 331 332 static int 333 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 334 { 335 struct pmc *pm; 336 pmc_value_t tmp; 337 338 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 339 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 340 KASSERT(ri >= 0 && ri < core_iaf_npmc, 341 ("[core,%d] illegal row-index %d", __LINE__, ri)); 342 343 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 344 345 KASSERT(pm, 346 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 347 ri, ri + core_iaf_ri)); 348 349 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 350 351 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 352 *v = iaf_perfctr_value_to_reload_count(tmp); 353 else 354 *v = tmp; 355 356 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 357 IAF_RI_TO_MSR(ri), *v); 358 359 return (0); 360 } 361 362 static int 363 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 364 { 365 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 366 367 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 368 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 369 KASSERT(ri >= 0 && ri < core_iaf_npmc, 370 ("[core,%d] illegal row-index %d", __LINE__, ri)); 371 372 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 373 ("[core,%d] PHW pmc non-NULL", __LINE__)); 374 375 return (0); 376 } 377 378 static int 379 iaf_start_pmc(int cpu, int ri) 380 { 381 struct pmc *pm; 382 struct core_cpu *iafc; 383 uint64_t msr = 0; 384 385 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 386 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 387 KASSERT(ri >= 0 && ri < core_iaf_npmc, 388 ("[core,%d] illegal row-index %d", __LINE__, ri)); 389 390 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 391 392 iafc = core_pcpu[cpu]; 393 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 394 395 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 396 397 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 398 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 399 400 do { 401 iafc->pc_resync = 0; 402 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 403 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 404 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 405 IAF_GLOBAL_CTRL_MASK)); 406 } while (iafc->pc_resync != 0); 407 408 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 409 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 410 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 411 412 return (0); 413 } 414 415 static int 416 iaf_stop_pmc(int cpu, int ri) 417 { 418 uint32_t fc; 419 struct core_cpu *iafc; 420 uint64_t msr = 0; 421 422 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 423 424 iafc = core_pcpu[cpu]; 425 426 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 427 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 428 KASSERT(ri >= 0 && ri < core_iaf_npmc, 429 ("[core,%d] illegal row-index %d", __LINE__, ri)); 430 431 fc = (IAF_MASK << (ri * 4)); 432 433 if (core_cputype != PMC_CPU_INTEL_ATOM) 434 fc &= ~IAF_ANY; 435 436 iafc->pc_iafctrl &= ~fc; 437 438 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 439 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 440 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 441 442 do { 443 iafc->pc_resync = 0; 444 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 445 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 446 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 447 IAF_GLOBAL_CTRL_MASK)); 448 } while (iafc->pc_resync != 0); 449 450 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 451 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 452 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 453 454 return (0); 455 } 456 457 static int 458 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 459 { 460 struct core_cpu *cc; 461 struct pmc *pm; 462 uint64_t msr; 463 464 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 465 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 466 KASSERT(ri >= 0 && ri < core_iaf_npmc, 467 ("[core,%d] illegal row-index %d", __LINE__, ri)); 468 469 cc = core_pcpu[cpu]; 470 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 471 472 KASSERT(pm, 473 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 474 475 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 476 v = iaf_reload_count_to_perfctr_value(v); 477 478 /* Turn off fixed counters */ 479 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 480 wrmsr(IAF_CTRL, msr); 481 482 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 483 484 /* Turn on fixed counters */ 485 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 486 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 487 488 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 489 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 490 (uintmax_t) rdmsr(IAF_CTRL), 491 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 492 493 return (0); 494 } 495 496 497 static void 498 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 499 { 500 struct pmc_classdep *pcd; 501 502 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 503 504 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 505 506 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 507 508 pcd->pcd_caps = IAF_PMC_CAPS; 509 pcd->pcd_class = PMC_CLASS_IAF; 510 pcd->pcd_num = npmc; 511 pcd->pcd_ri = md->pmd_npmc; 512 pcd->pcd_width = pmcwidth; 513 514 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 515 pcd->pcd_config_pmc = iaf_config_pmc; 516 pcd->pcd_describe = iaf_describe; 517 pcd->pcd_get_config = iaf_get_config; 518 pcd->pcd_get_msr = iaf_get_msr; 519 pcd->pcd_pcpu_fini = core_pcpu_noop; 520 pcd->pcd_pcpu_init = core_pcpu_noop; 521 pcd->pcd_read_pmc = iaf_read_pmc; 522 pcd->pcd_release_pmc = iaf_release_pmc; 523 pcd->pcd_start_pmc = iaf_start_pmc; 524 pcd->pcd_stop_pmc = iaf_stop_pmc; 525 pcd->pcd_write_pmc = iaf_write_pmc; 526 527 md->pmd_npmc += npmc; 528 } 529 530 /* 531 * Intel programmable PMCs. 532 */ 533 534 /* 535 * Event descriptor tables. 536 * 537 * For each event id, we track: 538 * 539 * 1. The CPUs that the event is valid for. 540 * 541 * 2. If the event uses a fixed UMASK, the value of the umask field. 542 * If the event doesn't use a fixed UMASK, a mask of legal bits 543 * to check against. 544 */ 545 546 struct iap_event_descr { 547 enum pmc_event iap_ev; 548 unsigned char iap_evcode; 549 unsigned char iap_umask; 550 unsigned int iap_flags; 551 }; 552 553 #define IAP_F_CC (1 << 0) /* CPU: Core */ 554 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 555 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 556 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 557 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 558 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 559 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 560 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 561 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 562 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 563 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge */ 564 #define IAP_F_FM (1 << 10) /* Fixed mask */ 565 566 #define IAP_F_ALLCPUSCORE2 \ 567 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 568 569 /* Sub fields of UMASK that this event supports. */ 570 #define IAP_M_CORE (1 << 0) /* Core specificity */ 571 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 572 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 573 #define IAP_M_MESI (1 << 3) /* MESI */ 574 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 575 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 576 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 577 578 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 579 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 580 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 581 #define IAP_F_MESI (0xF << 8) /* MESI */ 582 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 583 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 584 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 585 586 #define IAP_PREFETCH_RESERVED (0x2 << 12) 587 #define IAP_CORE_THIS (0x1 << 14) 588 #define IAP_CORE_ALL (0x3 << 14) 589 #define IAP_F_CMASK 0xFF000000 590 591 static struct iap_event_descr iap_events[] = { 592 #undef IAPDESCR 593 #define IAPDESCR(N,EV,UM,FLAGS) { \ 594 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 595 .iap_evcode = (EV), \ 596 .iap_umask = (UM), \ 597 .iap_flags = (FLAGS) \ 598 } 599 600 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 601 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 602 603 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 604 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 605 IAP_F_SBX), 606 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 607 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 608 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 609 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 610 IAP_F_SBX), 611 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 612 IAP_F_SBX), 613 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 614 615 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC), 616 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 617 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 618 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 619 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 620 621 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 622 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 623 IAP_F_SBX | IAP_F_IBX), 624 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB | 625 IAP_F_SBX | IAP_F_IBX), 626 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O), 627 628 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 629 IAP_F_CC2E | IAP_F_CA), 630 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 631 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 632 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 633 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 634 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 635 636 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 637 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 638 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 639 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 640 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 641 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 642 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 643 IAP_F_SBX), 644 645 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 646 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), 647 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 648 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), 649 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 650 IAP_F_WM | IAP_F_SB | IAP_F_SBX), 651 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 652 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 653 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 654 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 655 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 656 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 657 IAP_F_SBX), 658 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 659 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O), 660 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7), 661 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 662 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 663 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 664 665 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 666 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 667 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 668 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 669 670 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 671 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 672 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 673 674 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 675 IAP_F_WM), 676 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 677 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 678 679 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 680 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 681 682 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 683 IAP_F_SBX | IAP_F_IBX), 684 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 685 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 686 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 687 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 688 689 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 690 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 691 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 692 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 693 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 694 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 695 696 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 697 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 698 IAP_F_WM | IAP_F_SB | IAP_F_SBX), 699 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 700 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 701 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 702 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 703 IAP_F_SBX), 704 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 705 IAP_F_SBX), 706 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 707 IAP_F_SBX), 708 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 709 IAP_F_SBX), 710 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 711 712 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 713 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 714 IAP_F_SBX), 715 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 716 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 717 718 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 719 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 720 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 721 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 722 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 723 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 724 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 725 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 726 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 727 728 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 729 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 730 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 731 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 732 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 733 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 734 735 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 736 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 737 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 738 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 739 740 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 741 IAP_F_SBX), 742 743 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 744 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 745 746 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 747 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 748 IAP_F_I7 | IAP_F_WM), 749 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 750 751 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 752 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 753 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 754 755 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 756 757 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 758 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 759 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 760 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 761 762 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 763 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 764 IAP_F_SBX | IAP_F_IBX), 765 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 766 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 767 IAP_F_SBX | IAP_F_IBX), 768 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 769 IAP_F_SBX | IAP_F_IBX), 770 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 771 IAP_F_SBX | IAP_F_IBX), 772 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 773 IAP_F_SBX | IAP_F_IBX), 774 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 775 IAP_F_SBX | IAP_F_IBX), 776 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 777 IAP_F_SBX | IAP_F_IBX), 778 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 779 IAP_F_SBX | IAP_F_IBX), 780 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 781 IAP_F_SBX | IAP_F_IBX), 782 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 783 IAP_F_SBX | IAP_F_IBX), 784 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 785 IAP_F_SBX | IAP_F_IBX), 786 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 787 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 788 789 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 790 791 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 792 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 793 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 794 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 795 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 796 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 797 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 798 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 799 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 800 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 801 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 802 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 803 804 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 805 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 806 IAP_F_SBX | IAP_F_IBX), 807 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 808 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 809 IAP_F_SBX), 810 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 811 IAP_F_SBX | IAP_F_IBX), 812 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 813 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 814 IAP_F_SBX | IAP_F_IBX), 815 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 816 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 817 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 818 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 819 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 820 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 821 822 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 823 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX | 824 IAP_F_IBX), 825 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 826 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 827 IAP_F_SBX | IAP_F_IBX), 828 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | 829 IAP_F_SBX | IAP_F_IBX), 830 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX | 831 IAP_F_IBX), 832 833 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 834 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 835 IAP_F_CA | IAP_F_CC2), 836 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 837 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 838 839 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 840 IAP_F_ALLCPUSCORE2), 841 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 842 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 843 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 844 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 845 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 846 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 847 848 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 849 IAP_F_ALLCPUSCORE2), 850 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 851 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 852 853 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 854 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 855 856 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 857 858 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 859 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 860 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 861 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 862 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 863 864 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 865 866 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 867 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 868 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 869 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 870 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 871 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 872 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 873 874 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 875 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 876 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 877 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 878 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 879 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 880 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 881 882 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 883 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 884 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 885 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 886 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 887 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 888 889 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 890 IAP_F_I7), 891 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 892 IAP_F_CC2 | IAP_F_I7), 893 894 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 895 896 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 897 898 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 899 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 900 901 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 902 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 903 IAP_F_SBX | IAP_F_IBX), 904 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 905 906 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 907 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 908 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 909 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 910 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 911 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 912 IAP_F_SBX | IAP_F_IBX), 913 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 914 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 915 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7), 916 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O), 917 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7), 918 919 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 920 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 921 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 922 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 923 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 924 925 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 926 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 927 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 928 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 929 IAP_F_SBX | IAP_F_IBX), 930 931 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 932 933 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 934 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 935 IAP_F_SB | IAP_F_SBX), 936 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 937 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 938 939 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 940 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 941 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 942 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 943 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 944 945 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 946 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 947 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 948 IAP_F_SB | IAP_F_SBX), 949 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 950 IAP_F_SB | IAP_F_SBX), 951 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 952 IAP_F_SB | IAP_F_SBX), 953 954 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 955 956 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 957 958 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 959 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 960 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 961 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 962 963 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 964 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 965 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 966 967 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 968 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 969 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 970 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 971 972 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 973 IAP_F_SBX | IAP_F_IBX), 974 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 975 IAP_F_SBX | IAP_F_IBX), 976 977 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 978 IAP_F_SBX | IAP_F_IBX), 979 980 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB), 981 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX), 982 983 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 984 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 985 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 986 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 987 IAP_F_IBX), 988 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 989 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 990 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 991 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 992 993 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 994 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 995 996 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 997 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 998 999 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1000 IAP_F_CA | IAP_F_CC2), 1001 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1002 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1003 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1004 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1005 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1006 1007 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1008 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1009 1010 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1011 IAP_F_CA | IAP_F_CC2), 1012 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1013 1014 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1015 1016 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1017 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1018 1019 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1020 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1021 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1022 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1023 1024 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1025 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1026 1027 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1028 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1029 1030 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1031 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1032 1033 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1034 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1035 1036 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1037 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1038 1039 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1040 IAP_F_CA | IAP_F_CC2), 1041 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1042 1043 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1044 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1045 1046 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1047 IAP_F_SBX | IAP_F_IBX), 1048 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1049 IAP_F_SBX | IAP_F_IBX), 1050 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1051 IAP_F_SBX | IAP_F_IBX), 1052 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1053 IAP_F_SBX | IAP_F_IBX), 1054 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1055 IAP_F_SBX | IAP_F_IBX), 1056 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1057 IAP_F_SBX | IAP_F_IBX), 1058 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 1059 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 1060 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 1061 1062 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1063 1064 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1065 1066 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1067 1068 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1069 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1070 1071 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1072 1073 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1074 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1075 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1076 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1077 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1078 IAP_F_WM), 1079 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1080 1081 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1082 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1083 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1084 1085 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1086 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1087 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1088 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1089 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1090 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1091 1092 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1093 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1094 1095 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1096 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1097 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1098 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1099 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1100 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1101 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1102 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1103 IAP_F_SBX | IAP_F_IBX), 1104 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O), 1105 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O), 1106 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1107 1108 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1109 1110 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1111 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1112 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1113 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1114 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1115 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1116 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1117 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1118 1119 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1120 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1121 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1122 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1123 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1124 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1125 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1126 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1127 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1128 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1129 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1130 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1131 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1132 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1133 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1134 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1135 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1136 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1137 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1138 IAP_F_SBX | IAP_F_IBX), 1139 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1140 IAP_F_SBX | IAP_F_IBX), 1141 1142 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1143 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1144 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1145 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1146 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1147 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1148 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1149 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1150 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1151 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1152 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1153 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1154 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1155 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1156 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1157 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1158 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1159 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1160 IAP_F_SBX | IAP_F_IBX), 1161 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1162 IAP_F_SBX | IAP_F_IBX), 1163 1164 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1165 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1166 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1167 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1168 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1169 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1170 1171 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1172 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1173 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1174 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1175 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1176 1177 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1178 IAP_F_SBX | IAP_F_IBX), 1179 1180 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1181 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1182 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1183 1184 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1185 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1186 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1187 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1188 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1189 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1190 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1191 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1192 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1193 IAP_F_SBX | IAP_F_IBX), 1194 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1195 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1196 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1197 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1198 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1199 IAP_F_SBX | IAP_F_IBX), 1200 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1201 IAP_F_SBX | IAP_F_IBX), 1202 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1203 IAP_F_SBX | IAP_F_IBX), 1204 1205 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1206 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1207 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1208 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1209 IAP_F_SB | IAP_F_SBX), 1210 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1211 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1212 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1213 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1214 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1215 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1216 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1217 IAP_F_SB | IAP_F_SBX), 1218 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1219 IAP_F_SB | IAP_F_SBX), 1220 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1221 IAP_F_SB | IAP_F_SBX), 1222 1223 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1224 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1225 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1226 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_IBX), 1227 1228 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1229 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1230 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1231 1232 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1233 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1234 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1235 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1236 1237 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1238 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1239 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1240 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1241 1242 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1243 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1244 IAP_F_SBX | IAP_F_IBX), 1245 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1246 1247 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1248 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1249 1250 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1251 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1252 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1253 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1254 IAP_F_IBX), 1255 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1256 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1257 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1258 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1259 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1260 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1261 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1262 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1263 1264 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1265 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1266 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1267 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1268 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1269 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1270 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1271 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1272 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1273 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1274 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1275 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1276 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1277 IAP_F_WM), 1278 1279 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1280 IAP_F_SB | IAP_F_SBX), 1281 1282 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1283 IAP_F_WM | IAP_F_I7O), 1284 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1285 IAP_F_WM | IAP_F_I7O), 1286 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1287 IAP_F_WM | IAP_F_I7O), 1288 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1289 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1290 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1291 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1292 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1293 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1294 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1295 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1296 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1297 1298 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1299 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1300 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1301 1302 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1303 1304 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1305 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1306 1307 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1308 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1309 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1310 1311 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1312 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1313 1314 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1315 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1316 1317 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1318 IAP_F_SBX | IAP_F_IBX), 1319 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1320 IAP_F_SBX | IAP_F_IBX), 1321 1322 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1323 1324 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1325 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1326 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1327 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1328 IAP_F_IBX), 1329 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1330 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1331 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1332 IAP_F_I7 | IAP_F_WM), 1333 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1334 1335 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1336 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1337 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1338 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1339 IAP_F_SBX | IAP_F_IBX), 1340 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1341 IAP_F_SBX | IAP_F_IBX), 1342 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1343 IAP_F_SBX | IAP_F_IBX), 1344 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1345 1346 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1347 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1348 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1349 IAP_F_IBX), 1350 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1351 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1352 IAP_F_IBX), 1353 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1354 IAP_F_I7 | IAP_F_WM), 1355 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1356 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1357 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1358 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA), 1359 1360 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1361 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1362 IAP_F_I7 | IAP_F_WM), 1363 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1364 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1365 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1366 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1367 IAP_F_IBX), 1368 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1369 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1370 IAP_F_SBX | IAP_F_IBX), 1371 1372 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1373 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1374 IAP_F_IBX), 1375 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1376 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1377 IAP_F_IBX), 1378 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1379 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1380 IAP_F_IBX), 1381 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1382 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1383 IAP_F_IBX), 1384 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1385 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1386 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1387 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1388 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1389 IAP_F_SBX | IAP_F_IBX), 1390 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1391 IAP_F_SBX | IAP_F_IBX), 1392 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1393 IAP_F_SBX | IAP_F_IBX), 1394 1395 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1396 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1397 IAP_F_IBX), 1398 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1399 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1400 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1401 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1402 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1403 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1404 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1405 IAP_F_SBX | IAP_F_IBX), 1406 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1407 IAP_F_SBX | IAP_F_IBX), 1408 1409 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1410 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1411 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1412 1413 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1414 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1415 IAP_F_I7 | IAP_F_WM), 1416 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1417 IAP_F_I7 | IAP_F_WM), 1418 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1419 IAP_F_I7 | IAP_F_WM), 1420 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1421 IAP_F_I7 | IAP_F_WM), 1422 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1423 IAP_F_I7 | IAP_F_WM), 1424 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1425 1426 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1427 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1428 1429 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1430 1431 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1432 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1433 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1434 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1435 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1436 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1437 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1438 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1439 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1440 IAP_F_SBX | IAP_F_IBX), 1441 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1442 IAP_F_SBX | IAP_F_IBX), 1443 1444 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1445 IAP_F_I7 | IAP_F_WM), 1446 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1447 IAP_F_I7 | IAP_F_WM), 1448 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1449 IAP_F_I7 | IAP_F_WM), 1450 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1451 IAP_F_I7 | IAP_F_WM), 1452 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1453 IAP_F_WM), 1454 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1455 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1456 1457 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1458 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1459 IAP_F_I7 | IAP_F_WM), 1460 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1461 IAP_F_I7 | IAP_F_WM), 1462 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1463 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1464 IAP_F_SBX | IAP_F_IBX), 1465 1466 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1467 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1468 IAP_F_SBX | IAP_F_IBX), 1469 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1470 IAP_F_SBX | IAP_F_IBX), 1471 1472 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1473 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1474 1475 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1476 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1477 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1478 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1479 IAP_F_SBX | IAP_F_IBX), 1480 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1481 IAP_F_SBX | IAP_F_IBX), 1482 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1483 IAP_F_SBX | IAP_F_IBX), 1484 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1485 IAP_F_SBX | IAP_F_IBX), 1486 IAPDESCR(D0H_80H, 0xD0, 0X80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1487 IAP_F_SBX | IAP_F_IBX), 1488 1489 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1490 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1491 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1492 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1493 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1494 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1495 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1496 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1497 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1498 IAP_F_SBX | IAP_F_IBX), 1499 1500 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1501 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX), 1502 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1503 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX), 1504 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1505 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX), 1506 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1507 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX), 1508 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1509 IAP_F_I7 | IAP_F_WM), 1510 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1511 1512 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1513 IAP_F_IBX), 1514 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1515 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX), 1516 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX), 1517 1518 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1519 IAP_F_I7 | IAP_F_WM), 1520 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1521 IAP_F_SB | IAP_F_SBX), 1522 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1523 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1524 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1525 1526 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1527 IAP_F_I7 | IAP_F_WM), 1528 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1529 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1530 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1531 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1532 1533 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1534 1535 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1536 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1537 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1538 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1539 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1540 1541 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1542 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1543 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1544 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1545 1546 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1547 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1548 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1549 1550 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1551 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1552 1553 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1554 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1555 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1556 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1557 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1558 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1559 1560 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1561 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1562 IAP_F_WM), 1563 1564 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1565 1566 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1567 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1568 1569 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1570 1571 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1572 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1573 IAP_F_WM | IAP_F_SBX), 1574 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1575 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_IBX), 1576 1577 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1578 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1579 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1580 1581 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1582 1583 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1584 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1585 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1586 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1587 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1588 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1589 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1590 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1591 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1592 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1593 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1594 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1595 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1596 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1597 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1598 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1599 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1600 1601 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1602 IAP_F_SBX | IAP_F_IBX), 1603 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1604 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1605 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1606 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1607 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1608 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1609 1610 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1611 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1612 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1613 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1614 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1615 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1616 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1617 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1618 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1619 IAP_F_IBX), 1620 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1621 1622 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1623 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1624 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1625 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1626 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1627 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1628 1629 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1630 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1631 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1632 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1633 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1634 IAP_F_SB | IAP_F_SBX), 1635 1636 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1637 1638 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1639 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1640 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1641 1642 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1643 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1644 1645 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1646 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1647 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1648 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1649 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1650 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1651 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1652 }; 1653 1654 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1655 1656 static pmc_value_t 1657 iap_perfctr_value_to_reload_count(pmc_value_t v) 1658 { 1659 v &= (1ULL << core_iap_width) - 1; 1660 return (1ULL << core_iap_width) - v; 1661 } 1662 1663 static pmc_value_t 1664 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1665 { 1666 return (1ULL << core_iap_width) - rlc; 1667 } 1668 1669 static int 1670 iap_pmc_has_overflowed(int ri) 1671 { 1672 uint64_t v; 1673 1674 /* 1675 * We treat a Core (i.e., Intel architecture v1) PMC as has 1676 * having overflowed if its MSB is zero. 1677 */ 1678 v = rdpmc(ri); 1679 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1680 } 1681 1682 /* 1683 * Check an event against the set of supported architectural events. 1684 * 1685 * Returns 1 if the event is architectural and unsupported on this 1686 * CPU. Returns 0 otherwise. 1687 */ 1688 1689 static int 1690 iap_architectural_event_is_unsupported(enum pmc_event pe) 1691 { 1692 enum core_arch_events ae; 1693 1694 switch (pe) { 1695 case PMC_EV_IAP_EVENT_3CH_00H: 1696 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1697 break; 1698 case PMC_EV_IAP_EVENT_C0H_00H: 1699 ae = CORE_AE_INSTRUCTION_RETIRED; 1700 break; 1701 case PMC_EV_IAP_EVENT_3CH_01H: 1702 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1703 break; 1704 case PMC_EV_IAP_EVENT_2EH_4FH: 1705 ae = CORE_AE_LLC_REFERENCE; 1706 break; 1707 case PMC_EV_IAP_EVENT_2EH_41H: 1708 ae = CORE_AE_LLC_MISSES; 1709 break; 1710 case PMC_EV_IAP_EVENT_C4H_00H: 1711 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1712 break; 1713 case PMC_EV_IAP_EVENT_C5H_00H: 1714 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1715 break; 1716 1717 default: /* Non architectural event. */ 1718 return (0); 1719 } 1720 1721 return ((core_architectural_events & (1 << ae)) == 0); 1722 } 1723 1724 static int 1725 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1726 { 1727 uint32_t mask; 1728 1729 switch (pe) { 1730 /* 1731 * Events valid only on counter 0, 1. 1732 */ 1733 case PMC_EV_IAP_EVENT_40H_01H: 1734 case PMC_EV_IAP_EVENT_40H_02H: 1735 case PMC_EV_IAP_EVENT_40H_04H: 1736 case PMC_EV_IAP_EVENT_40H_08H: 1737 case PMC_EV_IAP_EVENT_40H_0FH: 1738 case PMC_EV_IAP_EVENT_41H_02H: 1739 case PMC_EV_IAP_EVENT_41H_04H: 1740 case PMC_EV_IAP_EVENT_41H_08H: 1741 case PMC_EV_IAP_EVENT_42H_01H: 1742 case PMC_EV_IAP_EVENT_42H_02H: 1743 case PMC_EV_IAP_EVENT_42H_04H: 1744 case PMC_EV_IAP_EVENT_42H_08H: 1745 case PMC_EV_IAP_EVENT_43H_01H: 1746 case PMC_EV_IAP_EVENT_43H_02H: 1747 case PMC_EV_IAP_EVENT_51H_01H: 1748 case PMC_EV_IAP_EVENT_51H_02H: 1749 case PMC_EV_IAP_EVENT_51H_04H: 1750 case PMC_EV_IAP_EVENT_51H_08H: 1751 case PMC_EV_IAP_EVENT_63H_01H: 1752 case PMC_EV_IAP_EVENT_63H_02H: 1753 mask = 0x3; 1754 break; 1755 1756 default: 1757 mask = ~0; /* Any row index is ok. */ 1758 } 1759 1760 return (mask & (1 << ri)); 1761 } 1762 1763 static int 1764 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1765 { 1766 uint32_t mask; 1767 1768 switch (pe) { 1769 /* 1770 * Events valid only on counter 0. 1771 */ 1772 case PMC_EV_IAP_EVENT_60H_01H: 1773 case PMC_EV_IAP_EVENT_60H_02H: 1774 case PMC_EV_IAP_EVENT_60H_04H: 1775 case PMC_EV_IAP_EVENT_60H_08H: 1776 case PMC_EV_IAP_EVENT_B3H_01H: 1777 case PMC_EV_IAP_EVENT_B3H_02H: 1778 case PMC_EV_IAP_EVENT_B3H_04H: 1779 mask = 0x1; 1780 break; 1781 1782 /* 1783 * Events valid only on counter 0, 1. 1784 */ 1785 case PMC_EV_IAP_EVENT_4CH_01H: 1786 case PMC_EV_IAP_EVENT_4EH_01H: 1787 case PMC_EV_IAP_EVENT_4EH_02H: 1788 case PMC_EV_IAP_EVENT_4EH_04H: 1789 case PMC_EV_IAP_EVENT_51H_01H: 1790 case PMC_EV_IAP_EVENT_51H_02H: 1791 case PMC_EV_IAP_EVENT_51H_04H: 1792 case PMC_EV_IAP_EVENT_51H_08H: 1793 case PMC_EV_IAP_EVENT_63H_01H: 1794 case PMC_EV_IAP_EVENT_63H_02H: 1795 mask = 0x3; 1796 break; 1797 1798 default: 1799 mask = ~0; /* Any row index is ok. */ 1800 } 1801 1802 return (mask & (1 << ri)); 1803 } 1804 1805 static int 1806 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 1807 { 1808 uint32_t mask; 1809 1810 switch (pe) { 1811 /* Events valid only on counter 0. */ 1812 case PMC_EV_IAP_EVENT_B7H_01H: 1813 mask = 0x1; 1814 break; 1815 /* Events valid only on counter 1. */ 1816 case PMC_EV_IAP_EVENT_C0H_01H: 1817 mask = 0x1; 1818 break; 1819 /* Events valid only on counter 2. */ 1820 case PMC_EV_IAP_EVENT_48H_01H: 1821 case PMC_EV_IAP_EVENT_A2H_02H: 1822 mask = 0x4; 1823 break; 1824 /* Events valid only on counter 3. */ 1825 case PMC_EV_IAP_EVENT_A3H_08H: 1826 case PMC_EV_IAP_EVENT_BBH_01H: 1827 case PMC_EV_IAP_EVENT_CDH_01H: 1828 case PMC_EV_IAP_EVENT_CDH_02H: 1829 mask = 0x8; 1830 break; 1831 default: 1832 mask = ~0; /* Any row index is ok. */ 1833 } 1834 1835 return (mask & (1 << ri)); 1836 } 1837 1838 static int 1839 iap_event_ok_on_counter(enum pmc_event pe, int ri) 1840 { 1841 uint32_t mask; 1842 1843 switch (pe) { 1844 /* 1845 * Events valid only on counter 0. 1846 */ 1847 case PMC_EV_IAP_EVENT_10H_00H: 1848 case PMC_EV_IAP_EVENT_14H_00H: 1849 case PMC_EV_IAP_EVENT_18H_00H: 1850 case PMC_EV_IAP_EVENT_B3H_01H: 1851 case PMC_EV_IAP_EVENT_B3H_02H: 1852 case PMC_EV_IAP_EVENT_B3H_04H: 1853 case PMC_EV_IAP_EVENT_C1H_00H: 1854 case PMC_EV_IAP_EVENT_CBH_01H: 1855 case PMC_EV_IAP_EVENT_CBH_02H: 1856 mask = (1 << 0); 1857 break; 1858 1859 /* 1860 * Events valid only on counter 1. 1861 */ 1862 case PMC_EV_IAP_EVENT_11H_00H: 1863 case PMC_EV_IAP_EVENT_12H_00H: 1864 case PMC_EV_IAP_EVENT_13H_00H: 1865 mask = (1 << 1); 1866 break; 1867 1868 default: 1869 mask = ~0; /* Any row index is ok. */ 1870 } 1871 1872 return (mask & (1 << ri)); 1873 } 1874 1875 static int 1876 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1877 const struct pmc_op_pmcallocate *a) 1878 { 1879 int n, model; 1880 enum pmc_event ev; 1881 struct iap_event_descr *ie; 1882 uint32_t c, caps, config, cpuflag, evsel, mask; 1883 1884 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1885 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1886 KASSERT(ri >= 0 && ri < core_iap_npmc, 1887 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1888 1889 /* check requested capabilities */ 1890 caps = a->pm_caps; 1891 if ((IAP_PMC_CAPS & caps) != caps) 1892 return (EPERM); 1893 1894 ev = pm->pm_event; 1895 1896 if (iap_architectural_event_is_unsupported(ev)) 1897 return (EOPNOTSUPP); 1898 1899 /* 1900 * A small number of events are not supported in all the 1901 * processors based on a given microarchitecture. 1902 */ 1903 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 1904 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 1905 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 1906 return (EINVAL); 1907 } 1908 1909 switch (core_cputype) { 1910 case PMC_CPU_INTEL_COREI7: 1911 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 1912 return (EINVAL); 1913 break; 1914 case PMC_CPU_INTEL_SANDYBRIDGE: 1915 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 1916 case PMC_CPU_INTEL_IVYBRIDGE: 1917 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 1918 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 1919 return (EINVAL); 1920 break; 1921 case PMC_CPU_INTEL_WESTMERE: 1922 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 1923 return (EINVAL); 1924 break; 1925 default: 1926 if (iap_event_ok_on_counter(ev, ri) == 0) 1927 return (EINVAL); 1928 } 1929 1930 /* 1931 * Look for an event descriptor with matching CPU and event id 1932 * fields. 1933 */ 1934 1935 switch (core_cputype) { 1936 default: 1937 case PMC_CPU_INTEL_ATOM: 1938 cpuflag = IAP_F_CA; 1939 break; 1940 case PMC_CPU_INTEL_CORE: 1941 cpuflag = IAP_F_CC; 1942 break; 1943 case PMC_CPU_INTEL_CORE2: 1944 cpuflag = IAP_F_CC2; 1945 break; 1946 case PMC_CPU_INTEL_CORE2EXTREME: 1947 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 1948 break; 1949 case PMC_CPU_INTEL_COREI7: 1950 cpuflag = IAP_F_I7; 1951 break; 1952 case PMC_CPU_INTEL_IVYBRIDGE: 1953 cpuflag = IAP_F_IB; 1954 break; 1955 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 1956 cpuflag = IAP_F_IBX; 1957 break; 1958 case PMC_CPU_INTEL_SANDYBRIDGE: 1959 cpuflag = IAP_F_SB; 1960 break; 1961 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 1962 cpuflag = IAP_F_SBX; 1963 break; 1964 case PMC_CPU_INTEL_WESTMERE: 1965 cpuflag = IAP_F_WM; 1966 break; 1967 } 1968 1969 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 1970 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 1971 break; 1972 1973 if (n == niap_events) 1974 return (EINVAL); 1975 1976 /* 1977 * A matching event descriptor has been found, so start 1978 * assembling the contents of the event select register. 1979 */ 1980 evsel = ie->iap_evcode; 1981 1982 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 1983 1984 /* 1985 * If the event uses a fixed umask value, reject any umask 1986 * bits set by the user. 1987 */ 1988 if (ie->iap_flags & IAP_F_FM) { 1989 1990 if (IAP_UMASK(config) != 0) 1991 return (EINVAL); 1992 1993 evsel |= (ie->iap_umask << 8); 1994 1995 } else { 1996 1997 /* 1998 * Otherwise, the UMASK value needs to be taken from 1999 * the MD fields of the allocation request. Reject 2000 * requests that specify reserved bits. 2001 */ 2002 2003 mask = 0; 2004 2005 if (ie->iap_umask & IAP_M_CORE) { 2006 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2007 c != IAP_CORE_THIS) 2008 return (EINVAL); 2009 mask |= IAP_F_CORE; 2010 } 2011 2012 if (ie->iap_umask & IAP_M_AGENT) 2013 mask |= IAP_F_AGENT; 2014 2015 if (ie->iap_umask & IAP_M_PREFETCH) { 2016 2017 if ((c = (config & IAP_F_PREFETCH)) == 2018 IAP_PREFETCH_RESERVED) 2019 return (EINVAL); 2020 2021 mask |= IAP_F_PREFETCH; 2022 } 2023 2024 if (ie->iap_umask & IAP_M_MESI) 2025 mask |= IAP_F_MESI; 2026 2027 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2028 mask |= IAP_F_SNOOPRESPONSE; 2029 2030 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2031 mask |= IAP_F_SNOOPTYPE; 2032 2033 if (ie->iap_umask & IAP_M_TRANSITION) 2034 mask |= IAP_F_TRANSITION; 2035 2036 /* 2037 * If bits outside of the allowed set of umask bits 2038 * are set, reject the request. 2039 */ 2040 if (config & ~mask) 2041 return (EINVAL); 2042 2043 evsel |= (config & mask); 2044 2045 } 2046 2047 /* 2048 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2049 */ 2050 if (core_cputype == PMC_CPU_INTEL_ATOM || 2051 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2052 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2053 evsel |= (config & IAP_ANY); 2054 else if (config & IAP_ANY) 2055 return (EINVAL); 2056 2057 /* 2058 * Check offcore response configuration. 2059 */ 2060 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2061 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2062 ev != PMC_EV_IAP_EVENT_BBH_01H) 2063 return (EINVAL); 2064 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2065 ev == PMC_EV_IAP_EVENT_BBH_01H) 2066 return (EINVAL); 2067 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2068 core_cputype == PMC_CPU_INTEL_WESTMERE) && 2069 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2070 return (EINVAL); 2071 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2072 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2073 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2074 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2075 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2076 return (EINVAL); 2077 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2078 } 2079 2080 if (caps & PMC_CAP_THRESHOLD) 2081 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2082 if (caps & PMC_CAP_USER) 2083 evsel |= IAP_USR; 2084 if (caps & PMC_CAP_SYSTEM) 2085 evsel |= IAP_OS; 2086 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2087 evsel |= (IAP_OS | IAP_USR); 2088 if (caps & PMC_CAP_EDGE) 2089 evsel |= IAP_EDGE; 2090 if (caps & PMC_CAP_INVERT) 2091 evsel |= IAP_INV; 2092 if (caps & PMC_CAP_INTERRUPT) 2093 evsel |= IAP_INT; 2094 2095 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2096 2097 return (0); 2098 } 2099 2100 static int 2101 iap_config_pmc(int cpu, int ri, struct pmc *pm) 2102 { 2103 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2104 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2105 2106 KASSERT(ri >= 0 && ri < core_iap_npmc, 2107 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2108 2109 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2110 2111 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2112 cpu)); 2113 2114 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2115 2116 return (0); 2117 } 2118 2119 static int 2120 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2121 { 2122 int error; 2123 struct pmc_hw *phw; 2124 char iap_name[PMC_NAME_MAX]; 2125 2126 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2127 2128 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2129 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2130 NULL)) != 0) 2131 return (error); 2132 2133 pi->pm_class = PMC_CLASS_IAP; 2134 2135 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2136 pi->pm_enabled = TRUE; 2137 *ppmc = phw->phw_pmc; 2138 } else { 2139 pi->pm_enabled = FALSE; 2140 *ppmc = NULL; 2141 } 2142 2143 return (0); 2144 } 2145 2146 static int 2147 iap_get_config(int cpu, int ri, struct pmc **ppm) 2148 { 2149 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2150 2151 return (0); 2152 } 2153 2154 static int 2155 iap_get_msr(int ri, uint32_t *msr) 2156 { 2157 KASSERT(ri >= 0 && ri < core_iap_npmc, 2158 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2159 2160 *msr = ri; 2161 2162 return (0); 2163 } 2164 2165 static int 2166 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2167 { 2168 struct pmc *pm; 2169 pmc_value_t tmp; 2170 2171 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2172 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2173 KASSERT(ri >= 0 && ri < core_iap_npmc, 2174 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2175 2176 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2177 2178 KASSERT(pm, 2179 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2180 ri)); 2181 2182 tmp = rdpmc(ri); 2183 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2184 *v = iap_perfctr_value_to_reload_count(tmp); 2185 else 2186 *v = tmp & ((1ULL << core_iap_width) - 1); 2187 2188 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2189 ri, *v); 2190 2191 return (0); 2192 } 2193 2194 static int 2195 iap_release_pmc(int cpu, int ri, struct pmc *pm) 2196 { 2197 (void) pm; 2198 2199 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2200 pm); 2201 2202 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2203 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2204 KASSERT(ri >= 0 && ri < core_iap_npmc, 2205 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2206 2207 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2208 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2209 2210 return (0); 2211 } 2212 2213 static int 2214 iap_start_pmc(int cpu, int ri) 2215 { 2216 struct pmc *pm; 2217 uint32_t evsel; 2218 struct core_cpu *cc; 2219 2220 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2221 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2222 KASSERT(ri >= 0 && ri < core_iap_npmc, 2223 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2224 2225 cc = core_pcpu[cpu]; 2226 pm = cc->pc_corepmcs[ri].phw_pmc; 2227 2228 KASSERT(pm, 2229 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2230 __LINE__, cpu, ri)); 2231 2232 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2233 2234 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2235 2236 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2237 cpu, ri, IAP_EVSEL0 + ri, evsel); 2238 2239 /* Event specific configuration. */ 2240 switch (pm->pm_event) { 2241 case PMC_EV_IAP_EVENT_B7H_01H: 2242 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2243 break; 2244 case PMC_EV_IAP_EVENT_BBH_01H: 2245 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2246 break; 2247 default: 2248 break; 2249 } 2250 2251 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2252 2253 if (core_cputype == PMC_CPU_INTEL_CORE) 2254 return (0); 2255 2256 do { 2257 cc->pc_resync = 0; 2258 cc->pc_globalctrl |= (1ULL << ri); 2259 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2260 } while (cc->pc_resync != 0); 2261 2262 return (0); 2263 } 2264 2265 static int 2266 iap_stop_pmc(int cpu, int ri) 2267 { 2268 struct pmc *pm; 2269 struct core_cpu *cc; 2270 uint64_t msr; 2271 2272 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2273 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2274 KASSERT(ri >= 0 && ri < core_iap_npmc, 2275 ("[core,%d] illegal row index %d", __LINE__, ri)); 2276 2277 cc = core_pcpu[cpu]; 2278 pm = cc->pc_corepmcs[ri].phw_pmc; 2279 2280 KASSERT(pm, 2281 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2282 cpu, ri)); 2283 2284 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2285 2286 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2287 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2288 2289 if (core_cputype == PMC_CPU_INTEL_CORE) 2290 return (0); 2291 2292 msr = 0; 2293 do { 2294 cc->pc_resync = 0; 2295 cc->pc_globalctrl &= ~(1ULL << ri); 2296 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2297 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2298 } while (cc->pc_resync != 0); 2299 2300 return (0); 2301 } 2302 2303 static int 2304 iap_write_pmc(int cpu, int ri, pmc_value_t v) 2305 { 2306 struct pmc *pm; 2307 struct core_cpu *cc; 2308 2309 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2310 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2311 KASSERT(ri >= 0 && ri < core_iap_npmc, 2312 ("[core,%d] illegal row index %d", __LINE__, ri)); 2313 2314 cc = core_pcpu[cpu]; 2315 pm = cc->pc_corepmcs[ri].phw_pmc; 2316 2317 KASSERT(pm, 2318 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2319 cpu, ri)); 2320 2321 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2322 IAP_PMC0 + ri, v); 2323 2324 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2325 v = iap_reload_count_to_perfctr_value(v); 2326 2327 /* 2328 * Write the new value to the counter. The counter will be in 2329 * a stopped state when the pcd_write() entry point is called. 2330 */ 2331 2332 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2333 2334 return (0); 2335 } 2336 2337 2338 static void 2339 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2340 int flags) 2341 { 2342 struct pmc_classdep *pcd; 2343 2344 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2345 2346 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 2347 2348 /* Remember the set of architectural events supported. */ 2349 core_architectural_events = ~flags; 2350 2351 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2352 2353 pcd->pcd_caps = IAP_PMC_CAPS; 2354 pcd->pcd_class = PMC_CLASS_IAP; 2355 pcd->pcd_num = npmc; 2356 pcd->pcd_ri = md->pmd_npmc; 2357 pcd->pcd_width = pmcwidth; 2358 2359 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2360 pcd->pcd_config_pmc = iap_config_pmc; 2361 pcd->pcd_describe = iap_describe; 2362 pcd->pcd_get_config = iap_get_config; 2363 pcd->pcd_get_msr = iap_get_msr; 2364 pcd->pcd_pcpu_fini = core_pcpu_fini; 2365 pcd->pcd_pcpu_init = core_pcpu_init; 2366 pcd->pcd_read_pmc = iap_read_pmc; 2367 pcd->pcd_release_pmc = iap_release_pmc; 2368 pcd->pcd_start_pmc = iap_start_pmc; 2369 pcd->pcd_stop_pmc = iap_stop_pmc; 2370 pcd->pcd_write_pmc = iap_write_pmc; 2371 2372 md->pmd_npmc += npmc; 2373 } 2374 2375 static int 2376 core_intr(int cpu, struct trapframe *tf) 2377 { 2378 pmc_value_t v; 2379 struct pmc *pm; 2380 struct core_cpu *cc; 2381 int error, found_interrupt, ri; 2382 uint64_t msr; 2383 2384 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2385 TRAPF_USERMODE(tf)); 2386 2387 found_interrupt = 0; 2388 cc = core_pcpu[cpu]; 2389 2390 for (ri = 0; ri < core_iap_npmc; ri++) { 2391 2392 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2393 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2394 continue; 2395 2396 if (!iap_pmc_has_overflowed(ri)) 2397 continue; 2398 2399 found_interrupt = 1; 2400 2401 if (pm->pm_state != PMC_STATE_RUNNING) 2402 continue; 2403 2404 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2405 TRAPF_USERMODE(tf)); 2406 2407 v = pm->pm_sc.pm_reloadcount; 2408 v = iaf_reload_count_to_perfctr_value(v); 2409 2410 /* 2411 * Stop the counter, reload it but only restart it if 2412 * the PMC is not stalled. 2413 */ 2414 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2415 wrmsr(IAP_EVSEL0 + ri, msr); 2416 wrmsr(IAP_PMC0 + ri, v); 2417 2418 if (error) 2419 continue; 2420 2421 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2422 IAP_EN)); 2423 } 2424 2425 if (found_interrupt) 2426 lapic_reenable_pmc(); 2427 2428 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2429 &pmc_stats.pm_intr_ignored, 1); 2430 2431 return (found_interrupt); 2432 } 2433 2434 static int 2435 core2_intr(int cpu, struct trapframe *tf) 2436 { 2437 int error, found_interrupt, n; 2438 uint64_t flag, intrstatus, intrenable, msr; 2439 struct pmc *pm; 2440 struct core_cpu *cc; 2441 pmc_value_t v; 2442 2443 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2444 TRAPF_USERMODE(tf)); 2445 2446 /* 2447 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2448 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2449 * the current set of interrupting PMCs and process these 2450 * after stopping them. 2451 */ 2452 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2453 intrenable = intrstatus & core_pmcmask; 2454 2455 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2456 (uintmax_t) intrstatus); 2457 2458 found_interrupt = 0; 2459 cc = core_pcpu[cpu]; 2460 2461 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2462 2463 cc->pc_globalctrl &= ~intrenable; 2464 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2465 2466 /* 2467 * Stop PMCs and clear overflow status bits. 2468 */ 2469 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2470 wrmsr(IA_GLOBAL_CTRL, msr); 2471 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2472 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2473 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2474 2475 /* 2476 * Look for interrupts from fixed function PMCs. 2477 */ 2478 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2479 n++, flag <<= 1) { 2480 2481 if ((intrstatus & flag) == 0) 2482 continue; 2483 2484 found_interrupt = 1; 2485 2486 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2487 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2488 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2489 continue; 2490 2491 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2492 TRAPF_USERMODE(tf)); 2493 if (error) 2494 intrenable &= ~flag; 2495 2496 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2497 2498 /* Reload sampling count. */ 2499 wrmsr(IAF_CTR0 + n, v); 2500 2501 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, 2502 (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2503 } 2504 2505 /* 2506 * Process interrupts from the programmable counters. 2507 */ 2508 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2509 if ((intrstatus & flag) == 0) 2510 continue; 2511 2512 found_interrupt = 1; 2513 2514 pm = cc->pc_corepmcs[n].phw_pmc; 2515 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2516 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2517 continue; 2518 2519 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2520 TRAPF_USERMODE(tf)); 2521 if (error) 2522 intrenable &= ~flag; 2523 2524 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2525 2526 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2527 (uintmax_t) v); 2528 2529 /* Reload sampling count. */ 2530 wrmsr(IAP_PMC0 + n, v); 2531 } 2532 2533 /* 2534 * Reenable all non-stalled PMCs. 2535 */ 2536 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2537 (uintmax_t) intrenable); 2538 2539 cc->pc_globalctrl |= intrenable; 2540 2541 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2542 2543 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2544 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2545 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2546 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2547 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2548 2549 if (found_interrupt) 2550 lapic_reenable_pmc(); 2551 2552 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2553 &pmc_stats.pm_intr_ignored, 1); 2554 2555 return (found_interrupt); 2556 } 2557 2558 int 2559 pmc_core_initialize(struct pmc_mdep *md, int maxcpu) 2560 { 2561 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2562 int ipa_version, flags, nflags; 2563 2564 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2565 2566 ipa_version = cpuid[CORE_CPUID_EAX] & 0xFF; 2567 2568 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2569 md->pmd_cputype, maxcpu, ipa_version); 2570 2571 if (ipa_version < 1 || ipa_version > 3) { 2572 /* Unknown PMC architecture. */ 2573 printf("hwpc_core: unknown PMC architecture: %d\n", 2574 ipa_version); 2575 return (EPROGMISMATCH); 2576 } 2577 2578 core_cputype = md->pmd_cputype; 2579 2580 core_pmcmask = 0; 2581 2582 /* 2583 * Initialize programmable counters. 2584 */ 2585 KASSERT(ipa_version >= 1, 2586 ("[core,%d] ipa_version %d too small", __LINE__, ipa_version)); 2587 2588 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2589 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2590 2591 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2592 2593 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2594 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2595 2596 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2597 2598 /* 2599 * Initialize fixed function counters, if present. 2600 */ 2601 if (core_cputype != PMC_CPU_INTEL_CORE) { 2602 KASSERT(ipa_version >= 2, 2603 ("[core,%d] ipa_version %d too small", __LINE__, 2604 ipa_version)); 2605 2606 core_iaf_ri = core_iap_npmc; 2607 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2608 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2609 2610 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2611 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2612 } 2613 2614 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2615 core_iaf_ri); 2616 2617 core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, 2618 M_ZERO | M_WAITOK); 2619 2620 /* 2621 * Choose the appropriate interrupt handler. 2622 */ 2623 if (ipa_version == 1) 2624 md->pmd_intr = core_intr; 2625 else 2626 md->pmd_intr = core2_intr; 2627 2628 md->pmd_pcpu_fini = NULL; 2629 md->pmd_pcpu_init = NULL; 2630 2631 return (0); 2632 } 2633 2634 void 2635 pmc_core_finalize(struct pmc_mdep *md) 2636 { 2637 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2638 2639 free(core_pcpu, M_PMC); 2640 core_pcpu = NULL; 2641 } 2642