1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #if (__FreeBSD_version >= 1100000) 42 #include <x86/apicvar.h> 43 #else 44 #include <machine/apicvar.h> 45 #endif 46 #include <machine/cpu.h> 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #define CORE_CPUID_REQUEST 0xA 52 #define CORE_CPUID_REQUEST_SIZE 0x4 53 #define CORE_CPUID_EAX 0x0 54 #define CORE_CPUID_EBX 0x1 55 #define CORE_CPUID_ECX 0x2 56 #define CORE_CPUID_EDX 0x3 57 58 #define IAF_PMC_CAPS \ 59 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 60 PMC_CAP_USER | PMC_CAP_SYSTEM) 61 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 62 63 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 64 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 65 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 66 67 #define EV_IS_NOTARCH 0 68 #define EV_IS_ARCH_SUPP 1 69 #define EV_IS_ARCH_NOTSUPP -1 70 71 /* 72 * "Architectural" events defined by Intel. The values of these 73 * symbols correspond to positions in the bitmask returned by 74 * the CPUID.0AH instruction. 75 */ 76 enum core_arch_events { 77 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 78 CORE_AE_BRANCH_MISSES_RETIRED = 6, 79 CORE_AE_INSTRUCTION_RETIRED = 1, 80 CORE_AE_LLC_MISSES = 4, 81 CORE_AE_LLC_REFERENCE = 3, 82 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 83 CORE_AE_UNHALTED_CORE_CYCLES = 0 84 }; 85 86 static enum pmc_cputype core_cputype; 87 88 struct core_cpu { 89 volatile uint32_t pc_resync; 90 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 91 volatile uint64_t pc_globalctrl; /* Global control register. */ 92 struct pmc_hw pc_corepmcs[]; 93 }; 94 95 static struct core_cpu **core_pcpu; 96 97 static uint32_t core_architectural_events; 98 static uint64_t core_pmcmask; 99 100 static int core_iaf_ri; /* relative index of fixed counters */ 101 static int core_iaf_width; 102 static int core_iaf_npmc; 103 104 static int core_iap_width; 105 static int core_iap_npmc; 106 107 static int 108 core_pcpu_noop(struct pmc_mdep *md, int cpu) 109 { 110 (void) md; 111 (void) cpu; 112 return (0); 113 } 114 115 static int 116 core_pcpu_init(struct pmc_mdep *md, int cpu) 117 { 118 struct pmc_cpu *pc; 119 struct core_cpu *cc; 120 struct pmc_hw *phw; 121 int core_ri, n, npmc; 122 123 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 124 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 125 126 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 127 128 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 129 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 130 131 if (core_cputype != PMC_CPU_INTEL_CORE) 132 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 133 134 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 135 M_PMC, M_WAITOK | M_ZERO); 136 137 core_pcpu[cpu] = cc; 138 pc = pmc_pcpu[cpu]; 139 140 KASSERT(pc != NULL && cc != NULL, 141 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 142 143 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 144 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 145 PMC_PHW_CPU_TO_STATE(cpu) | 146 PMC_PHW_INDEX_TO_STATE(n + core_ri); 147 phw->phw_pmc = NULL; 148 pc->pc_hwpmcs[n + core_ri] = phw; 149 } 150 151 return (0); 152 } 153 154 static int 155 core_pcpu_fini(struct pmc_mdep *md, int cpu) 156 { 157 int core_ri, n, npmc; 158 struct pmc_cpu *pc; 159 struct core_cpu *cc; 160 uint64_t msr = 0; 161 162 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 163 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 164 165 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 166 167 if ((cc = core_pcpu[cpu]) == NULL) 168 return (0); 169 170 core_pcpu[cpu] = NULL; 171 172 pc = pmc_pcpu[cpu]; 173 174 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 175 cpu)); 176 177 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 178 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 179 180 for (n = 0; n < npmc; n++) { 181 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 182 wrmsr(IAP_EVSEL0 + n, msr); 183 } 184 185 if (core_cputype != PMC_CPU_INTEL_CORE) { 186 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 187 wrmsr(IAF_CTRL, msr); 188 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 189 } 190 191 for (n = 0; n < npmc; n++) 192 pc->pc_hwpmcs[n + core_ri] = NULL; 193 194 free(cc, M_PMC); 195 196 return (0); 197 } 198 199 /* 200 * Fixed function counters. 201 */ 202 203 static pmc_value_t 204 iaf_perfctr_value_to_reload_count(pmc_value_t v) 205 { 206 v &= (1ULL << core_iaf_width) - 1; 207 return (1ULL << core_iaf_width) - v; 208 } 209 210 static pmc_value_t 211 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 212 { 213 return (1ULL << core_iaf_width) - rlc; 214 } 215 216 static int 217 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 218 const struct pmc_op_pmcallocate *a) 219 { 220 enum pmc_event ev; 221 uint32_t caps, flags, validflags; 222 223 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 224 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 225 226 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 227 228 if (ri < 0 || ri > core_iaf_npmc) 229 return (EINVAL); 230 231 caps = a->pm_caps; 232 233 if (a->pm_class != PMC_CLASS_IAF || 234 (caps & IAF_PMC_CAPS) != caps) 235 return (EINVAL); 236 237 ev = pm->pm_event; 238 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 239 return (EINVAL); 240 241 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 242 return (EINVAL); 243 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 244 return (EINVAL); 245 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 246 return (EINVAL); 247 248 flags = a->pm_md.pm_iaf.pm_iaf_flags; 249 250 validflags = IAF_MASK; 251 252 if (core_cputype != PMC_CPU_INTEL_ATOM && 253 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 254 validflags &= ~IAF_ANY; 255 256 if ((flags & ~validflags) != 0) 257 return (EINVAL); 258 259 if (caps & PMC_CAP_INTERRUPT) 260 flags |= IAF_PMI; 261 if (caps & PMC_CAP_SYSTEM) 262 flags |= IAF_OS; 263 if (caps & PMC_CAP_USER) 264 flags |= IAF_USR; 265 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 266 flags |= (IAF_OS | IAF_USR); 267 268 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 269 270 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 271 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 272 273 return (0); 274 } 275 276 static int 277 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 278 { 279 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 280 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 281 282 KASSERT(ri >= 0 && ri < core_iaf_npmc, 283 ("[core,%d] illegal row-index %d", __LINE__, ri)); 284 285 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 286 287 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 288 cpu)); 289 290 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 291 292 return (0); 293 } 294 295 static int 296 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 297 { 298 int error; 299 struct pmc_hw *phw; 300 char iaf_name[PMC_NAME_MAX]; 301 302 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 303 304 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 305 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 306 NULL)) != 0) 307 return (error); 308 309 pi->pm_class = PMC_CLASS_IAF; 310 311 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 312 pi->pm_enabled = TRUE; 313 *ppmc = phw->phw_pmc; 314 } else { 315 pi->pm_enabled = FALSE; 316 *ppmc = NULL; 317 } 318 319 return (0); 320 } 321 322 static int 323 iaf_get_config(int cpu, int ri, struct pmc **ppm) 324 { 325 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 326 327 return (0); 328 } 329 330 static int 331 iaf_get_msr(int ri, uint32_t *msr) 332 { 333 KASSERT(ri >= 0 && ri < core_iaf_npmc, 334 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 335 336 *msr = IAF_RI_TO_MSR(ri); 337 338 return (0); 339 } 340 341 static int 342 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 343 { 344 struct pmc *pm; 345 pmc_value_t tmp; 346 347 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 348 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 349 KASSERT(ri >= 0 && ri < core_iaf_npmc, 350 ("[core,%d] illegal row-index %d", __LINE__, ri)); 351 352 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 353 354 KASSERT(pm, 355 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 356 ri, ri + core_iaf_ri)); 357 358 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 359 360 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 361 *v = iaf_perfctr_value_to_reload_count(tmp); 362 else 363 *v = tmp; 364 365 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 366 IAF_RI_TO_MSR(ri), *v); 367 368 return (0); 369 } 370 371 static int 372 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 373 { 374 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 375 376 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 377 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 378 KASSERT(ri >= 0 && ri < core_iaf_npmc, 379 ("[core,%d] illegal row-index %d", __LINE__, ri)); 380 381 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 382 ("[core,%d] PHW pmc non-NULL", __LINE__)); 383 384 return (0); 385 } 386 387 static int 388 iaf_start_pmc(int cpu, int ri) 389 { 390 struct pmc *pm; 391 struct core_cpu *iafc; 392 uint64_t msr = 0; 393 394 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 395 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 396 KASSERT(ri >= 0 && ri < core_iaf_npmc, 397 ("[core,%d] illegal row-index %d", __LINE__, ri)); 398 399 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 400 401 iafc = core_pcpu[cpu]; 402 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 403 404 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 405 406 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 407 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 408 409 do { 410 iafc->pc_resync = 0; 411 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 412 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 413 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 414 IAF_GLOBAL_CTRL_MASK)); 415 } while (iafc->pc_resync != 0); 416 417 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 418 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 419 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 420 421 return (0); 422 } 423 424 static int 425 iaf_stop_pmc(int cpu, int ri) 426 { 427 uint32_t fc; 428 struct core_cpu *iafc; 429 uint64_t msr = 0; 430 431 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 432 433 iafc = core_pcpu[cpu]; 434 435 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 436 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 437 KASSERT(ri >= 0 && ri < core_iaf_npmc, 438 ("[core,%d] illegal row-index %d", __LINE__, ri)); 439 440 fc = (IAF_MASK << (ri * 4)); 441 442 if (core_cputype != PMC_CPU_INTEL_ATOM && 443 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 444 fc &= ~IAF_ANY; 445 446 iafc->pc_iafctrl &= ~fc; 447 448 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 449 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 450 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 451 452 do { 453 iafc->pc_resync = 0; 454 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 455 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 456 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 457 IAF_GLOBAL_CTRL_MASK)); 458 } while (iafc->pc_resync != 0); 459 460 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 461 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 462 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 463 464 return (0); 465 } 466 467 static int 468 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 469 { 470 struct core_cpu *cc; 471 struct pmc *pm; 472 uint64_t msr; 473 474 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 475 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 476 KASSERT(ri >= 0 && ri < core_iaf_npmc, 477 ("[core,%d] illegal row-index %d", __LINE__, ri)); 478 479 cc = core_pcpu[cpu]; 480 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 481 482 KASSERT(pm, 483 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 484 485 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 486 v = iaf_reload_count_to_perfctr_value(v); 487 488 /* Turn off fixed counters */ 489 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 490 wrmsr(IAF_CTRL, msr); 491 492 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 493 494 /* Turn on fixed counters */ 495 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 496 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 497 498 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 499 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 500 (uintmax_t) rdmsr(IAF_CTRL), 501 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 502 503 return (0); 504 } 505 506 507 static void 508 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 509 { 510 struct pmc_classdep *pcd; 511 512 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 513 514 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 515 516 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 517 518 pcd->pcd_caps = IAF_PMC_CAPS; 519 pcd->pcd_class = PMC_CLASS_IAF; 520 pcd->pcd_num = npmc; 521 pcd->pcd_ri = md->pmd_npmc; 522 pcd->pcd_width = pmcwidth; 523 524 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 525 pcd->pcd_config_pmc = iaf_config_pmc; 526 pcd->pcd_describe = iaf_describe; 527 pcd->pcd_get_config = iaf_get_config; 528 pcd->pcd_get_msr = iaf_get_msr; 529 pcd->pcd_pcpu_fini = core_pcpu_noop; 530 pcd->pcd_pcpu_init = core_pcpu_noop; 531 pcd->pcd_read_pmc = iaf_read_pmc; 532 pcd->pcd_release_pmc = iaf_release_pmc; 533 pcd->pcd_start_pmc = iaf_start_pmc; 534 pcd->pcd_stop_pmc = iaf_stop_pmc; 535 pcd->pcd_write_pmc = iaf_write_pmc; 536 537 md->pmd_npmc += npmc; 538 } 539 540 /* 541 * Intel programmable PMCs. 542 */ 543 544 /* 545 * Event descriptor tables. 546 * 547 * For each event id, we track: 548 * 549 * 1. The CPUs that the event is valid for. 550 * 551 * 2. If the event uses a fixed UMASK, the value of the umask field. 552 * If the event doesn't use a fixed UMASK, a mask of legal bits 553 * to check against. 554 */ 555 556 struct iap_event_descr { 557 enum pmc_event iap_ev; 558 unsigned char iap_evcode; 559 unsigned char iap_umask; 560 unsigned int iap_flags; 561 }; 562 563 #define IAP_F_CC (1 << 0) /* CPU: Core */ 564 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 565 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 566 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 567 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 568 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 569 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 570 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 571 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 572 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 573 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ 574 #define IAP_F_HW (1 << 10) /* CPU: Haswell */ 575 #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ 576 #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ 577 #define IAP_F_FM (1 << 13) /* Fixed mask */ 578 579 #define IAP_F_ALLCPUSCORE2 \ 580 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 581 582 /* Sub fields of UMASK that this event supports. */ 583 #define IAP_M_CORE (1 << 0) /* Core specificity */ 584 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 585 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 586 #define IAP_M_MESI (1 << 3) /* MESI */ 587 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 588 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 589 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 590 591 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 592 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 593 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 594 #define IAP_F_MESI (0xF << 8) /* MESI */ 595 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 596 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 597 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 598 599 #define IAP_PREFETCH_RESERVED (0x2 << 12) 600 #define IAP_CORE_THIS (0x1 << 14) 601 #define IAP_CORE_ALL (0x3 << 14) 602 #define IAP_F_CMASK 0xFF000000 603 604 static struct iap_event_descr iap_events[] = { 605 #undef IAPDESCR 606 #define IAPDESCR(N,EV,UM,FLAGS) { \ 607 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 608 .iap_evcode = (EV), \ 609 .iap_umask = (UM), \ 610 .iap_flags = (FLAGS) \ 611 } 612 613 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 614 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 615 616 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 617 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 618 IAP_F_SBX | IAP_F_CAS), 619 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 620 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 621 IAP_F_CAS | IAP_F_HWX), 622 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 623 IAP_F_CAS), 624 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 625 IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 626 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 627 IAP_F_SBX | IAP_F_CAS), 628 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 629 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_CAS), 630 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_CAS), 631 632 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), 633 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 634 IAP_F_CAS), 635 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 636 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_CAS), 637 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 638 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 639 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_CAS), 640 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_CAS), 641 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_CAS), 642 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_CAS), 643 644 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 645 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 646 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 647 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | 648 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 649 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), 650 651 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 652 IAP_F_CC2E | IAP_F_CA), 653 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 654 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 655 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 656 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 657 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 658 659 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 660 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 661 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 662 IAP_F_HW | IAP_F_HWX), 663 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 664 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 665 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 666 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 667 IAP_F_SBX), 668 669 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 670 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 671 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 672 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 673 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 674 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 675 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 676 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 677 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 678 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 679 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 680 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 681 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 682 IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 683 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 684 IAP_F_HWX), 685 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 686 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 687 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 688 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 689 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 690 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 691 IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_IB | IAP_F_IBX), 692 693 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 694 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 695 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 696 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 697 698 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 699 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 700 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 701 702 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 703 IAP_F_WM), 704 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 705 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 706 707 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | 708 IAP_F_IB | IAP_F_IBX | IAP_F_HWX), 709 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 710 711 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 712 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 713 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 714 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 715 IAP_F_HWX), 716 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 717 IAP_F_HWX), 718 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 719 IAP_F_HWX), 720 721 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 722 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 723 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 724 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 725 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 726 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 727 728 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 729 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 730 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ), 731 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 732 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 733 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 734 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 735 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 736 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 737 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 738 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 739 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 740 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 741 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 742 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 743 744 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 745 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 746 IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 747 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), 748 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 749 750 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 751 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 752 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 753 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 754 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 755 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 756 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 757 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 758 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 759 760 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 761 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 762 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 763 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 764 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 765 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 766 767 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 768 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 769 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 770 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 771 772 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 773 IAP_F_SBX), 774 775 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 776 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 777 778 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 779 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 780 IAP_F_I7 | IAP_F_WM), 781 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 782 783 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 784 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 785 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 786 787 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 788 789 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 790 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 791 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 792 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 793 794 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 795 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 796 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 797 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 798 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 799 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 800 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 801 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 802 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 803 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 804 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 805 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 806 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 807 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 808 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 809 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 810 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 811 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 812 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 813 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 814 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 815 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 816 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 817 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 818 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 819 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 820 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 821 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 822 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 823 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 824 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 825 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 826 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 827 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 828 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 829 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 830 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 831 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 832 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 833 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | 834 IAP_F_HWX), 835 836 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 837 838 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 839 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 840 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 841 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 842 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 843 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 844 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 845 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 846 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 847 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 848 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 849 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 850 851 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 852 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 853 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 854 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 855 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 856 IAP_F_SBX), 857 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 858 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 859 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 860 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 861 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 862 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 863 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 864 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 865 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 866 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 867 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 868 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 869 870 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 871 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 872 IAP_F_SBX | IAP_F_IBX), 873 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 874 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 875 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 876 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 877 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 878 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 879 IAP_F_SBX | IAP_F_IBX), 880 881 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 882 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 883 IAP_F_CA | IAP_F_CC2), 884 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 885 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 886 887 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 888 IAP_F_ALLCPUSCORE2), 889 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 890 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 891 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 892 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 893 IAP_F_CAS | IAP_F_HWX), 894 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 895 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 896 IAP_F_CAS | IAP_F_HWX), 897 898 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 899 IAP_F_ALLCPUSCORE2), 900 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_CAS), 901 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_CAS), 902 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 903 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 904 905 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 906 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 907 908 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 909 910 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 911 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 912 IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 913 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 914 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 915 IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 916 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 917 918 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 919 920 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 921 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 922 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 923 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 924 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 925 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 926 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 927 928 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 929 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 930 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 931 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 932 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 933 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 934 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 935 936 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 937 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 938 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 939 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 940 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 941 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 942 943 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 944 IAP_F_I7), 945 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 946 IAP_F_CC2 | IAP_F_I7), 947 948 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 949 950 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 951 952 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 953 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 954 955 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 956 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 957 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 958 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 959 960 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 961 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 962 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 963 IAP_F_HW | IAP_F_HWX), 964 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 965 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 966 IAP_F_HW | IAP_F_HWX), 967 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 968 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 969 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 970 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 971 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 972 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), 973 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 974 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 975 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | 976 IAP_F_HWX), 977 978 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 979 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 980 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 981 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 982 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 983 984 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 985 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 986 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 987 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 988 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 989 990 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 991 992 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 993 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 994 IAP_F_SB | IAP_F_SBX), 995 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 996 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 997 998 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 999 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 1000 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 1001 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 1002 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 1003 1004 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1005 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1006 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1007 IAP_F_SB | IAP_F_SBX), 1008 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1009 IAP_F_SB | IAP_F_SBX), 1010 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1011 IAP_F_SB | IAP_F_SBX), 1012 1013 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1014 1015 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1016 1017 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1018 IAP_F_HWX), 1019 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1020 IAP_F_HWX), 1021 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1022 IAP_F_HWX), 1023 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1024 IAP_F_HWX), 1025 1026 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1027 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1028 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1029 1030 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1031 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1032 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1033 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1034 1035 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1036 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1037 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1038 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1039 1040 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1041 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1042 1043 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */ 1044 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX | IAP_F_IB), 1045 1046 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1047 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1048 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1049 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1050 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1051 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1052 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1053 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1054 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1055 1056 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1057 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1058 1059 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1060 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1061 1062 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1063 IAP_F_CA | IAP_F_CC2), 1064 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1065 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1066 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1067 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1068 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1069 1070 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1071 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1072 1073 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1074 IAP_F_CA | IAP_F_CC2), 1075 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1076 1077 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1078 1079 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1080 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1081 1082 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1083 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1084 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1085 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1086 1087 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1088 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1089 1090 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1091 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1092 1093 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1094 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1095 1096 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1097 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1098 1099 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1100 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1101 1102 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1103 IAP_F_CA | IAP_F_CC2), 1104 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1105 1106 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1107 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1108 1109 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1110 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1111 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1112 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1113 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1114 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1115 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1116 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1117 1118 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1119 1120 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1121 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1122 1123 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1124 1125 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1126 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1127 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1128 IAP_F_HWX), 1129 1130 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1131 1132 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1133 1134 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1135 1136 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1137 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1138 1139 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1140 1141 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1142 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1143 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1144 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1145 IAP_F_CAS | IAP_F_HWX), 1146 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1147 IAP_F_WM | IAP_F_CAS), 1148 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_IBX), 1149 1150 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1151 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1152 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1153 1154 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1155 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1156 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1157 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1158 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1159 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1160 1161 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1162 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1163 1164 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1165 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1166 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1167 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1168 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1169 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1170 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1171 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1172 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1173 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1174 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1175 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), 1176 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1177 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1178 1179 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1180 1181 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1182 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1183 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1184 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1185 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1186 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1187 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1188 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1189 1190 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1191 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1192 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1193 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1194 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1195 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1196 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1197 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1198 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1199 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1200 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1201 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1202 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1203 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1204 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1205 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1206 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1207 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1208 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1209 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1210 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1211 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1212 1213 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1214 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1215 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1216 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1217 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1218 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1219 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1220 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1221 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1222 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1223 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1224 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1225 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1226 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1227 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1228 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1229 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1230 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1231 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1232 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1233 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1234 1235 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1236 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1237 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1238 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1239 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1240 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1241 1242 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1243 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1244 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1245 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1246 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1247 1248 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1249 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1250 1251 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1252 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1253 1254 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1255 1256 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1257 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1258 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1259 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1260 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1261 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1262 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1263 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1264 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_IB | IAP_F_IBX), 1265 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1266 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1267 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ 1268 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1269 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1270 IAP_F_SBX | IAP_F_IBX), 1271 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1272 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1273 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1274 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1275 1276 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1277 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1278 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1279 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1280 IAP_F_SB | IAP_F_SBX), 1281 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1282 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1283 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1284 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1285 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1286 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1287 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1288 IAP_F_SB | IAP_F_SBX), 1289 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1290 IAP_F_SB | IAP_F_SBX), 1291 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1292 IAP_F_SB | IAP_F_SBX), 1293 1294 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), 1295 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), 1296 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB), 1297 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1298 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | IAP_F_HWX), 1299 IAPDESCR(A3H_0CH, 0xA3, 0x08, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1300 1301 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1302 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1303 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX | 1304 IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), 1305 1306 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1307 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1308 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1309 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1310 1311 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1312 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1313 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1314 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1315 1316 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1317 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1318 IAP_F_SBX | IAP_F_IBX), 1319 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1320 1321 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1322 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1323 1324 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1325 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1326 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1327 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1328 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1329 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1330 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1331 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1332 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1333 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1334 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1335 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1336 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1337 1338 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1339 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1340 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1341 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1342 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1343 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1344 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1345 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1346 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1347 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1348 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1349 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1350 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1351 IAP_F_WM), 1352 1353 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1354 IAP_F_SB | IAP_F_SBX), 1355 1356 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1357 IAP_F_WM | IAP_F_I7O), 1358 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1359 IAP_F_WM | IAP_F_I7O), 1360 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1361 IAP_F_WM | IAP_F_I7O), 1362 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1363 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1364 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1365 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1366 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1367 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1368 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1369 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1370 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1371 1372 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1373 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1374 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1375 1376 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1377 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_CAS), 1378 1379 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1380 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | 1381 IAP_F_HWX), 1382 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), 1383 1384 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1385 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1386 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1387 1388 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1389 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1390 1391 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1392 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1393 1394 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1395 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1396 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1397 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1398 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1399 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1400 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1401 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1402 1403 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1404 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1405 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1406 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1407 1408 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1409 1410 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1411 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1412 IAP_F_CAS | IAP_F_HWX), 1413 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1414 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1415 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1416 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1417 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1418 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1419 IAP_F_I7 | IAP_F_WM), 1420 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1421 1422 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1423 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1424 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1425 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1426 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1427 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1428 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1429 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1430 IAP_F_SBX | IAP_F_IBX), 1431 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1432 IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_IB | IAP_F_IBX), 1433 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1434 1435 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1436 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1437 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1438 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1439 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1440 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1441 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1442 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1443 IAP_F_I7 | IAP_F_WM), 1444 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1445 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1446 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1447 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), 1448 1449 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1450 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1451 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1452 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1453 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1454 IAP_F_CAS | IAP_F_HWX), 1455 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1456 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1457 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1458 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_CAS), 1459 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1460 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1461 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1462 1463 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1464 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1465 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1466 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1467 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1468 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1469 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1470 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1471 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1472 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1473 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1474 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1475 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1476 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1477 IAP_F_HWX), 1478 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1479 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1480 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1481 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1482 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1483 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1484 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1485 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1486 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_CAS), 1487 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_CAS), 1488 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_CAS), 1489 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_CAS), 1490 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_CAS), 1491 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_CAS), 1492 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_CAS), 1493 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_CAS), 1494 1495 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1496 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1497 IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1498 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1499 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1500 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1501 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1502 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1503 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1504 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1505 IAP_F_SBX | IAP_F_IBX), 1506 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1507 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1508 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_CAS), 1509 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_CAS), 1510 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_CAS), 1511 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_CAS), 1512 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_CAS), 1513 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_CAS), 1514 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_CAS), 1515 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_CAS), 1516 1517 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1518 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1519 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1520 1521 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1522 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1523 IAP_F_I7 | IAP_F_WM), 1524 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1525 IAP_F_I7 | IAP_F_WM), 1526 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1527 IAP_F_I7 | IAP_F_WM), 1528 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1529 IAP_F_I7 | IAP_F_WM), 1530 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1531 IAP_F_I7 | IAP_F_WM), 1532 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1533 1534 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1535 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1536 1537 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1538 1539 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1540 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 1541 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1542 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1543 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1544 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1545 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1546 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1547 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1548 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1549 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1550 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1551 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_CAS), 1552 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_CAS), 1553 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_CAS), 1554 1555 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1556 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1557 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1558 IAP_F_I7 | IAP_F_WM), 1559 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1560 IAP_F_I7 | IAP_F_WM), 1561 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1562 IAP_F_I7 | IAP_F_WM), 1563 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1564 IAP_F_WM), 1565 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_CAS), 1566 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1567 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1568 1569 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1570 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1571 IAP_F_I7 | IAP_F_WM), 1572 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1573 IAP_F_I7 | IAP_F_WM), 1574 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1575 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1576 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1577 1578 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1579 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1580 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), 1581 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1582 IAP_F_SBX | IAP_F_IBX), 1583 1584 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1585 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1586 1587 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ 1588 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1589 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1590 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1591 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1592 IAP_F_HWX), 1593 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1594 IAP_F_HWX), 1595 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1596 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1597 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1598 IAP_F_HWX), 1599 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1600 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1601 IAP_F_HWX), 1602 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1603 IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */ 1604 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1605 IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */ 1606 IAPDESCR(D0H_80H, 0xD0, 0x80, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | 1607 IAP_F_HWX), 1608 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1609 IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */ 1610 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1611 IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */ 1612 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1613 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1614 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1615 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1616 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1617 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1618 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1619 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1620 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX), 1621 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | 1622 IAP_F_HW | IAP_F_HWX), 1623 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1624 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1625 1626 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1627 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1628 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1629 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1630 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1631 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1632 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1633 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1634 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1635 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1636 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1637 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1638 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1639 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1640 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1641 1642 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1643 1644 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1645 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1646 IAPDESCR(D3H_03H, 0xD0, 0x3, IAP_F_IBX ), 1647 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), /* Not defined for IBX */ 1648 IAPDESCR(D3H_0CH, 0xD0, 0x0, IAP_F_IBX ), 1649 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX ), 1650 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX ), 1651 1652 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1653 IAP_F_I7 | IAP_F_WM), 1654 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1655 IAP_F_SB | IAP_F_SBX), 1656 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1657 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1658 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1659 1660 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1661 IAP_F_I7 | IAP_F_WM), 1662 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1663 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1664 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1665 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1666 1667 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1668 1669 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1670 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1671 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1672 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1673 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1674 1675 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1676 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1677 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1678 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1679 1680 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1681 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1682 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1683 1684 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1685 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1686 1687 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1688 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1689 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1690 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1691 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1692 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1693 1694 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1695 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1696 IAP_F_WM), 1697 1698 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1699 1700 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1701 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1702 1703 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1704 1705 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1706 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1707 IAP_F_WM | IAP_F_SBX | IAP_F_CAS), 1708 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1709 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_CAS), 1710 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_CAS), 1711 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB | 1712 IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1713 1714 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_CAS), 1715 1716 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1717 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1718 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1719 1720 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1721 1722 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1723 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1724 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1725 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1726 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1727 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1728 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1729 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1730 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1731 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1732 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1733 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1734 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1735 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1736 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1737 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1738 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1739 1740 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1741 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1742 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1743 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1744 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1745 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1746 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1747 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), 1748 1749 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1750 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1751 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1752 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1753 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1754 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1755 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1756 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX), 1757 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1758 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1759 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1760 IAP_F_IBX), 1761 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1762 1763 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1764 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1765 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1766 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1767 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1768 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1769 1770 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1771 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1772 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1773 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1774 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1775 IAP_F_SB | IAP_F_SBX), 1776 1777 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1778 1779 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1780 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1781 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1782 1783 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1784 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1785 1786 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1787 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1788 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1789 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1790 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1791 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1792 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1793 }; 1794 1795 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1796 1797 static pmc_value_t 1798 iap_perfctr_value_to_reload_count(pmc_value_t v) 1799 { 1800 v &= (1ULL << core_iap_width) - 1; 1801 return (1ULL << core_iap_width) - v; 1802 } 1803 1804 static pmc_value_t 1805 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1806 { 1807 return (1ULL << core_iap_width) - rlc; 1808 } 1809 1810 static int 1811 iap_pmc_has_overflowed(int ri) 1812 { 1813 uint64_t v; 1814 1815 /* 1816 * We treat a Core (i.e., Intel architecture v1) PMC as has 1817 * having overflowed if its MSB is zero. 1818 */ 1819 v = rdpmc(ri); 1820 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1821 } 1822 1823 /* 1824 * Check an event against the set of supported architectural events. 1825 * 1826 * If the event is not architectural EV_IS_NOTARCH is returned. 1827 * If the event is architectural and supported on this CPU, the correct 1828 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. 1829 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. 1830 */ 1831 1832 static int 1833 iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) 1834 { 1835 enum core_arch_events ae; 1836 1837 switch (pe) { 1838 case PMC_EV_IAP_ARCH_UNH_COR_CYC: 1839 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1840 *map = PMC_EV_IAP_EVENT_3CH_00H; 1841 break; 1842 case PMC_EV_IAP_ARCH_INS_RET: 1843 ae = CORE_AE_INSTRUCTION_RETIRED; 1844 *map = PMC_EV_IAP_EVENT_C0H_00H; 1845 break; 1846 case PMC_EV_IAP_ARCH_UNH_REF_CYC: 1847 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1848 *map = PMC_EV_IAP_EVENT_3CH_01H; 1849 break; 1850 case PMC_EV_IAP_ARCH_LLC_REF: 1851 ae = CORE_AE_LLC_REFERENCE; 1852 *map = PMC_EV_IAP_EVENT_2EH_4FH; 1853 break; 1854 case PMC_EV_IAP_ARCH_LLC_MIS: 1855 ae = CORE_AE_LLC_MISSES; 1856 *map = PMC_EV_IAP_EVENT_2EH_41H; 1857 break; 1858 case PMC_EV_IAP_ARCH_BR_INS_RET: 1859 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1860 *map = PMC_EV_IAP_EVENT_C4H_00H; 1861 break; 1862 case PMC_EV_IAP_ARCH_BR_MIS_RET: 1863 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1864 *map = PMC_EV_IAP_EVENT_C5H_00H; 1865 break; 1866 1867 default: /* Non architectural event. */ 1868 return (EV_IS_NOTARCH); 1869 } 1870 1871 return (((core_architectural_events & (1 << ae)) == 0) ? 1872 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); 1873 } 1874 1875 static int 1876 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1877 { 1878 uint32_t mask; 1879 1880 switch (pe) { 1881 /* 1882 * Events valid only on counter 0, 1. 1883 */ 1884 case PMC_EV_IAP_EVENT_40H_01H: 1885 case PMC_EV_IAP_EVENT_40H_02H: 1886 case PMC_EV_IAP_EVENT_40H_04H: 1887 case PMC_EV_IAP_EVENT_40H_08H: 1888 case PMC_EV_IAP_EVENT_40H_0FH: 1889 case PMC_EV_IAP_EVENT_41H_02H: 1890 case PMC_EV_IAP_EVENT_41H_04H: 1891 case PMC_EV_IAP_EVENT_41H_08H: 1892 case PMC_EV_IAP_EVENT_42H_01H: 1893 case PMC_EV_IAP_EVENT_42H_02H: 1894 case PMC_EV_IAP_EVENT_42H_04H: 1895 case PMC_EV_IAP_EVENT_42H_08H: 1896 case PMC_EV_IAP_EVENT_43H_01H: 1897 case PMC_EV_IAP_EVENT_43H_02H: 1898 case PMC_EV_IAP_EVENT_51H_01H: 1899 case PMC_EV_IAP_EVENT_51H_02H: 1900 case PMC_EV_IAP_EVENT_51H_04H: 1901 case PMC_EV_IAP_EVENT_51H_08H: 1902 case PMC_EV_IAP_EVENT_63H_01H: 1903 case PMC_EV_IAP_EVENT_63H_02H: 1904 mask = 0x3; 1905 break; 1906 1907 default: 1908 mask = ~0; /* Any row index is ok. */ 1909 } 1910 1911 return (mask & (1 << ri)); 1912 } 1913 1914 static int 1915 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1916 { 1917 uint32_t mask; 1918 1919 switch (pe) { 1920 /* 1921 * Events valid only on counter 0. 1922 */ 1923 case PMC_EV_IAP_EVENT_60H_01H: 1924 case PMC_EV_IAP_EVENT_60H_02H: 1925 case PMC_EV_IAP_EVENT_60H_04H: 1926 case PMC_EV_IAP_EVENT_60H_08H: 1927 case PMC_EV_IAP_EVENT_B3H_01H: 1928 case PMC_EV_IAP_EVENT_B3H_02H: 1929 case PMC_EV_IAP_EVENT_B3H_04H: 1930 mask = 0x1; 1931 break; 1932 1933 /* 1934 * Events valid only on counter 0, 1. 1935 */ 1936 case PMC_EV_IAP_EVENT_4CH_01H: 1937 case PMC_EV_IAP_EVENT_4EH_01H: 1938 case PMC_EV_IAP_EVENT_4EH_02H: 1939 case PMC_EV_IAP_EVENT_4EH_04H: 1940 case PMC_EV_IAP_EVENT_51H_01H: 1941 case PMC_EV_IAP_EVENT_51H_02H: 1942 case PMC_EV_IAP_EVENT_51H_04H: 1943 case PMC_EV_IAP_EVENT_51H_08H: 1944 case PMC_EV_IAP_EVENT_63H_01H: 1945 case PMC_EV_IAP_EVENT_63H_02H: 1946 mask = 0x3; 1947 break; 1948 1949 default: 1950 mask = ~0; /* Any row index is ok. */ 1951 } 1952 1953 return (mask & (1 << ri)); 1954 } 1955 1956 static int 1957 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 1958 { 1959 uint32_t mask; 1960 1961 switch (pe) { 1962 /* Events valid only on counter 0. */ 1963 case PMC_EV_IAP_EVENT_B7H_01H: 1964 mask = 0x1; 1965 break; 1966 /* Events valid only on counter 1. */ 1967 case PMC_EV_IAP_EVENT_C0H_01H: 1968 mask = 0x1; 1969 break; 1970 /* Events valid only on counter 2. */ 1971 case PMC_EV_IAP_EVENT_48H_01H: 1972 case PMC_EV_IAP_EVENT_A2H_02H: 1973 mask = 0x4; 1974 break; 1975 /* Events valid only on counter 3. */ 1976 case PMC_EV_IAP_EVENT_A3H_08H: 1977 case PMC_EV_IAP_EVENT_BBH_01H: 1978 case PMC_EV_IAP_EVENT_CDH_01H: 1979 case PMC_EV_IAP_EVENT_CDH_02H: 1980 mask = 0x8; 1981 break; 1982 default: 1983 mask = ~0; /* Any row index is ok. */ 1984 } 1985 1986 return (mask & (1 << ri)); 1987 } 1988 1989 static int 1990 iap_event_ok_on_counter(enum pmc_event pe, int ri) 1991 { 1992 uint32_t mask; 1993 1994 switch (pe) { 1995 /* 1996 * Events valid only on counter 0. 1997 */ 1998 case PMC_EV_IAP_EVENT_10H_00H: 1999 case PMC_EV_IAP_EVENT_14H_00H: 2000 case PMC_EV_IAP_EVENT_18H_00H: 2001 case PMC_EV_IAP_EVENT_B3H_01H: 2002 case PMC_EV_IAP_EVENT_B3H_02H: 2003 case PMC_EV_IAP_EVENT_B3H_04H: 2004 case PMC_EV_IAP_EVENT_C1H_00H: 2005 case PMC_EV_IAP_EVENT_CBH_01H: 2006 case PMC_EV_IAP_EVENT_CBH_02H: 2007 mask = (1 << 0); 2008 break; 2009 2010 /* 2011 * Events valid only on counter 1. 2012 */ 2013 case PMC_EV_IAP_EVENT_11H_00H: 2014 case PMC_EV_IAP_EVENT_12H_00H: 2015 case PMC_EV_IAP_EVENT_13H_00H: 2016 mask = (1 << 1); 2017 break; 2018 2019 default: 2020 mask = ~0; /* Any row index is ok. */ 2021 } 2022 2023 return (mask & (1 << ri)); 2024 } 2025 2026 static int 2027 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 2028 const struct pmc_op_pmcallocate *a) 2029 { 2030 int arch, n, model; 2031 enum pmc_event ev, map; 2032 struct iap_event_descr *ie; 2033 uint32_t c, caps, config, cpuflag, evsel, mask; 2034 2035 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2036 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2037 KASSERT(ri >= 0 && ri < core_iap_npmc, 2038 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 2039 2040 /* check requested capabilities */ 2041 caps = a->pm_caps; 2042 if ((IAP_PMC_CAPS & caps) != caps) 2043 return (EPERM); 2044 map = 0; /* XXX: silent GCC warning */ 2045 arch = iap_is_event_architectural(pm->pm_event, &map); 2046 if (arch == EV_IS_ARCH_NOTSUPP) 2047 return (EOPNOTSUPP); 2048 else if (arch == EV_IS_ARCH_SUPP) 2049 ev = map; 2050 else 2051 ev = pm->pm_event; 2052 2053 /* 2054 * A small number of events are not supported in all the 2055 * processors based on a given microarchitecture. 2056 */ 2057 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 2058 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 2059 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 2060 return (EINVAL); 2061 } 2062 2063 switch (core_cputype) { 2064 case PMC_CPU_INTEL_COREI7: 2065 case PMC_CPU_INTEL_NEHALEM_EX: 2066 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 2067 return (EINVAL); 2068 break; 2069 case PMC_CPU_INTEL_SANDYBRIDGE: 2070 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2071 case PMC_CPU_INTEL_IVYBRIDGE: 2072 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2073 case PMC_CPU_INTEL_HASWELL: 2074 case PMC_CPU_INTEL_HASWELL_XEON: 2075 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 2076 return (EINVAL); 2077 break; 2078 case PMC_CPU_INTEL_WESTMERE: 2079 case PMC_CPU_INTEL_WESTMERE_EX: 2080 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 2081 return (EINVAL); 2082 break; 2083 default: 2084 if (iap_event_ok_on_counter(ev, ri) == 0) 2085 return (EINVAL); 2086 } 2087 2088 /* 2089 * Look for an event descriptor with matching CPU and event id 2090 * fields. 2091 */ 2092 2093 switch (core_cputype) { 2094 default: 2095 case PMC_CPU_INTEL_ATOM: 2096 cpuflag = IAP_F_CA; 2097 break; 2098 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2099 cpuflag = IAP_F_CAS; 2100 break; 2101 case PMC_CPU_INTEL_CORE: 2102 cpuflag = IAP_F_CC; 2103 break; 2104 case PMC_CPU_INTEL_CORE2: 2105 cpuflag = IAP_F_CC2; 2106 break; 2107 case PMC_CPU_INTEL_CORE2EXTREME: 2108 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 2109 break; 2110 case PMC_CPU_INTEL_COREI7: 2111 cpuflag = IAP_F_I7; 2112 break; 2113 case PMC_CPU_INTEL_HASWELL: 2114 cpuflag = IAP_F_HW; 2115 break; 2116 case PMC_CPU_INTEL_HASWELL_XEON: 2117 cpuflag = IAP_F_HWX; 2118 break; 2119 case PMC_CPU_INTEL_IVYBRIDGE: 2120 cpuflag = IAP_F_IB; 2121 break; 2122 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2123 cpuflag = IAP_F_IBX; 2124 break; 2125 case PMC_CPU_INTEL_SANDYBRIDGE: 2126 cpuflag = IAP_F_SB; 2127 break; 2128 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2129 cpuflag = IAP_F_SBX; 2130 break; 2131 case PMC_CPU_INTEL_WESTMERE: 2132 cpuflag = IAP_F_WM; 2133 break; 2134 } 2135 2136 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 2137 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2138 break; 2139 2140 if (n == niap_events) 2141 return (EINVAL); 2142 2143 /* 2144 * A matching event descriptor has been found, so start 2145 * assembling the contents of the event select register. 2146 */ 2147 evsel = ie->iap_evcode; 2148 2149 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2150 2151 /* 2152 * If the event uses a fixed umask value, reject any umask 2153 * bits set by the user. 2154 */ 2155 if (ie->iap_flags & IAP_F_FM) { 2156 2157 if (IAP_UMASK(config) != 0) 2158 return (EINVAL); 2159 2160 evsel |= (ie->iap_umask << 8); 2161 2162 } else { 2163 2164 /* 2165 * Otherwise, the UMASK value needs to be taken from 2166 * the MD fields of the allocation request. Reject 2167 * requests that specify reserved bits. 2168 */ 2169 2170 mask = 0; 2171 2172 if (ie->iap_umask & IAP_M_CORE) { 2173 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2174 c != IAP_CORE_THIS) 2175 return (EINVAL); 2176 mask |= IAP_F_CORE; 2177 } 2178 2179 if (ie->iap_umask & IAP_M_AGENT) 2180 mask |= IAP_F_AGENT; 2181 2182 if (ie->iap_umask & IAP_M_PREFETCH) { 2183 2184 if ((c = (config & IAP_F_PREFETCH)) == 2185 IAP_PREFETCH_RESERVED) 2186 return (EINVAL); 2187 2188 mask |= IAP_F_PREFETCH; 2189 } 2190 2191 if (ie->iap_umask & IAP_M_MESI) 2192 mask |= IAP_F_MESI; 2193 2194 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2195 mask |= IAP_F_SNOOPRESPONSE; 2196 2197 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2198 mask |= IAP_F_SNOOPTYPE; 2199 2200 if (ie->iap_umask & IAP_M_TRANSITION) 2201 mask |= IAP_F_TRANSITION; 2202 2203 /* 2204 * If bits outside of the allowed set of umask bits 2205 * are set, reject the request. 2206 */ 2207 if (config & ~mask) 2208 return (EINVAL); 2209 2210 evsel |= (config & mask); 2211 2212 } 2213 2214 /* 2215 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2216 */ 2217 if (core_cputype == PMC_CPU_INTEL_ATOM || 2218 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 2219 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2220 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2221 evsel |= (config & IAP_ANY); 2222 else if (config & IAP_ANY) 2223 return (EINVAL); 2224 2225 /* 2226 * Check offcore response configuration. 2227 */ 2228 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2229 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2230 ev != PMC_EV_IAP_EVENT_BBH_01H) 2231 return (EINVAL); 2232 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2233 ev == PMC_EV_IAP_EVENT_BBH_01H) 2234 return (EINVAL); 2235 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2236 core_cputype == PMC_CPU_INTEL_WESTMERE || 2237 core_cputype == PMC_CPU_INTEL_NEHALEM_EX || 2238 core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && 2239 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2240 return (EINVAL); 2241 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2242 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2243 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2244 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2245 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2246 return (EINVAL); 2247 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2248 } 2249 2250 if (caps & PMC_CAP_THRESHOLD) 2251 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2252 if (caps & PMC_CAP_USER) 2253 evsel |= IAP_USR; 2254 if (caps & PMC_CAP_SYSTEM) 2255 evsel |= IAP_OS; 2256 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2257 evsel |= (IAP_OS | IAP_USR); 2258 if (caps & PMC_CAP_EDGE) 2259 evsel |= IAP_EDGE; 2260 if (caps & PMC_CAP_INVERT) 2261 evsel |= IAP_INV; 2262 if (caps & PMC_CAP_INTERRUPT) 2263 evsel |= IAP_INT; 2264 2265 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2266 2267 return (0); 2268 } 2269 2270 static int 2271 iap_config_pmc(int cpu, int ri, struct pmc *pm) 2272 { 2273 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2274 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2275 2276 KASSERT(ri >= 0 && ri < core_iap_npmc, 2277 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2278 2279 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2280 2281 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2282 cpu)); 2283 2284 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2285 2286 return (0); 2287 } 2288 2289 static int 2290 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2291 { 2292 int error; 2293 struct pmc_hw *phw; 2294 char iap_name[PMC_NAME_MAX]; 2295 2296 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2297 2298 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2299 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2300 NULL)) != 0) 2301 return (error); 2302 2303 pi->pm_class = PMC_CLASS_IAP; 2304 2305 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2306 pi->pm_enabled = TRUE; 2307 *ppmc = phw->phw_pmc; 2308 } else { 2309 pi->pm_enabled = FALSE; 2310 *ppmc = NULL; 2311 } 2312 2313 return (0); 2314 } 2315 2316 static int 2317 iap_get_config(int cpu, int ri, struct pmc **ppm) 2318 { 2319 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2320 2321 return (0); 2322 } 2323 2324 static int 2325 iap_get_msr(int ri, uint32_t *msr) 2326 { 2327 KASSERT(ri >= 0 && ri < core_iap_npmc, 2328 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2329 2330 *msr = ri; 2331 2332 return (0); 2333 } 2334 2335 static int 2336 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2337 { 2338 struct pmc *pm; 2339 pmc_value_t tmp; 2340 2341 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2342 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2343 KASSERT(ri >= 0 && ri < core_iap_npmc, 2344 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2345 2346 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2347 2348 KASSERT(pm, 2349 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2350 ri)); 2351 2352 tmp = rdpmc(ri); 2353 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2354 *v = iap_perfctr_value_to_reload_count(tmp); 2355 else 2356 *v = tmp & ((1ULL << core_iap_width) - 1); 2357 2358 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2359 ri, *v); 2360 2361 return (0); 2362 } 2363 2364 static int 2365 iap_release_pmc(int cpu, int ri, struct pmc *pm) 2366 { 2367 (void) pm; 2368 2369 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2370 pm); 2371 2372 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2373 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2374 KASSERT(ri >= 0 && ri < core_iap_npmc, 2375 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2376 2377 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2378 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2379 2380 return (0); 2381 } 2382 2383 static int 2384 iap_start_pmc(int cpu, int ri) 2385 { 2386 struct pmc *pm; 2387 uint32_t evsel; 2388 struct core_cpu *cc; 2389 2390 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2391 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2392 KASSERT(ri >= 0 && ri < core_iap_npmc, 2393 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2394 2395 cc = core_pcpu[cpu]; 2396 pm = cc->pc_corepmcs[ri].phw_pmc; 2397 2398 KASSERT(pm, 2399 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2400 __LINE__, cpu, ri)); 2401 2402 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2403 2404 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2405 2406 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2407 cpu, ri, IAP_EVSEL0 + ri, evsel); 2408 2409 /* Event specific configuration. */ 2410 switch (pm->pm_event) { 2411 case PMC_EV_IAP_EVENT_B7H_01H: 2412 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2413 break; 2414 case PMC_EV_IAP_EVENT_BBH_01H: 2415 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2416 break; 2417 default: 2418 break; 2419 } 2420 2421 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2422 2423 if (core_cputype == PMC_CPU_INTEL_CORE) 2424 return (0); 2425 2426 do { 2427 cc->pc_resync = 0; 2428 cc->pc_globalctrl |= (1ULL << ri); 2429 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2430 } while (cc->pc_resync != 0); 2431 2432 return (0); 2433 } 2434 2435 static int 2436 iap_stop_pmc(int cpu, int ri) 2437 { 2438 struct pmc *pm; 2439 struct core_cpu *cc; 2440 uint64_t msr; 2441 2442 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2443 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2444 KASSERT(ri >= 0 && ri < core_iap_npmc, 2445 ("[core,%d] illegal row index %d", __LINE__, ri)); 2446 2447 cc = core_pcpu[cpu]; 2448 pm = cc->pc_corepmcs[ri].phw_pmc; 2449 2450 KASSERT(pm, 2451 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2452 cpu, ri)); 2453 2454 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2455 2456 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2457 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2458 2459 if (core_cputype == PMC_CPU_INTEL_CORE) 2460 return (0); 2461 2462 msr = 0; 2463 do { 2464 cc->pc_resync = 0; 2465 cc->pc_globalctrl &= ~(1ULL << ri); 2466 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2467 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2468 } while (cc->pc_resync != 0); 2469 2470 return (0); 2471 } 2472 2473 static int 2474 iap_write_pmc(int cpu, int ri, pmc_value_t v) 2475 { 2476 struct pmc *pm; 2477 struct core_cpu *cc; 2478 2479 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2480 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2481 KASSERT(ri >= 0 && ri < core_iap_npmc, 2482 ("[core,%d] illegal row index %d", __LINE__, ri)); 2483 2484 cc = core_pcpu[cpu]; 2485 pm = cc->pc_corepmcs[ri].phw_pmc; 2486 2487 KASSERT(pm, 2488 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2489 cpu, ri)); 2490 2491 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2492 IAP_PMC0 + ri, v); 2493 2494 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2495 v = iap_reload_count_to_perfctr_value(v); 2496 2497 /* 2498 * Write the new value to the counter. The counter will be in 2499 * a stopped state when the pcd_write() entry point is called. 2500 */ 2501 2502 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2503 2504 return (0); 2505 } 2506 2507 2508 static void 2509 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2510 int flags) 2511 { 2512 struct pmc_classdep *pcd; 2513 2514 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2515 2516 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 2517 2518 /* Remember the set of architectural events supported. */ 2519 core_architectural_events = ~flags; 2520 2521 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2522 2523 pcd->pcd_caps = IAP_PMC_CAPS; 2524 pcd->pcd_class = PMC_CLASS_IAP; 2525 pcd->pcd_num = npmc; 2526 pcd->pcd_ri = md->pmd_npmc; 2527 pcd->pcd_width = pmcwidth; 2528 2529 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2530 pcd->pcd_config_pmc = iap_config_pmc; 2531 pcd->pcd_describe = iap_describe; 2532 pcd->pcd_get_config = iap_get_config; 2533 pcd->pcd_get_msr = iap_get_msr; 2534 pcd->pcd_pcpu_fini = core_pcpu_fini; 2535 pcd->pcd_pcpu_init = core_pcpu_init; 2536 pcd->pcd_read_pmc = iap_read_pmc; 2537 pcd->pcd_release_pmc = iap_release_pmc; 2538 pcd->pcd_start_pmc = iap_start_pmc; 2539 pcd->pcd_stop_pmc = iap_stop_pmc; 2540 pcd->pcd_write_pmc = iap_write_pmc; 2541 2542 md->pmd_npmc += npmc; 2543 } 2544 2545 static int 2546 core_intr(int cpu, struct trapframe *tf) 2547 { 2548 pmc_value_t v; 2549 struct pmc *pm; 2550 struct core_cpu *cc; 2551 int error, found_interrupt, ri; 2552 uint64_t msr; 2553 2554 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2555 TRAPF_USERMODE(tf)); 2556 2557 found_interrupt = 0; 2558 cc = core_pcpu[cpu]; 2559 2560 for (ri = 0; ri < core_iap_npmc; ri++) { 2561 2562 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2563 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2564 continue; 2565 2566 if (!iap_pmc_has_overflowed(ri)) 2567 continue; 2568 2569 found_interrupt = 1; 2570 2571 if (pm->pm_state != PMC_STATE_RUNNING) 2572 continue; 2573 2574 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2575 TRAPF_USERMODE(tf)); 2576 2577 v = pm->pm_sc.pm_reloadcount; 2578 v = iaf_reload_count_to_perfctr_value(v); 2579 2580 /* 2581 * Stop the counter, reload it but only restart it if 2582 * the PMC is not stalled. 2583 */ 2584 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2585 wrmsr(IAP_EVSEL0 + ri, msr); 2586 wrmsr(IAP_PMC0 + ri, v); 2587 2588 if (error) 2589 continue; 2590 2591 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2592 IAP_EN)); 2593 } 2594 2595 if (found_interrupt) 2596 lapic_reenable_pmc(); 2597 2598 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2599 &pmc_stats.pm_intr_ignored, 1); 2600 2601 return (found_interrupt); 2602 } 2603 2604 static int 2605 core2_intr(int cpu, struct trapframe *tf) 2606 { 2607 int error, found_interrupt, n; 2608 uint64_t flag, intrstatus, intrenable, msr; 2609 struct pmc *pm; 2610 struct core_cpu *cc; 2611 pmc_value_t v; 2612 2613 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2614 TRAPF_USERMODE(tf)); 2615 2616 /* 2617 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2618 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2619 * the current set of interrupting PMCs and process these 2620 * after stopping them. 2621 */ 2622 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2623 intrenable = intrstatus & core_pmcmask; 2624 2625 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2626 (uintmax_t) intrstatus); 2627 2628 found_interrupt = 0; 2629 cc = core_pcpu[cpu]; 2630 2631 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2632 2633 cc->pc_globalctrl &= ~intrenable; 2634 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2635 2636 /* 2637 * Stop PMCs and clear overflow status bits. 2638 */ 2639 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2640 wrmsr(IA_GLOBAL_CTRL, msr); 2641 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2642 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2643 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2644 2645 /* 2646 * Look for interrupts from fixed function PMCs. 2647 */ 2648 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2649 n++, flag <<= 1) { 2650 2651 if ((intrstatus & flag) == 0) 2652 continue; 2653 2654 found_interrupt = 1; 2655 2656 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2657 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2658 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2659 continue; 2660 2661 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2662 TRAPF_USERMODE(tf)); 2663 if (error) 2664 intrenable &= ~flag; 2665 2666 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2667 2668 /* Reload sampling count. */ 2669 wrmsr(IAF_CTR0 + n, v); 2670 2671 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 2672 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2673 } 2674 2675 /* 2676 * Process interrupts from the programmable counters. 2677 */ 2678 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2679 if ((intrstatus & flag) == 0) 2680 continue; 2681 2682 found_interrupt = 1; 2683 2684 pm = cc->pc_corepmcs[n].phw_pmc; 2685 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2686 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2687 continue; 2688 2689 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2690 TRAPF_USERMODE(tf)); 2691 if (error) 2692 intrenable &= ~flag; 2693 2694 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2695 2696 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2697 (uintmax_t) v); 2698 2699 /* Reload sampling count. */ 2700 wrmsr(IAP_PMC0 + n, v); 2701 } 2702 2703 /* 2704 * Reenable all non-stalled PMCs. 2705 */ 2706 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2707 (uintmax_t) intrenable); 2708 2709 cc->pc_globalctrl |= intrenable; 2710 2711 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2712 2713 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2714 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2715 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2716 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2717 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2718 2719 if (found_interrupt) 2720 lapic_reenable_pmc(); 2721 2722 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2723 &pmc_stats.pm_intr_ignored, 1); 2724 2725 return (found_interrupt); 2726 } 2727 2728 int 2729 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 2730 { 2731 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2732 int ipa_version, flags, nflags; 2733 2734 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2735 2736 ipa_version = (version_override > 0) ? version_override : 2737 cpuid[CORE_CPUID_EAX] & 0xFF; 2738 core_cputype = md->pmd_cputype; 2739 2740 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2741 core_cputype, maxcpu, ipa_version); 2742 2743 if (ipa_version < 1 || ipa_version > 3 || 2744 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 2745 /* Unknown PMC architecture. */ 2746 printf("hwpc_core: unknown PMC architecture: %d\n", 2747 ipa_version); 2748 return (EPROGMISMATCH); 2749 } 2750 2751 core_pmcmask = 0; 2752 2753 /* 2754 * Initialize programmable counters. 2755 */ 2756 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2757 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2758 2759 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2760 2761 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2762 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2763 2764 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2765 2766 /* 2767 * Initialize fixed function counters, if present. 2768 */ 2769 if (core_cputype != PMC_CPU_INTEL_CORE) { 2770 core_iaf_ri = core_iap_npmc; 2771 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2772 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2773 2774 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2775 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2776 } 2777 2778 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2779 core_iaf_ri); 2780 2781 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 2782 M_ZERO | M_WAITOK); 2783 2784 /* 2785 * Choose the appropriate interrupt handler. 2786 */ 2787 if (ipa_version == 1) 2788 md->pmd_intr = core_intr; 2789 else 2790 md->pmd_intr = core2_intr; 2791 2792 md->pmd_pcpu_fini = NULL; 2793 md->pmd_pcpu_init = NULL; 2794 2795 return (0); 2796 } 2797 2798 void 2799 pmc_core_finalize(struct pmc_mdep *md) 2800 { 2801 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2802 2803 free(core_pcpu, M_PMC); 2804 core_pcpu = NULL; 2805 } 2806