1 /*- 2 * Copyright (c) 2008 Joseph Koshy 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Intel Core PMCs. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 #include <sys/systm.h> 39 40 #include <machine/intr_machdep.h> 41 #include <x86/apicvar.h> 42 #include <machine/cpu.h> 43 #include <machine/cpufunc.h> 44 #include <machine/md_var.h> 45 #include <machine/specialreg.h> 46 47 #define CORE_CPUID_REQUEST 0xA 48 #define CORE_CPUID_REQUEST_SIZE 0x4 49 #define CORE_CPUID_EAX 0x0 50 #define CORE_CPUID_EBX 0x1 51 #define CORE_CPUID_ECX 0x2 52 #define CORE_CPUID_EDX 0x3 53 54 #define IAF_PMC_CAPS \ 55 (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ 56 PMC_CAP_USER | PMC_CAP_SYSTEM) 57 #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) 58 59 #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ 60 PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ 61 PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) 62 63 #define EV_IS_NOTARCH 0 64 #define EV_IS_ARCH_SUPP 1 65 #define EV_IS_ARCH_NOTSUPP -1 66 67 /* 68 * "Architectural" events defined by Intel. The values of these 69 * symbols correspond to positions in the bitmask returned by 70 * the CPUID.0AH instruction. 71 */ 72 enum core_arch_events { 73 CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, 74 CORE_AE_BRANCH_MISSES_RETIRED = 6, 75 CORE_AE_INSTRUCTION_RETIRED = 1, 76 CORE_AE_LLC_MISSES = 4, 77 CORE_AE_LLC_REFERENCE = 3, 78 CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, 79 CORE_AE_UNHALTED_CORE_CYCLES = 0 80 }; 81 82 static enum pmc_cputype core_cputype; 83 84 struct core_cpu { 85 volatile uint32_t pc_resync; 86 volatile uint32_t pc_iafctrl; /* Fixed function control. */ 87 volatile uint64_t pc_globalctrl; /* Global control register. */ 88 struct pmc_hw pc_corepmcs[]; 89 }; 90 91 static struct core_cpu **core_pcpu; 92 93 static uint32_t core_architectural_events; 94 static uint64_t core_pmcmask; 95 96 static int core_iaf_ri; /* relative index of fixed counters */ 97 static int core_iaf_width; 98 static int core_iaf_npmc; 99 100 static int core_iap_width; 101 static int core_iap_npmc; 102 103 static int 104 core_pcpu_noop(struct pmc_mdep *md, int cpu) 105 { 106 (void) md; 107 (void) cpu; 108 return (0); 109 } 110 111 static int 112 core_pcpu_init(struct pmc_mdep *md, int cpu) 113 { 114 struct pmc_cpu *pc; 115 struct core_cpu *cc; 116 struct pmc_hw *phw; 117 int core_ri, n, npmc; 118 119 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 120 ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); 121 122 PMCDBG(MDP,INI,1,"core-init cpu=%d", cpu); 123 124 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 125 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 126 127 if (core_cputype != PMC_CPU_INTEL_CORE) 128 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 129 130 cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), 131 M_PMC, M_WAITOK | M_ZERO); 132 133 core_pcpu[cpu] = cc; 134 pc = pmc_pcpu[cpu]; 135 136 KASSERT(pc != NULL && cc != NULL, 137 ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); 138 139 for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { 140 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 141 PMC_PHW_CPU_TO_STATE(cpu) | 142 PMC_PHW_INDEX_TO_STATE(n + core_ri); 143 phw->phw_pmc = NULL; 144 pc->pc_hwpmcs[n + core_ri] = phw; 145 } 146 147 return (0); 148 } 149 150 static int 151 core_pcpu_fini(struct pmc_mdep *md, int cpu) 152 { 153 int core_ri, n, npmc; 154 struct pmc_cpu *pc; 155 struct core_cpu *cc; 156 uint64_t msr = 0; 157 158 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 159 ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); 160 161 PMCDBG(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); 162 163 if ((cc = core_pcpu[cpu]) == NULL) 164 return (0); 165 166 core_pcpu[cpu] = NULL; 167 168 pc = pmc_pcpu[cpu]; 169 170 KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, 171 cpu)); 172 173 npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; 174 core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; 175 176 for (n = 0; n < npmc; n++) { 177 msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; 178 wrmsr(IAP_EVSEL0 + n, msr); 179 } 180 181 if (core_cputype != PMC_CPU_INTEL_CORE) { 182 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 183 wrmsr(IAF_CTRL, msr); 184 npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; 185 } 186 187 for (n = 0; n < npmc; n++) 188 pc->pc_hwpmcs[n + core_ri] = NULL; 189 190 free(cc, M_PMC); 191 192 return (0); 193 } 194 195 /* 196 * Fixed function counters. 197 */ 198 199 static pmc_value_t 200 iaf_perfctr_value_to_reload_count(pmc_value_t v) 201 { 202 v &= (1ULL << core_iaf_width) - 1; 203 return (1ULL << core_iaf_width) - v; 204 } 205 206 static pmc_value_t 207 iaf_reload_count_to_perfctr_value(pmc_value_t rlc) 208 { 209 return (1ULL << core_iaf_width) - rlc; 210 } 211 212 static int 213 iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, 214 const struct pmc_op_pmcallocate *a) 215 { 216 enum pmc_event ev; 217 uint32_t caps, flags, validflags; 218 219 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 220 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 221 222 PMCDBG(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); 223 224 if (ri < 0 || ri > core_iaf_npmc) 225 return (EINVAL); 226 227 caps = a->pm_caps; 228 229 if (a->pm_class != PMC_CLASS_IAF || 230 (caps & IAF_PMC_CAPS) != caps) 231 return (EINVAL); 232 233 ev = pm->pm_event; 234 if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) 235 return (EINVAL); 236 237 if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) 238 return (EINVAL); 239 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) 240 return (EINVAL); 241 if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) 242 return (EINVAL); 243 244 flags = a->pm_md.pm_iaf.pm_iaf_flags; 245 246 validflags = IAF_MASK; 247 248 if (core_cputype != PMC_CPU_INTEL_ATOM && 249 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 250 validflags &= ~IAF_ANY; 251 252 if ((flags & ~validflags) != 0) 253 return (EINVAL); 254 255 if (caps & PMC_CAP_INTERRUPT) 256 flags |= IAF_PMI; 257 if (caps & PMC_CAP_SYSTEM) 258 flags |= IAF_OS; 259 if (caps & PMC_CAP_USER) 260 flags |= IAF_USR; 261 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 262 flags |= (IAF_OS | IAF_USR); 263 264 pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); 265 266 PMCDBG(MDP,ALL,2, "iaf-allocate config=0x%jx", 267 (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); 268 269 return (0); 270 } 271 272 static int 273 iaf_config_pmc(int cpu, int ri, struct pmc *pm) 274 { 275 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 276 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 277 278 KASSERT(ri >= 0 && ri < core_iaf_npmc, 279 ("[core,%d] illegal row-index %d", __LINE__, ri)); 280 281 PMCDBG(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 282 283 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 284 cpu)); 285 286 core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; 287 288 return (0); 289 } 290 291 static int 292 iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 293 { 294 int error; 295 struct pmc_hw *phw; 296 char iaf_name[PMC_NAME_MAX]; 297 298 phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; 299 300 (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); 301 if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, 302 NULL)) != 0) 303 return (error); 304 305 pi->pm_class = PMC_CLASS_IAF; 306 307 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 308 pi->pm_enabled = TRUE; 309 *ppmc = phw->phw_pmc; 310 } else { 311 pi->pm_enabled = FALSE; 312 *ppmc = NULL; 313 } 314 315 return (0); 316 } 317 318 static int 319 iaf_get_config(int cpu, int ri, struct pmc **ppm) 320 { 321 *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 322 323 return (0); 324 } 325 326 static int 327 iaf_get_msr(int ri, uint32_t *msr) 328 { 329 KASSERT(ri >= 0 && ri < core_iaf_npmc, 330 ("[iaf,%d] ri %d out of range", __LINE__, ri)); 331 332 *msr = IAF_RI_TO_MSR(ri); 333 334 return (0); 335 } 336 337 static int 338 iaf_read_pmc(int cpu, int ri, pmc_value_t *v) 339 { 340 struct pmc *pm; 341 pmc_value_t tmp; 342 343 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 344 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 345 KASSERT(ri >= 0 && ri < core_iaf_npmc, 346 ("[core,%d] illegal row-index %d", __LINE__, ri)); 347 348 pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 349 350 KASSERT(pm, 351 ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, 352 ri, ri + core_iaf_ri)); 353 354 tmp = rdpmc(IAF_RI_TO_MSR(ri)); 355 356 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 357 *v = iaf_perfctr_value_to_reload_count(tmp); 358 else 359 *v = tmp; 360 361 PMCDBG(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 362 IAF_RI_TO_MSR(ri), *v); 363 364 return (0); 365 } 366 367 static int 368 iaf_release_pmc(int cpu, int ri, struct pmc *pmc) 369 { 370 PMCDBG(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); 371 372 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 373 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 374 KASSERT(ri >= 0 && ri < core_iaf_npmc, 375 ("[core,%d] illegal row-index %d", __LINE__, ri)); 376 377 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, 378 ("[core,%d] PHW pmc non-NULL", __LINE__)); 379 380 return (0); 381 } 382 383 static int 384 iaf_start_pmc(int cpu, int ri) 385 { 386 struct pmc *pm; 387 struct core_cpu *iafc; 388 uint64_t msr = 0; 389 390 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 391 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 392 KASSERT(ri >= 0 && ri < core_iaf_npmc, 393 ("[core,%d] illegal row-index %d", __LINE__, ri)); 394 395 PMCDBG(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); 396 397 iafc = core_pcpu[cpu]; 398 pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 399 400 iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; 401 402 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 403 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 404 405 do { 406 iafc->pc_resync = 0; 407 iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); 408 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 409 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 410 IAF_GLOBAL_CTRL_MASK)); 411 } while (iafc->pc_resync != 0); 412 413 PMCDBG(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 414 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 415 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 416 417 return (0); 418 } 419 420 static int 421 iaf_stop_pmc(int cpu, int ri) 422 { 423 uint32_t fc; 424 struct core_cpu *iafc; 425 uint64_t msr = 0; 426 427 PMCDBG(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); 428 429 iafc = core_pcpu[cpu]; 430 431 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 432 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 433 KASSERT(ri >= 0 && ri < core_iaf_npmc, 434 ("[core,%d] illegal row-index %d", __LINE__, ri)); 435 436 fc = (IAF_MASK << (ri * 4)); 437 438 if (core_cputype != PMC_CPU_INTEL_ATOM && 439 core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) 440 fc &= ~IAF_ANY; 441 442 iafc->pc_iafctrl &= ~fc; 443 444 PMCDBG(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); 445 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 446 wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); 447 448 do { 449 iafc->pc_resync = 0; 450 iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); 451 msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; 452 wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & 453 IAF_GLOBAL_CTRL_MASK)); 454 } while (iafc->pc_resync != 0); 455 456 PMCDBG(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", 457 iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), 458 iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); 459 460 return (0); 461 } 462 463 static int 464 iaf_write_pmc(int cpu, int ri, pmc_value_t v) 465 { 466 struct core_cpu *cc; 467 struct pmc *pm; 468 uint64_t msr; 469 470 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 471 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 472 KASSERT(ri >= 0 && ri < core_iaf_npmc, 473 ("[core,%d] illegal row-index %d", __LINE__, ri)); 474 475 cc = core_pcpu[cpu]; 476 pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; 477 478 KASSERT(pm, 479 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); 480 481 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 482 v = iaf_reload_count_to_perfctr_value(v); 483 484 /* Turn off fixed counters */ 485 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 486 wrmsr(IAF_CTRL, msr); 487 488 wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); 489 490 /* Turn on fixed counters */ 491 msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; 492 wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); 493 494 PMCDBG(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " 495 "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, 496 (uintmax_t) rdmsr(IAF_CTRL), 497 (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); 498 499 return (0); 500 } 501 502 503 static void 504 iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) 505 { 506 struct pmc_classdep *pcd; 507 508 KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); 509 510 PMCDBG(MDP,INI,1, "%s", "iaf-initialize"); 511 512 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; 513 514 pcd->pcd_caps = IAF_PMC_CAPS; 515 pcd->pcd_class = PMC_CLASS_IAF; 516 pcd->pcd_num = npmc; 517 pcd->pcd_ri = md->pmd_npmc; 518 pcd->pcd_width = pmcwidth; 519 520 pcd->pcd_allocate_pmc = iaf_allocate_pmc; 521 pcd->pcd_config_pmc = iaf_config_pmc; 522 pcd->pcd_describe = iaf_describe; 523 pcd->pcd_get_config = iaf_get_config; 524 pcd->pcd_get_msr = iaf_get_msr; 525 pcd->pcd_pcpu_fini = core_pcpu_noop; 526 pcd->pcd_pcpu_init = core_pcpu_noop; 527 pcd->pcd_read_pmc = iaf_read_pmc; 528 pcd->pcd_release_pmc = iaf_release_pmc; 529 pcd->pcd_start_pmc = iaf_start_pmc; 530 pcd->pcd_stop_pmc = iaf_stop_pmc; 531 pcd->pcd_write_pmc = iaf_write_pmc; 532 533 md->pmd_npmc += npmc; 534 } 535 536 /* 537 * Intel programmable PMCs. 538 */ 539 540 /* 541 * Event descriptor tables. 542 * 543 * For each event id, we track: 544 * 545 * 1. The CPUs that the event is valid for. 546 * 547 * 2. If the event uses a fixed UMASK, the value of the umask field. 548 * If the event doesn't use a fixed UMASK, a mask of legal bits 549 * to check against. 550 */ 551 552 struct iap_event_descr { 553 enum pmc_event iap_ev; 554 unsigned char iap_evcode; 555 unsigned char iap_umask; 556 unsigned int iap_flags; 557 }; 558 559 #define IAP_F_CC (1 << 0) /* CPU: Core */ 560 #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ 561 #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ 562 #define IAP_F_CA (1 << 3) /* CPU: Atom */ 563 #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ 564 #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ 565 #define IAP_F_WM (1 << 5) /* CPU: Westmere */ 566 #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ 567 #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ 568 #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ 569 #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ 570 #define IAP_F_HW (1 << 10) /* CPU: Haswell */ 571 #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ 572 #define IAP_F_FM (1 << 12) /* Fixed mask */ 573 574 #define IAP_F_ALLCPUSCORE2 \ 575 (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) 576 577 /* Sub fields of UMASK that this event supports. */ 578 #define IAP_M_CORE (1 << 0) /* Core specificity */ 579 #define IAP_M_AGENT (1 << 1) /* Agent specificity */ 580 #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ 581 #define IAP_M_MESI (1 << 3) /* MESI */ 582 #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ 583 #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ 584 #define IAP_M_TRANSITION (1 << 6) /* Transition */ 585 586 #define IAP_F_CORE (0x3 << 14) /* Core specificity */ 587 #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ 588 #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ 589 #define IAP_F_MESI (0xF << 8) /* MESI */ 590 #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ 591 #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ 592 #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ 593 594 #define IAP_PREFETCH_RESERVED (0x2 << 12) 595 #define IAP_CORE_THIS (0x1 << 14) 596 #define IAP_CORE_ALL (0x3 << 14) 597 #define IAP_F_CMASK 0xFF000000 598 599 static struct iap_event_descr iap_events[] = { 600 #undef IAPDESCR 601 #define IAPDESCR(N,EV,UM,FLAGS) { \ 602 .iap_ev = PMC_EV_IAP_EVENT_##N, \ 603 .iap_evcode = (EV), \ 604 .iap_umask = (UM), \ 605 .iap_flags = (FLAGS) \ 606 } 607 608 IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), 609 IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), 610 611 IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), 612 IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 613 IAP_F_SBX | IAP_F_CAS), 614 IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 615 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 616 IAP_F_CAS), 617 IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 618 IAP_F_CAS), 619 IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 620 IAP_F_SBX | IAP_F_CAS), 621 IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | 622 IAP_F_SBX | IAP_F_CAS), 623 IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 624 IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_CAS), 625 IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_CAS), 626 627 IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), 628 IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | 629 IAP_F_CAS), 630 IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 631 IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_CAS), 632 IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 633 IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 634 IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_CAS), 635 IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_CAS), 636 IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_CAS), 637 IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_CAS), 638 639 IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), 640 IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 641 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS), 642 IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | 643 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS), 644 IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), 645 646 IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | 647 IAP_F_CC2E | IAP_F_CA), 648 IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), 649 IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), 650 IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 651 IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 652 IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), 653 654 IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 655 IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 656 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 657 IAP_F_HW), 658 IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 659 IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), 660 IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), 661 IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | 662 IAP_F_SBX), 663 664 IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 665 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), 666 IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 667 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), 668 IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 669 IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), 670 IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), 671 IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), 672 IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), 673 IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 674 IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), 675 IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW), 676 IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 677 IAP_F_SBX | IAP_F_HW), 678 IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW), 679 IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW), 680 IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW), 681 IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW), 682 IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 683 IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 684 IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), 685 686 IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 687 IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), 688 IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), 689 IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), 690 691 IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 692 IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 693 IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 694 695 IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 696 IAP_F_WM), 697 IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), 698 IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), 699 700 IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW), 701 IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 702 703 IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 704 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 705 IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 706 IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 707 IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 708 IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 709 710 IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), 711 IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 712 IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 713 IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 714 IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 715 IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 716 717 IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 718 IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 719 IAP_F_WM | IAP_F_SB | IAP_F_SBX), 720 IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 721 IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 722 IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 723 IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 724 IAP_F_SBX), 725 IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 726 IAP_F_SBX), 727 IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 728 IAP_F_SBX), 729 IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 730 IAP_F_SBX), 731 IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), 732 733 IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 734 IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | 735 IAP_F_SBX), 736 IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 737 IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), 738 739 IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 740 IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 741 IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 742 IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 743 IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 744 IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 745 IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 746 IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 747 IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), 748 749 IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 750 IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), 751 IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 752 IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 753 IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 754 IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), 755 756 IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 757 IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 758 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 759 IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 760 761 IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 762 IAP_F_SBX), 763 764 IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 765 IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 766 767 IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 768 IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 769 IAP_F_I7 | IAP_F_WM), 770 IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 771 772 IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), 773 IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), 774 IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), 775 776 IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 777 778 IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 779 IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 780 IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), 781 IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 782 783 IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 784 IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 785 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 786 IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 787 IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 788 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 789 IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 790 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 791 IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 792 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 793 IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 794 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 795 IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 796 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 797 IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 798 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 799 IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW), 800 IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW), 801 IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW), 802 IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW), 803 IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 804 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 805 IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 806 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 807 IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW), 808 IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW), 809 IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW), 810 IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW), 811 IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 812 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 813 IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 814 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 815 IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW), 816 IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW), 817 IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW), 818 IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW), 819 IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 820 IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW), 821 IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW), 822 IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW), 823 824 IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 825 826 IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 827 IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 828 IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 829 IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 830 IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 831 IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 832 IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 833 IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 834 IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 835 IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 836 IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 837 IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 838 839 IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), 840 IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 841 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 842 IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 843 IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | 844 IAP_F_SBX), 845 IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 846 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 847 IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 848 IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 849 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 850 IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 851 IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 852 IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 853 IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW), 854 IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 855 IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 856 IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 857 858 IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 859 IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 860 IAP_F_SBX | IAP_F_IBX), 861 IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), 862 IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 863 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 864 IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | 865 IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 866 IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 867 IAP_F_SBX | IAP_F_IBX), 868 869 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), 870 IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 871 IAP_F_CA | IAP_F_CC2), 872 IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), 873 IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), 874 875 IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 876 IAP_F_ALLCPUSCORE2), 877 IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), 878 IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), 879 IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 880 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 881 IAP_F_CAS), 882 IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | 883 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 884 IAP_F_CAS), 885 886 IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, 887 IAP_F_ALLCPUSCORE2), 888 IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_CAS), 889 IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_CAS), 890 IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), 891 IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 892 893 IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), 894 IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 895 896 IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), 897 898 IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 899 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 900 IAP_F_HW | IAP_F_CAS), 901 IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 902 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 903 IAP_F_HW | IAP_F_CAS), 904 IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 905 906 IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), 907 908 IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 909 IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), 910 IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), 911 IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), 912 IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), 913 IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), 914 IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), 915 916 IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), 917 IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), 918 IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), 919 IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), 920 IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), 921 IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), 922 IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), 923 924 IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), 925 IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), 926 IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), 927 IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), 928 IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), 929 IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 930 931 IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 932 IAP_F_I7), 933 IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | 934 IAP_F_CC2 | IAP_F_I7), 935 936 IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), 937 938 IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), 939 940 IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 941 IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 942 943 IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 944 IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 945 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 946 IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), 947 948 IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), 949 IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 950 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 951 IAP_F_HW), 952 IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 953 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | 954 IAP_F_HW), 955 IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | 956 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 957 IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW), 958 IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 959 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 960 IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW), 961 IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW), 962 IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW), 963 IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW), 964 965 IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 966 IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), 967 IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), 968 IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), 969 IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), 970 971 IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 972 IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 973 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 974 IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 975 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 976 977 IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), 978 979 IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 980 IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 981 IAP_F_SB | IAP_F_SBX), 982 IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 983 IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 984 985 IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), 986 IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), 987 IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), 988 IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), 989 IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), 990 991 IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 992 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 993 IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 994 IAP_F_SB | IAP_F_SBX), 995 IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 996 IAP_F_SB | IAP_F_SBX), 997 IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 998 IAP_F_SB | IAP_F_SBX), 999 1000 IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1001 1002 IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1003 1004 IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1005 IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1006 IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1007 IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1008 1009 IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1010 IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1011 IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1012 1013 IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1014 IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1015 IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1016 IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1017 1018 IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1019 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1020 IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1021 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1022 1023 IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1024 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1025 1026 IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB), 1027 IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX), 1028 1029 IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1030 IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1031 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1032 IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1033 IAP_F_IBX | IAP_F_HW), 1034 IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1035 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1036 IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1037 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1038 1039 IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1040 IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), 1041 1042 IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), 1043 IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), 1044 1045 IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, 1046 IAP_F_CA | IAP_F_CC2), 1047 IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), 1048 IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1049 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1050 IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1051 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1052 1053 IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1054 IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), 1055 1056 IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, 1057 IAP_F_CA | IAP_F_CC2), 1058 IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), 1059 1060 IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1061 1062 IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1063 IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), 1064 1065 IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1066 IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1067 IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1068 IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1069 1070 IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1071 IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1072 1073 IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1074 IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), 1075 1076 IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1077 IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), 1078 1079 IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1080 IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), 1081 1082 IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1083 IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), 1084 1085 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, 1086 IAP_F_CA | IAP_F_CC2), 1087 IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), 1088 1089 IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), 1090 IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), 1091 1092 IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1093 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1094 IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1095 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1096 IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1097 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1098 IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1099 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1100 IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1101 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1102 IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1103 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1104 IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1105 IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1106 IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1107 1108 IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1109 1110 IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), 1111 1112 IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), 1113 1114 IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1115 IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), 1116 1117 IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), 1118 1119 IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1120 IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1121 IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1122 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1123 IAP_F_CAS), 1124 IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1125 IAP_F_WM | IAP_F_CAS), 1126 IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1127 1128 IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1129 IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), 1130 IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), 1131 1132 IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1133 IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1134 IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), 1135 IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1136 IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), 1137 IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), 1138 1139 IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), 1140 IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1141 1142 IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), 1143 IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1144 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1145 IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1146 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1147 IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1148 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1149 IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW), 1150 IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | 1151 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1152 IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW), 1153 IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW), 1154 IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW), 1155 IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1156 1157 IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1158 1159 IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1160 IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1161 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1162 IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1163 IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1164 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1165 IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1166 IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1167 1168 IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1169 IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1170 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1171 IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1172 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1173 IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1174 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1175 IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1176 IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1177 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1178 IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1179 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1180 IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1181 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1182 IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1183 IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1184 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1185 IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1186 IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1187 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1188 IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1189 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1190 1191 IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1192 IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1193 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1194 IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1195 IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1196 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1197 IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1198 IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1199 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1200 IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1201 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1202 IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1203 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1204 IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1205 IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1206 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1207 IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1208 IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1209 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1210 IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1211 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1212 1213 IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1214 IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1215 IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1216 IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1217 IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1218 IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1219 1220 IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1221 IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1222 IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1223 IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1224 IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1225 1226 IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1227 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1228 1229 IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1230 IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1231 IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1232 1233 IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1234 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1235 IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1236 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1237 IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1238 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1239 IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1240 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1241 IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1242 IAP_F_SBX | IAP_F_IBX), 1243 IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1244 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1245 IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1246 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1247 IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1248 IAP_F_SBX | IAP_F_IBX), 1249 IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1250 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1251 IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1252 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1253 1254 IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), 1255 IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1256 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1257 IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1258 IAP_F_SB | IAP_F_SBX), 1259 IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1260 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1261 IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1262 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1263 IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1264 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1265 IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1266 IAP_F_SB | IAP_F_SBX), 1267 IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1268 IAP_F_SB | IAP_F_SBX), 1269 IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1270 IAP_F_SB | IAP_F_SBX), 1271 1272 IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1273 IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1274 IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1275 IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW), 1276 IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW), 1277 1278 IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1279 IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1280 IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1281 1282 IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), 1283 IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), 1284 IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), 1285 IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), 1286 1287 IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1288 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1289 IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1290 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1291 1292 IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1293 IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1294 IAP_F_SBX | IAP_F_IBX), 1295 IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1296 1297 IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1298 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1299 1300 IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1301 IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1302 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1303 IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | 1304 IAP_F_IBX | IAP_F_HW), 1305 IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1306 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1307 IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | 1308 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1309 IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1310 IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), 1311 IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1312 IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), 1313 1314 IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1315 IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1316 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1317 IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1318 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1319 IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1320 IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1321 IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1322 IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1323 IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1324 IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1325 IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1326 IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1327 IAP_F_WM), 1328 1329 IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1330 IAP_F_SB | IAP_F_SBX), 1331 1332 IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1333 IAP_F_WM | IAP_F_I7O), 1334 IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1335 IAP_F_WM | IAP_F_I7O), 1336 IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1337 IAP_F_WM | IAP_F_I7O), 1338 IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1339 IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1340 IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1341 IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), 1342 IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), 1343 IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), 1344 IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), 1345 IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), 1346 IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), 1347 1348 IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), 1349 IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), 1350 IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), 1351 1352 IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1353 IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_CAS), 1354 1355 IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1356 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS), 1357 IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), 1358 1359 IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1360 IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1361 IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1362 1363 IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), 1364 IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), 1365 1366 IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1367 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1368 1369 IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW), 1370 IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW), 1371 IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW), 1372 IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW), 1373 IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW), 1374 IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW), 1375 IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW), 1376 IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW), 1377 1378 IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1379 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1380 IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1381 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1382 1383 IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1384 1385 IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1386 IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | 1387 IAP_F_CAS), 1388 IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1389 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1390 IAP_F_IBX | IAP_F_HW), 1391 IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1392 IAP_F_I7 | IAP_F_WM | IAP_F_SB), 1393 IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1394 IAP_F_I7 | IAP_F_WM), 1395 IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), 1396 1397 IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), 1398 IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1399 IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1400 IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1401 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1402 IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1403 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1404 IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1405 IAP_F_SBX | IAP_F_IBX), 1406 IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW), 1407 IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1408 1409 IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), 1410 IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1411 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1412 IAP_F_IBX | IAP_F_HW | IAP_F_CAS), 1413 IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1414 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1415 IAP_F_IBX | IAP_F_HW), 1416 IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1417 IAP_F_I7 | IAP_F_WM), 1418 IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1419 IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1420 IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), 1421 IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), 1422 1423 IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), 1424 IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1425 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1426 IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1427 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS), 1428 IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1429 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1430 IAP_F_IBX | IAP_F_HW | IAP_F_CAS), 1431 IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_CAS), 1432 IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), 1433 IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1434 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1435 1436 IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1437 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1438 IAP_F_IBX | IAP_F_HW | IAP_F_CAS), 1439 IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1440 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1441 IAP_F_IBX | IAP_F_HW), 1442 IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1443 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1444 IAP_F_IBX | IAP_F_HW), 1445 IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1446 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1447 IAP_F_IBX | IAP_F_HW), 1448 IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1449 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1450 IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1451 IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), 1452 IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1453 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1454 IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1455 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1456 IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1457 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1458 IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_CAS), 1459 IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_CAS), 1460 IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_CAS), 1461 IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_CAS), 1462 IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_CAS), 1463 IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_CAS), 1464 IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_CAS), 1465 IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_CAS), 1466 1467 IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1468 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | 1469 IAP_F_IBX | IAP_F_HW | IAP_F_CAS), 1470 IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1471 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1472 IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1473 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1474 IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1475 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1476 IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1477 IAP_F_SBX | IAP_F_IBX), 1478 IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1479 IAP_F_SBX | IAP_F_IBX), 1480 IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_CAS), 1481 IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_CAS), 1482 IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_CAS), 1483 IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_CAS), 1484 IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_CAS), 1485 IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_CAS), 1486 IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_CAS), 1487 IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_CAS), 1488 1489 IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), 1490 IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1491 IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1492 1493 IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), 1494 IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1495 IAP_F_I7 | IAP_F_WM), 1496 IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1497 IAP_F_I7 | IAP_F_WM), 1498 IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1499 IAP_F_I7 | IAP_F_WM), 1500 IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1501 IAP_F_I7 | IAP_F_WM), 1502 IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1503 IAP_F_I7 | IAP_F_WM), 1504 IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1505 1506 IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1507 IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1508 1509 IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1510 1511 IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), 1512 IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), 1513 IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1514 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1515 IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1516 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1517 IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1518 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1519 IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1520 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1521 IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1522 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1523 IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_CAS), 1524 IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_CAS), 1525 IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_CAS), 1526 1527 IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1528 IAP_F_I7 | IAP_F_WM | IAP_F_CAS), 1529 IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1530 IAP_F_I7 | IAP_F_WM), 1531 IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1532 IAP_F_I7 | IAP_F_WM), 1533 IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1534 IAP_F_I7 | IAP_F_WM), 1535 IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | 1536 IAP_F_WM), 1537 IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_CAS), 1538 IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1539 IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1540 1541 IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), 1542 IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | 1543 IAP_F_I7 | IAP_F_WM), 1544 IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1545 IAP_F_I7 | IAP_F_WM), 1546 IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1547 IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1548 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1549 1550 IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1551 IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1552 IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS), 1553 IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1554 IAP_F_SBX | IAP_F_IBX), 1555 1556 IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1557 IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1558 1559 /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ 1560 IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), 1561 IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | 1562 IAP_F_IBX | IAP_F_HW), 1563 IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1564 IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1565 IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1566 IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1567 IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1568 IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1569 IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1570 IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1571 IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1572 IAPDESCR(D0H_80H, 0xD0, 0x80, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW), 1573 IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1574 IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX), 1575 1576 IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | 1577 IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1578 IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1579 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1580 IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1581 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1582 IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1583 IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW), 1584 IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1585 IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1586 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1587 1588 IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1589 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1590 IAP_F_IBX | IAP_F_HW), 1591 IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1592 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1593 IAP_F_IBX | IAP_F_HW), 1594 IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1595 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1596 IAP_F_IBX | IAP_F_HW), 1597 IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1598 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1599 IAP_F_IBX | IAP_F_HW), 1600 IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1601 IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | 1602 IAP_F_IBX | IAP_F_HW), 1603 1604 IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), 1605 1606 IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | 1607 IAP_F_IBX | IAP_F_HW), 1608 IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), 1609 IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX), 1610 IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX), 1611 1612 IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1613 IAP_F_I7 | IAP_F_WM), 1614 IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1615 IAP_F_SB | IAP_F_SBX), 1616 IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1617 IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1618 IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1619 1620 IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | 1621 IAP_F_I7 | IAP_F_WM), 1622 IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1623 IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1624 IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1625 IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1626 1627 IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), 1628 1629 IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), 1630 IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), 1631 IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), 1632 IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), 1633 IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), 1634 1635 IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), 1636 IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), 1637 IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), 1638 IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), 1639 1640 IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), 1641 IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), 1642 IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), 1643 1644 IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), 1645 IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1646 1647 IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1648 IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1649 IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1650 IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1651 IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1652 IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), 1653 1654 IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1655 IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1656 IAP_F_WM), 1657 1658 IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), 1659 1660 IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1661 IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), 1662 1663 IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1664 1665 IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), 1666 IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | 1667 IAP_F_WM | IAP_F_SBX | IAP_F_CAS), 1668 IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1669 IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_CAS), 1670 IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_CAS), 1671 IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IBX | IAP_F_HW), 1672 1673 IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_CAS), 1674 1675 IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1676 IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1677 IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), 1678 1679 IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), 1680 1681 IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1682 IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1683 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1684 IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1685 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1686 IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1687 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1688 IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1689 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1690 IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1691 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1692 IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1693 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1694 IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1695 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1696 IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1697 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1698 1699 IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | 1700 IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1701 IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1702 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1703 IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1704 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1705 IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1706 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW), 1707 1708 IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1709 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1710 IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1711 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1712 IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1713 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1714 IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW), 1715 IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW), 1716 IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1717 IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), 1718 IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | 1719 IAP_F_IBX), 1720 IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1721 1722 IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), 1723 IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), 1724 IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), 1725 IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), 1726 IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), 1727 IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), 1728 1729 IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), 1730 IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), 1731 IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), 1732 IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), 1733 IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | 1734 IAP_F_SB | IAP_F_SBX), 1735 1736 IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), 1737 1738 IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1739 IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1740 IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1741 1742 IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), 1743 IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), 1744 1745 IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1746 IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1747 IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1748 IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1749 IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1750 IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1751 IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), 1752 }; 1753 1754 static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); 1755 1756 static pmc_value_t 1757 iap_perfctr_value_to_reload_count(pmc_value_t v) 1758 { 1759 v &= (1ULL << core_iap_width) - 1; 1760 return (1ULL << core_iap_width) - v; 1761 } 1762 1763 static pmc_value_t 1764 iap_reload_count_to_perfctr_value(pmc_value_t rlc) 1765 { 1766 return (1ULL << core_iap_width) - rlc; 1767 } 1768 1769 static int 1770 iap_pmc_has_overflowed(int ri) 1771 { 1772 uint64_t v; 1773 1774 /* 1775 * We treat a Core (i.e., Intel architecture v1) PMC as has 1776 * having overflowed if its MSB is zero. 1777 */ 1778 v = rdpmc(ri); 1779 return ((v & (1ULL << (core_iap_width - 1))) == 0); 1780 } 1781 1782 /* 1783 * Check an event against the set of supported architectural events. 1784 * 1785 * If the event is not architectural EV_IS_NOTARCH is returned. 1786 * If the event is architectural and supported on this CPU, the correct 1787 * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. 1788 * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. 1789 */ 1790 1791 static int 1792 iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) 1793 { 1794 enum core_arch_events ae; 1795 1796 switch (pe) { 1797 case PMC_EV_IAP_ARCH_UNH_COR_CYC: 1798 ae = CORE_AE_UNHALTED_CORE_CYCLES; 1799 *map = PMC_EV_IAP_EVENT_C4H_00H; 1800 break; 1801 case PMC_EV_IAP_ARCH_INS_RET: 1802 ae = CORE_AE_INSTRUCTION_RETIRED; 1803 *map = PMC_EV_IAP_EVENT_C0H_00H; 1804 break; 1805 case PMC_EV_IAP_ARCH_UNH_REF_CYC: 1806 ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; 1807 *map = PMC_EV_IAP_EVENT_3CH_01H; 1808 break; 1809 case PMC_EV_IAP_ARCH_LLC_REF: 1810 ae = CORE_AE_LLC_REFERENCE; 1811 *map = PMC_EV_IAP_EVENT_2EH_4FH; 1812 break; 1813 case PMC_EV_IAP_ARCH_LLC_MIS: 1814 ae = CORE_AE_LLC_MISSES; 1815 *map = PMC_EV_IAP_EVENT_2EH_41H; 1816 break; 1817 case PMC_EV_IAP_ARCH_BR_INS_RET: 1818 ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; 1819 *map = PMC_EV_IAP_EVENT_C4H_00H; 1820 break; 1821 case PMC_EV_IAP_ARCH_BR_MIS_RET: 1822 ae = CORE_AE_BRANCH_MISSES_RETIRED; 1823 *map = PMC_EV_IAP_EVENT_C5H_00H; 1824 break; 1825 1826 default: /* Non architectural event. */ 1827 return (EV_IS_NOTARCH); 1828 } 1829 1830 return (((core_architectural_events & (1 << ae)) == 0) ? 1831 EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); 1832 } 1833 1834 static int 1835 iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) 1836 { 1837 uint32_t mask; 1838 1839 switch (pe) { 1840 /* 1841 * Events valid only on counter 0, 1. 1842 */ 1843 case PMC_EV_IAP_EVENT_40H_01H: 1844 case PMC_EV_IAP_EVENT_40H_02H: 1845 case PMC_EV_IAP_EVENT_40H_04H: 1846 case PMC_EV_IAP_EVENT_40H_08H: 1847 case PMC_EV_IAP_EVENT_40H_0FH: 1848 case PMC_EV_IAP_EVENT_41H_02H: 1849 case PMC_EV_IAP_EVENT_41H_04H: 1850 case PMC_EV_IAP_EVENT_41H_08H: 1851 case PMC_EV_IAP_EVENT_42H_01H: 1852 case PMC_EV_IAP_EVENT_42H_02H: 1853 case PMC_EV_IAP_EVENT_42H_04H: 1854 case PMC_EV_IAP_EVENT_42H_08H: 1855 case PMC_EV_IAP_EVENT_43H_01H: 1856 case PMC_EV_IAP_EVENT_43H_02H: 1857 case PMC_EV_IAP_EVENT_51H_01H: 1858 case PMC_EV_IAP_EVENT_51H_02H: 1859 case PMC_EV_IAP_EVENT_51H_04H: 1860 case PMC_EV_IAP_EVENT_51H_08H: 1861 case PMC_EV_IAP_EVENT_63H_01H: 1862 case PMC_EV_IAP_EVENT_63H_02H: 1863 mask = 0x3; 1864 break; 1865 1866 default: 1867 mask = ~0; /* Any row index is ok. */ 1868 } 1869 1870 return (mask & (1 << ri)); 1871 } 1872 1873 static int 1874 iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) 1875 { 1876 uint32_t mask; 1877 1878 switch (pe) { 1879 /* 1880 * Events valid only on counter 0. 1881 */ 1882 case PMC_EV_IAP_EVENT_60H_01H: 1883 case PMC_EV_IAP_EVENT_60H_02H: 1884 case PMC_EV_IAP_EVENT_60H_04H: 1885 case PMC_EV_IAP_EVENT_60H_08H: 1886 case PMC_EV_IAP_EVENT_B3H_01H: 1887 case PMC_EV_IAP_EVENT_B3H_02H: 1888 case PMC_EV_IAP_EVENT_B3H_04H: 1889 mask = 0x1; 1890 break; 1891 1892 /* 1893 * Events valid only on counter 0, 1. 1894 */ 1895 case PMC_EV_IAP_EVENT_4CH_01H: 1896 case PMC_EV_IAP_EVENT_4EH_01H: 1897 case PMC_EV_IAP_EVENT_4EH_02H: 1898 case PMC_EV_IAP_EVENT_4EH_04H: 1899 case PMC_EV_IAP_EVENT_51H_01H: 1900 case PMC_EV_IAP_EVENT_51H_02H: 1901 case PMC_EV_IAP_EVENT_51H_04H: 1902 case PMC_EV_IAP_EVENT_51H_08H: 1903 case PMC_EV_IAP_EVENT_63H_01H: 1904 case PMC_EV_IAP_EVENT_63H_02H: 1905 mask = 0x3; 1906 break; 1907 1908 default: 1909 mask = ~0; /* Any row index is ok. */ 1910 } 1911 1912 return (mask & (1 << ri)); 1913 } 1914 1915 static int 1916 iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) 1917 { 1918 uint32_t mask; 1919 1920 switch (pe) { 1921 /* Events valid only on counter 0. */ 1922 case PMC_EV_IAP_EVENT_B7H_01H: 1923 mask = 0x1; 1924 break; 1925 /* Events valid only on counter 1. */ 1926 case PMC_EV_IAP_EVENT_C0H_01H: 1927 mask = 0x1; 1928 break; 1929 /* Events valid only on counter 2. */ 1930 case PMC_EV_IAP_EVENT_48H_01H: 1931 case PMC_EV_IAP_EVENT_A2H_02H: 1932 mask = 0x4; 1933 break; 1934 /* Events valid only on counter 3. */ 1935 case PMC_EV_IAP_EVENT_A3H_08H: 1936 case PMC_EV_IAP_EVENT_BBH_01H: 1937 case PMC_EV_IAP_EVENT_CDH_01H: 1938 case PMC_EV_IAP_EVENT_CDH_02H: 1939 mask = 0x8; 1940 break; 1941 default: 1942 mask = ~0; /* Any row index is ok. */ 1943 } 1944 1945 return (mask & (1 << ri)); 1946 } 1947 1948 static int 1949 iap_event_ok_on_counter(enum pmc_event pe, int ri) 1950 { 1951 uint32_t mask; 1952 1953 switch (pe) { 1954 /* 1955 * Events valid only on counter 0. 1956 */ 1957 case PMC_EV_IAP_EVENT_10H_00H: 1958 case PMC_EV_IAP_EVENT_14H_00H: 1959 case PMC_EV_IAP_EVENT_18H_00H: 1960 case PMC_EV_IAP_EVENT_B3H_01H: 1961 case PMC_EV_IAP_EVENT_B3H_02H: 1962 case PMC_EV_IAP_EVENT_B3H_04H: 1963 case PMC_EV_IAP_EVENT_C1H_00H: 1964 case PMC_EV_IAP_EVENT_CBH_01H: 1965 case PMC_EV_IAP_EVENT_CBH_02H: 1966 mask = (1 << 0); 1967 break; 1968 1969 /* 1970 * Events valid only on counter 1. 1971 */ 1972 case PMC_EV_IAP_EVENT_11H_00H: 1973 case PMC_EV_IAP_EVENT_12H_00H: 1974 case PMC_EV_IAP_EVENT_13H_00H: 1975 mask = (1 << 1); 1976 break; 1977 1978 default: 1979 mask = ~0; /* Any row index is ok. */ 1980 } 1981 1982 return (mask & (1 << ri)); 1983 } 1984 1985 static int 1986 iap_allocate_pmc(int cpu, int ri, struct pmc *pm, 1987 const struct pmc_op_pmcallocate *a) 1988 { 1989 int arch, n, model; 1990 enum pmc_event ev, map; 1991 struct iap_event_descr *ie; 1992 uint32_t c, caps, config, cpuflag, evsel, mask; 1993 1994 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 1995 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 1996 KASSERT(ri >= 0 && ri < core_iap_npmc, 1997 ("[core,%d] illegal row-index value %d", __LINE__, ri)); 1998 1999 /* check requested capabilities */ 2000 caps = a->pm_caps; 2001 if ((IAP_PMC_CAPS & caps) != caps) 2002 return (EPERM); 2003 map = 0; /* XXX: silent GCC warning */ 2004 arch = iap_is_event_architectural(pm->pm_event, &map); 2005 if (arch == EV_IS_ARCH_NOTSUPP) 2006 return (EOPNOTSUPP); 2007 else if (arch == EV_IS_ARCH_SUPP) 2008 ev = map; 2009 else 2010 ev = pm->pm_event; 2011 2012 /* 2013 * A small number of events are not supported in all the 2014 * processors based on a given microarchitecture. 2015 */ 2016 if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { 2017 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 2018 if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) 2019 return (EINVAL); 2020 } 2021 2022 switch (core_cputype) { 2023 case PMC_CPU_INTEL_COREI7: 2024 if (iap_event_corei7_ok_on_counter(ev, ri) == 0) 2025 return (EINVAL); 2026 break; 2027 case PMC_CPU_INTEL_SANDYBRIDGE: 2028 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2029 case PMC_CPU_INTEL_IVYBRIDGE: 2030 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2031 case PMC_CPU_INTEL_HASWELL: 2032 if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) 2033 return (EINVAL); 2034 break; 2035 case PMC_CPU_INTEL_WESTMERE: 2036 if (iap_event_westmere_ok_on_counter(ev, ri) == 0) 2037 return (EINVAL); 2038 break; 2039 default: 2040 if (iap_event_ok_on_counter(ev, ri) == 0) 2041 return (EINVAL); 2042 } 2043 2044 /* 2045 * Look for an event descriptor with matching CPU and event id 2046 * fields. 2047 */ 2048 2049 switch (core_cputype) { 2050 default: 2051 case PMC_CPU_INTEL_ATOM: 2052 cpuflag = IAP_F_CA; 2053 break; 2054 case PMC_CPU_INTEL_ATOM_SILVERMONT: 2055 cpuflag = IAP_F_CAS; 2056 break; 2057 case PMC_CPU_INTEL_CORE: 2058 cpuflag = IAP_F_CC; 2059 break; 2060 case PMC_CPU_INTEL_CORE2: 2061 cpuflag = IAP_F_CC2; 2062 break; 2063 case PMC_CPU_INTEL_CORE2EXTREME: 2064 cpuflag = IAP_F_CC2 | IAP_F_CC2E; 2065 break; 2066 case PMC_CPU_INTEL_COREI7: 2067 cpuflag = IAP_F_I7; 2068 break; 2069 case PMC_CPU_INTEL_HASWELL: 2070 cpuflag = IAP_F_HW; 2071 break; 2072 case PMC_CPU_INTEL_IVYBRIDGE: 2073 cpuflag = IAP_F_IB; 2074 break; 2075 case PMC_CPU_INTEL_IVYBRIDGE_XEON: 2076 cpuflag = IAP_F_IBX; 2077 break; 2078 case PMC_CPU_INTEL_SANDYBRIDGE: 2079 cpuflag = IAP_F_SB; 2080 break; 2081 case PMC_CPU_INTEL_SANDYBRIDGE_XEON: 2082 cpuflag = IAP_F_SBX; 2083 break; 2084 case PMC_CPU_INTEL_WESTMERE: 2085 cpuflag = IAP_F_WM; 2086 break; 2087 } 2088 2089 for (n = 0, ie = iap_events; n < niap_events; n++, ie++) 2090 if (ie->iap_ev == ev && ie->iap_flags & cpuflag) 2091 break; 2092 2093 if (n == niap_events) 2094 return (EINVAL); 2095 2096 /* 2097 * A matching event descriptor has been found, so start 2098 * assembling the contents of the event select register. 2099 */ 2100 evsel = ie->iap_evcode; 2101 2102 config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; 2103 2104 /* 2105 * If the event uses a fixed umask value, reject any umask 2106 * bits set by the user. 2107 */ 2108 if (ie->iap_flags & IAP_F_FM) { 2109 2110 if (IAP_UMASK(config) != 0) 2111 return (EINVAL); 2112 2113 evsel |= (ie->iap_umask << 8); 2114 2115 } else { 2116 2117 /* 2118 * Otherwise, the UMASK value needs to be taken from 2119 * the MD fields of the allocation request. Reject 2120 * requests that specify reserved bits. 2121 */ 2122 2123 mask = 0; 2124 2125 if (ie->iap_umask & IAP_M_CORE) { 2126 if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && 2127 c != IAP_CORE_THIS) 2128 return (EINVAL); 2129 mask |= IAP_F_CORE; 2130 } 2131 2132 if (ie->iap_umask & IAP_M_AGENT) 2133 mask |= IAP_F_AGENT; 2134 2135 if (ie->iap_umask & IAP_M_PREFETCH) { 2136 2137 if ((c = (config & IAP_F_PREFETCH)) == 2138 IAP_PREFETCH_RESERVED) 2139 return (EINVAL); 2140 2141 mask |= IAP_F_PREFETCH; 2142 } 2143 2144 if (ie->iap_umask & IAP_M_MESI) 2145 mask |= IAP_F_MESI; 2146 2147 if (ie->iap_umask & IAP_M_SNOOPRESPONSE) 2148 mask |= IAP_F_SNOOPRESPONSE; 2149 2150 if (ie->iap_umask & IAP_M_SNOOPTYPE) 2151 mask |= IAP_F_SNOOPTYPE; 2152 2153 if (ie->iap_umask & IAP_M_TRANSITION) 2154 mask |= IAP_F_TRANSITION; 2155 2156 /* 2157 * If bits outside of the allowed set of umask bits 2158 * are set, reject the request. 2159 */ 2160 if (config & ~mask) 2161 return (EINVAL); 2162 2163 evsel |= (config & mask); 2164 2165 } 2166 2167 /* 2168 * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. 2169 */ 2170 if (core_cputype == PMC_CPU_INTEL_ATOM || 2171 core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || 2172 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2173 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) 2174 evsel |= (config & IAP_ANY); 2175 else if (config & IAP_ANY) 2176 return (EINVAL); 2177 2178 /* 2179 * Check offcore response configuration. 2180 */ 2181 if (a->pm_md.pm_iap.pm_iap_rsp != 0) { 2182 if (ev != PMC_EV_IAP_EVENT_B7H_01H && 2183 ev != PMC_EV_IAP_EVENT_BBH_01H) 2184 return (EINVAL); 2185 if (core_cputype == PMC_CPU_INTEL_COREI7 && 2186 ev == PMC_EV_IAP_EVENT_BBH_01H) 2187 return (EINVAL); 2188 if ((core_cputype == PMC_CPU_INTEL_COREI7 || 2189 core_cputype == PMC_CPU_INTEL_WESTMERE) && 2190 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) 2191 return (EINVAL); 2192 else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || 2193 core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || 2194 core_cputype == PMC_CPU_INTEL_IVYBRIDGE || 2195 core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && 2196 a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) 2197 return (EINVAL); 2198 pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; 2199 } 2200 2201 if (caps & PMC_CAP_THRESHOLD) 2202 evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); 2203 if (caps & PMC_CAP_USER) 2204 evsel |= IAP_USR; 2205 if (caps & PMC_CAP_SYSTEM) 2206 evsel |= IAP_OS; 2207 if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) 2208 evsel |= (IAP_OS | IAP_USR); 2209 if (caps & PMC_CAP_EDGE) 2210 evsel |= IAP_EDGE; 2211 if (caps & PMC_CAP_INVERT) 2212 evsel |= IAP_INV; 2213 if (caps & PMC_CAP_INTERRUPT) 2214 evsel |= IAP_INT; 2215 2216 pm->pm_md.pm_iap.pm_iap_evsel = evsel; 2217 2218 return (0); 2219 } 2220 2221 static int 2222 iap_config_pmc(int cpu, int ri, struct pmc *pm) 2223 { 2224 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2225 ("[core,%d] illegal CPU %d", __LINE__, cpu)); 2226 2227 KASSERT(ri >= 0 && ri < core_iap_npmc, 2228 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2229 2230 PMCDBG(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); 2231 2232 KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, 2233 cpu)); 2234 2235 core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; 2236 2237 return (0); 2238 } 2239 2240 static int 2241 iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 2242 { 2243 int error; 2244 struct pmc_hw *phw; 2245 char iap_name[PMC_NAME_MAX]; 2246 2247 phw = &core_pcpu[cpu]->pc_corepmcs[ri]; 2248 2249 (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); 2250 if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, 2251 NULL)) != 0) 2252 return (error); 2253 2254 pi->pm_class = PMC_CLASS_IAP; 2255 2256 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 2257 pi->pm_enabled = TRUE; 2258 *ppmc = phw->phw_pmc; 2259 } else { 2260 pi->pm_enabled = FALSE; 2261 *ppmc = NULL; 2262 } 2263 2264 return (0); 2265 } 2266 2267 static int 2268 iap_get_config(int cpu, int ri, struct pmc **ppm) 2269 { 2270 *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2271 2272 return (0); 2273 } 2274 2275 static int 2276 iap_get_msr(int ri, uint32_t *msr) 2277 { 2278 KASSERT(ri >= 0 && ri < core_iap_npmc, 2279 ("[iap,%d] ri %d out of range", __LINE__, ri)); 2280 2281 *msr = ri; 2282 2283 return (0); 2284 } 2285 2286 static int 2287 iap_read_pmc(int cpu, int ri, pmc_value_t *v) 2288 { 2289 struct pmc *pm; 2290 pmc_value_t tmp; 2291 2292 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2293 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2294 KASSERT(ri >= 0 && ri < core_iap_npmc, 2295 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2296 2297 pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; 2298 2299 KASSERT(pm, 2300 ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, 2301 ri)); 2302 2303 tmp = rdpmc(ri); 2304 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2305 *v = iap_perfctr_value_to_reload_count(tmp); 2306 else 2307 *v = tmp & ((1ULL << core_iap_width) - 1); 2308 2309 PMCDBG(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, 2310 ri, *v); 2311 2312 return (0); 2313 } 2314 2315 static int 2316 iap_release_pmc(int cpu, int ri, struct pmc *pm) 2317 { 2318 (void) pm; 2319 2320 PMCDBG(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, 2321 pm); 2322 2323 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2324 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2325 KASSERT(ri >= 0 && ri < core_iap_npmc, 2326 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2327 2328 KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc 2329 == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); 2330 2331 return (0); 2332 } 2333 2334 static int 2335 iap_start_pmc(int cpu, int ri) 2336 { 2337 struct pmc *pm; 2338 uint32_t evsel; 2339 struct core_cpu *cc; 2340 2341 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2342 ("[core,%d] illegal CPU value %d", __LINE__, cpu)); 2343 KASSERT(ri >= 0 && ri < core_iap_npmc, 2344 ("[core,%d] illegal row-index %d", __LINE__, ri)); 2345 2346 cc = core_pcpu[cpu]; 2347 pm = cc->pc_corepmcs[ri].phw_pmc; 2348 2349 KASSERT(pm, 2350 ("[core,%d] starting cpu%d,ri%d with no pmc configured", 2351 __LINE__, cpu, ri)); 2352 2353 PMCDBG(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); 2354 2355 evsel = pm->pm_md.pm_iap.pm_iap_evsel; 2356 2357 PMCDBG(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", 2358 cpu, ri, IAP_EVSEL0 + ri, evsel); 2359 2360 /* Event specific configuration. */ 2361 switch (pm->pm_event) { 2362 case PMC_EV_IAP_EVENT_B7H_01H: 2363 wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); 2364 break; 2365 case PMC_EV_IAP_EVENT_BBH_01H: 2366 wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); 2367 break; 2368 default: 2369 break; 2370 } 2371 2372 wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); 2373 2374 if (core_cputype == PMC_CPU_INTEL_CORE) 2375 return (0); 2376 2377 do { 2378 cc->pc_resync = 0; 2379 cc->pc_globalctrl |= (1ULL << ri); 2380 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2381 } while (cc->pc_resync != 0); 2382 2383 return (0); 2384 } 2385 2386 static int 2387 iap_stop_pmc(int cpu, int ri) 2388 { 2389 struct pmc *pm; 2390 struct core_cpu *cc; 2391 uint64_t msr; 2392 2393 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2394 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2395 KASSERT(ri >= 0 && ri < core_iap_npmc, 2396 ("[core,%d] illegal row index %d", __LINE__, ri)); 2397 2398 cc = core_pcpu[cpu]; 2399 pm = cc->pc_corepmcs[ri].phw_pmc; 2400 2401 KASSERT(pm, 2402 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2403 cpu, ri)); 2404 2405 PMCDBG(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); 2406 2407 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2408 wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ 2409 2410 if (core_cputype == PMC_CPU_INTEL_CORE) 2411 return (0); 2412 2413 msr = 0; 2414 do { 2415 cc->pc_resync = 0; 2416 cc->pc_globalctrl &= ~(1ULL << ri); 2417 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2418 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); 2419 } while (cc->pc_resync != 0); 2420 2421 return (0); 2422 } 2423 2424 static int 2425 iap_write_pmc(int cpu, int ri, pmc_value_t v) 2426 { 2427 struct pmc *pm; 2428 struct core_cpu *cc; 2429 2430 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 2431 ("[core,%d] illegal cpu value %d", __LINE__, cpu)); 2432 KASSERT(ri >= 0 && ri < core_iap_npmc, 2433 ("[core,%d] illegal row index %d", __LINE__, ri)); 2434 2435 cc = core_pcpu[cpu]; 2436 pm = cc->pc_corepmcs[ri].phw_pmc; 2437 2438 KASSERT(pm, 2439 ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, 2440 cpu, ri)); 2441 2442 PMCDBG(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, 2443 IAP_PMC0 + ri, v); 2444 2445 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2446 v = iap_reload_count_to_perfctr_value(v); 2447 2448 /* 2449 * Write the new value to the counter. The counter will be in 2450 * a stopped state when the pcd_write() entry point is called. 2451 */ 2452 2453 wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); 2454 2455 return (0); 2456 } 2457 2458 2459 static void 2460 iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, 2461 int flags) 2462 { 2463 struct pmc_classdep *pcd; 2464 2465 KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); 2466 2467 PMCDBG(MDP,INI,1, "%s", "iap-initialize"); 2468 2469 /* Remember the set of architectural events supported. */ 2470 core_architectural_events = ~flags; 2471 2472 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; 2473 2474 pcd->pcd_caps = IAP_PMC_CAPS; 2475 pcd->pcd_class = PMC_CLASS_IAP; 2476 pcd->pcd_num = npmc; 2477 pcd->pcd_ri = md->pmd_npmc; 2478 pcd->pcd_width = pmcwidth; 2479 2480 pcd->pcd_allocate_pmc = iap_allocate_pmc; 2481 pcd->pcd_config_pmc = iap_config_pmc; 2482 pcd->pcd_describe = iap_describe; 2483 pcd->pcd_get_config = iap_get_config; 2484 pcd->pcd_get_msr = iap_get_msr; 2485 pcd->pcd_pcpu_fini = core_pcpu_fini; 2486 pcd->pcd_pcpu_init = core_pcpu_init; 2487 pcd->pcd_read_pmc = iap_read_pmc; 2488 pcd->pcd_release_pmc = iap_release_pmc; 2489 pcd->pcd_start_pmc = iap_start_pmc; 2490 pcd->pcd_stop_pmc = iap_stop_pmc; 2491 pcd->pcd_write_pmc = iap_write_pmc; 2492 2493 md->pmd_npmc += npmc; 2494 } 2495 2496 static int 2497 core_intr(int cpu, struct trapframe *tf) 2498 { 2499 pmc_value_t v; 2500 struct pmc *pm; 2501 struct core_cpu *cc; 2502 int error, found_interrupt, ri; 2503 uint64_t msr; 2504 2505 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2506 TRAPF_USERMODE(tf)); 2507 2508 found_interrupt = 0; 2509 cc = core_pcpu[cpu]; 2510 2511 for (ri = 0; ri < core_iap_npmc; ri++) { 2512 2513 if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || 2514 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2515 continue; 2516 2517 if (!iap_pmc_has_overflowed(ri)) 2518 continue; 2519 2520 found_interrupt = 1; 2521 2522 if (pm->pm_state != PMC_STATE_RUNNING) 2523 continue; 2524 2525 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2526 TRAPF_USERMODE(tf)); 2527 2528 v = pm->pm_sc.pm_reloadcount; 2529 v = iaf_reload_count_to_perfctr_value(v); 2530 2531 /* 2532 * Stop the counter, reload it but only restart it if 2533 * the PMC is not stalled. 2534 */ 2535 msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; 2536 wrmsr(IAP_EVSEL0 + ri, msr); 2537 wrmsr(IAP_PMC0 + ri, v); 2538 2539 if (error) 2540 continue; 2541 2542 wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | 2543 IAP_EN)); 2544 } 2545 2546 if (found_interrupt) 2547 lapic_reenable_pmc(); 2548 2549 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2550 &pmc_stats.pm_intr_ignored, 1); 2551 2552 return (found_interrupt); 2553 } 2554 2555 static int 2556 core2_intr(int cpu, struct trapframe *tf) 2557 { 2558 int error, found_interrupt, n; 2559 uint64_t flag, intrstatus, intrenable, msr; 2560 struct pmc *pm; 2561 struct core_cpu *cc; 2562 pmc_value_t v; 2563 2564 PMCDBG(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, 2565 TRAPF_USERMODE(tf)); 2566 2567 /* 2568 * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which 2569 * PMCs have a pending PMI interrupt. We take a 'snapshot' of 2570 * the current set of interrupting PMCs and process these 2571 * after stopping them. 2572 */ 2573 intrstatus = rdmsr(IA_GLOBAL_STATUS); 2574 intrenable = intrstatus & core_pmcmask; 2575 2576 PMCDBG(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, 2577 (uintmax_t) intrstatus); 2578 2579 found_interrupt = 0; 2580 cc = core_pcpu[cpu]; 2581 2582 KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); 2583 2584 cc->pc_globalctrl &= ~intrenable; 2585 cc->pc_resync = 1; /* MSRs now potentially out of sync. */ 2586 2587 /* 2588 * Stop PMCs and clear overflow status bits. 2589 */ 2590 msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; 2591 wrmsr(IA_GLOBAL_CTRL, msr); 2592 wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | 2593 IA_GLOBAL_STATUS_FLAG_OVFBUF | 2594 IA_GLOBAL_STATUS_FLAG_CONDCHG); 2595 2596 /* 2597 * Look for interrupts from fixed function PMCs. 2598 */ 2599 for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; 2600 n++, flag <<= 1) { 2601 2602 if ((intrstatus & flag) == 0) 2603 continue; 2604 2605 found_interrupt = 1; 2606 2607 pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; 2608 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2609 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2610 continue; 2611 2612 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2613 TRAPF_USERMODE(tf)); 2614 if (error) 2615 intrenable &= ~flag; 2616 2617 v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2618 2619 /* Reload sampling count. */ 2620 wrmsr(IAF_CTR0 + n, v); 2621 2622 PMCDBG(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, 2623 error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); 2624 } 2625 2626 /* 2627 * Process interrupts from the programmable counters. 2628 */ 2629 for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { 2630 if ((intrstatus & flag) == 0) 2631 continue; 2632 2633 found_interrupt = 1; 2634 2635 pm = cc->pc_corepmcs[n].phw_pmc; 2636 if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || 2637 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 2638 continue; 2639 2640 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 2641 TRAPF_USERMODE(tf)); 2642 if (error) 2643 intrenable &= ~flag; 2644 2645 v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); 2646 2647 PMCDBG(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, 2648 (uintmax_t) v); 2649 2650 /* Reload sampling count. */ 2651 wrmsr(IAP_PMC0 + n, v); 2652 } 2653 2654 /* 2655 * Reenable all non-stalled PMCs. 2656 */ 2657 PMCDBG(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, 2658 (uintmax_t) intrenable); 2659 2660 cc->pc_globalctrl |= intrenable; 2661 2662 wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); 2663 2664 PMCDBG(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " 2665 "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), 2666 (uintmax_t) rdmsr(IA_GLOBAL_CTRL), 2667 (uintmax_t) rdmsr(IA_GLOBAL_STATUS), 2668 (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); 2669 2670 if (found_interrupt) 2671 lapic_reenable_pmc(); 2672 2673 atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : 2674 &pmc_stats.pm_intr_ignored, 1); 2675 2676 return (found_interrupt); 2677 } 2678 2679 int 2680 pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) 2681 { 2682 int cpuid[CORE_CPUID_REQUEST_SIZE]; 2683 int ipa_version, flags, nflags; 2684 2685 do_cpuid(CORE_CPUID_REQUEST, cpuid); 2686 2687 ipa_version = (version_override > 0) ? version_override : 2688 cpuid[CORE_CPUID_EAX] & 0xFF; 2689 core_cputype = md->pmd_cputype; 2690 2691 PMCDBG(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", 2692 core_cputype, maxcpu, ipa_version); 2693 2694 if (ipa_version < 1 || ipa_version > 3 || 2695 (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { 2696 /* Unknown PMC architecture. */ 2697 printf("hwpc_core: unknown PMC architecture: %d\n", 2698 ipa_version); 2699 return (EPROGMISMATCH); 2700 } 2701 2702 core_pmcmask = 0; 2703 2704 /* 2705 * Initialize programmable counters. 2706 */ 2707 core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; 2708 core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; 2709 2710 core_pmcmask |= ((1ULL << core_iap_npmc) - 1); 2711 2712 nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; 2713 flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); 2714 2715 iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); 2716 2717 /* 2718 * Initialize fixed function counters, if present. 2719 */ 2720 if (core_cputype != PMC_CPU_INTEL_CORE) { 2721 core_iaf_ri = core_iap_npmc; 2722 core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; 2723 core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; 2724 2725 iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); 2726 core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; 2727 } 2728 2729 PMCDBG(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, 2730 core_iaf_ri); 2731 2732 core_pcpu = malloc(sizeof(*core_pcpu) * maxcpu, M_PMC, 2733 M_ZERO | M_WAITOK); 2734 2735 /* 2736 * Choose the appropriate interrupt handler. 2737 */ 2738 if (ipa_version == 1) 2739 md->pmd_intr = core_intr; 2740 else 2741 md->pmd_intr = core2_intr; 2742 2743 md->pmd_pcpu_fini = NULL; 2744 md->pmd_pcpu_init = NULL; 2745 2746 return (0); 2747 } 2748 2749 void 2750 pmc_core_finalize(struct pmc_mdep *md) 2751 { 2752 PMCDBG(MDP,INI,1, "%s", "core-finalize"); 2753 2754 free(core_pcpu, M_PMC); 2755 core_pcpu = NULL; 2756 } 2757