1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * Copyright (c) 2021 ARM Ltd 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 /* Arm CoreLink CMN-600 Coherent Mesh Network PMU Driver */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <sys/pmc.h> 44 #include <sys/pmckern.h> 45 #include <sys/systm.h> 46 47 #include <machine/cmn600_reg.h> 48 49 struct cmn600_descr { 50 struct pmc_descr pd_descr; /* "base class" */ 51 void *pd_rw_arg; /* Argument to use with read/write */ 52 struct pmc *pd_pmc; 53 struct pmc_hw *pd_phw; 54 uint32_t pd_nodeid; 55 int32_t pd_node_type; 56 int pd_local_counter; 57 58 }; 59 60 static struct cmn600_descr **cmn600_pmcdesc; 61 62 static struct cmn600_pmc cmn600_pmcs[CMN600_UNIT_MAX]; 63 static int cmn600_units = 0; 64 65 static inline struct cmn600_descr * 66 cmn600desc(int ri) 67 { 68 69 return (cmn600_pmcdesc[ri]); 70 } 71 72 static inline int 73 class_ri2unit(int ri) 74 { 75 76 return (ri / CMN600_COUNTERS_N); 77 } 78 79 #define EVENCNTR(x) (((x) >> POR_DT_PMEVCNT_EVENCNT_SHIFT) << \ 80 POR_DTM_PMEVCNT_CNTR_WIDTH) 81 #define ODDCNTR(x) (((x) >> POR_DT_PMEVCNT_ODDCNT_SHIFT) << \ 82 POR_DTM_PMEVCNT_CNTR_WIDTH) 83 84 static uint64_t 85 cmn600_pmu_readcntr(void *arg, u_int nodeid, u_int xpcntr, u_int dtccntr, 86 u_int width) 87 { 88 uint64_t dtcval, xpval; 89 90 KASSERT(xpcntr < 4, ("[cmn600,%d] XP counter number %d is too big." 91 " Max: 3", __LINE__, xpcntr)); 92 KASSERT(dtccntr < 8, ("[cmn600,%d] Global counter number %d is too" 93 " big. Max: 7", __LINE__, dtccntr)); 94 95 dtcval = pmu_cmn600_rd8(arg, nodeid, NODE_TYPE_DTC, 96 POR_DT_PMEVCNT(dtccntr >> 1)); 97 if (width == 4) { 98 dtcval = (dtccntr & 1) ? ODDCNTR(dtcval) : EVENCNTR(dtcval); 99 dtcval &= 0xffffffff0000UL; 100 } else 101 dtcval <<= POR_DTM_PMEVCNT_CNTR_WIDTH; 102 103 xpval = pmu_cmn600_rd8(arg, nodeid, NODE_TYPE_XP, POR_DTM_PMEVCNT); 104 xpval >>= xpcntr * POR_DTM_PMEVCNT_CNTR_WIDTH; 105 xpval &= 0xffffUL; 106 return (dtcval | xpval); 107 } 108 109 static void 110 cmn600_pmu_writecntr(void *arg, u_int nodeid, u_int xpcntr, u_int dtccntr, 111 u_int width, uint64_t val) 112 { 113 int shift; 114 115 KASSERT(xpcntr < 4, ("[cmn600,%d] XP counter number %d is too big." 116 " Max: 3", __LINE__, xpcntr)); 117 KASSERT(dtccntr < 8, ("[cmn600,%d] Global counter number %d is too" 118 " big. Max: 7", __LINE__, dtccntr)); 119 120 if (width == 4) { 121 shift = (dtccntr & 1) ? POR_DT_PMEVCNT_ODDCNT_SHIFT : 122 POR_DT_PMEVCNT_EVENCNT_SHIFT; 123 pmu_cmn600_md8(arg, nodeid, NODE_TYPE_DTC, 124 POR_DT_PMEVCNT(dtccntr >> 1), 0xffffffffUL << shift, 125 ((val >> POR_DTM_PMEVCNT_CNTR_WIDTH) & 0xffffffff) << shift); 126 } else 127 pmu_cmn600_wr8(arg, nodeid, NODE_TYPE_DTC, 128 POR_DT_PMEVCNT(dtccntr & ~0x1), val >> 129 POR_DTM_PMEVCNT_CNTR_WIDTH); 130 131 shift = xpcntr * POR_DTM_PMEVCNT_CNTR_WIDTH; 132 val &= 0xffffUL; 133 pmu_cmn600_md8(arg, nodeid, NODE_TYPE_XP, POR_DTM_PMEVCNT, 134 0xffffUL << shift, val << shift); 135 } 136 137 #undef EVENCNTR 138 #undef ODDCNTR 139 140 /* 141 * read a pmc register 142 */ 143 static int 144 cmn600_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v) 145 { 146 int counter, local_counter, nodeid; 147 struct cmn600_descr *desc; 148 void *arg; 149 150 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 151 ("[cmn600,%d] illegal CPU value %d", __LINE__, cpu)); 152 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, 153 ri)); 154 155 counter = ri % CMN600_COUNTERS_N; 156 desc = cmn600desc(ri); 157 arg = desc->pd_rw_arg; 158 nodeid = pm->pm_md.pm_cmn600.pm_cmn600_nodeid; 159 local_counter = pm->pm_md.pm_cmn600.pm_cmn600_local_counter; 160 161 *v = cmn600_pmu_readcntr(arg, nodeid, local_counter, counter, 4); 162 PMCDBG3(MDP, REA, 2, "%s id=%d -> %jd", __func__, ri, *v); 163 164 return (0); 165 } 166 167 /* 168 * Write a pmc register. 169 */ 170 static int 171 cmn600_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v) 172 { 173 int counter, local_counter, nodeid; 174 struct cmn600_descr *desc; 175 void *arg; 176 177 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 178 ("[cmn600,%d] illegal CPU value %d", __LINE__, cpu)); 179 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, 180 ri)); 181 182 counter = ri % CMN600_COUNTERS_N; 183 desc = cmn600desc(ri); 184 arg = desc->pd_rw_arg; 185 nodeid = pm->pm_md.pm_cmn600.pm_cmn600_nodeid; 186 local_counter = pm->pm_md.pm_cmn600.pm_cmn600_local_counter; 187 188 KASSERT(pm != NULL, 189 ("[cmn600,%d] PMC not owned (cpu%d,pmc%d)", __LINE__, 190 cpu, ri)); 191 192 PMCDBG4(MDP, WRI, 1, "%s cpu=%d ri=%d v=%jx", __func__, cpu, ri, v); 193 194 cmn600_pmu_writecntr(arg, nodeid, local_counter, counter, 4, v); 195 return (0); 196 } 197 198 /* 199 * configure hardware pmc according to the configuration recorded in 200 * pmc 'pm'. 201 */ 202 static int 203 cmn600_config_pmc(int cpu, int ri, struct pmc *pm) 204 { 205 struct pmc_hw *phw; 206 207 PMCDBG4(MDP, CFG, 1, "%s cpu=%d ri=%d pm=%p", __func__, cpu, ri, pm); 208 209 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 210 ("[cmn600,%d] illegal CPU value %d", __LINE__, cpu)); 211 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, 212 ri)); 213 214 phw = cmn600desc(ri)->pd_phw; 215 216 KASSERT(pm == NULL || phw->phw_pmc == NULL, 217 ("[cmn600,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 218 __LINE__, pm, phw->phw_pmc)); 219 220 phw->phw_pmc = pm; 221 return (0); 222 } 223 224 /* 225 * Retrieve a configured PMC pointer from hardware state. 226 */ 227 static int 228 cmn600_get_config(int cpu, int ri, struct pmc **ppm) 229 { 230 231 *ppm = cmn600desc(ri)->pd_phw->phw_pmc; 232 233 return (0); 234 } 235 236 #define CASE_DN_VER_EVT(n, id) case PMC_EV_CMN600_PMU_ ## n: { *event = id; \ 237 return (0); } 238 static int 239 cmn600_map_ev2event(int ev, int rev, int *node_type, uint8_t *event) 240 { 241 if (ev < PMC_EV_CMN600_PMU_dn_rxreq_dvmop || 242 ev > PMC_EV_CMN600_PMU_rni_rdb_ord) 243 return (EINVAL); 244 if (ev <= PMC_EV_CMN600_PMU_dn_rxreq_trk_full) { 245 *node_type = NODE_TYPE_DVM; 246 if (rev < 0x200) { 247 switch (ev) { 248 CASE_DN_VER_EVT(dn_rxreq_dvmop, 1); 249 CASE_DN_VER_EVT(dn_rxreq_dvmsync, 2); 250 CASE_DN_VER_EVT(dn_rxreq_dvmop_vmid_filtered, 3); 251 CASE_DN_VER_EVT(dn_rxreq_retried, 4); 252 CASE_DN_VER_EVT(dn_rxreq_trk_occupancy, 5); 253 } 254 } else { 255 switch (ev) { 256 CASE_DN_VER_EVT(dn_rxreq_tlbi_dvmop, 0x01); 257 CASE_DN_VER_EVT(dn_rxreq_bpi_dvmop, 0x02); 258 CASE_DN_VER_EVT(dn_rxreq_pici_dvmop, 0x03); 259 CASE_DN_VER_EVT(dn_rxreq_vivi_dvmop, 0x04); 260 CASE_DN_VER_EVT(dn_rxreq_dvmsync, 0x05); 261 CASE_DN_VER_EVT(dn_rxreq_dvmop_vmid_filtered, 0x06); 262 CASE_DN_VER_EVT(dn_rxreq_dvmop_other_filtered, 0x07); 263 CASE_DN_VER_EVT(dn_rxreq_retried, 0x08); 264 CASE_DN_VER_EVT(dn_rxreq_snp_sent, 0x09); 265 CASE_DN_VER_EVT(dn_rxreq_snp_stalled, 0x0a); 266 CASE_DN_VER_EVT(dn_rxreq_trk_full, 0x0b); 267 CASE_DN_VER_EVT(dn_rxreq_trk_occupancy, 0x0c); 268 } 269 } 270 return (EINVAL); 271 } else if (ev <= PMC_EV_CMN600_PMU_hnf_snp_fwded) { 272 *node_type = NODE_TYPE_HN_F; 273 *event = ev - PMC_EV_CMN600_PMU_hnf_cache_miss; 274 return (0); 275 } else if (ev <= PMC_EV_CMN600_PMU_hni_pcie_serialization) { 276 *node_type = NODE_TYPE_HN_I; 277 *event = ev - PMC_EV_CMN600_PMU_hni_rrt_rd_occ_cnt_ovfl; 278 return (0); 279 } else if (ev <= PMC_EV_CMN600_PMU_xp_partial_dat_flit) { 280 *node_type = NODE_TYPE_XP; 281 *event = ev - PMC_EV_CMN600_PMU_xp_txflit_valid; 282 return (0); 283 } else if (ev <= PMC_EV_CMN600_PMU_sbsx_txrsp_stall) { 284 *node_type = NODE_TYPE_SBSX; 285 *event = ev - PMC_EV_CMN600_PMU_sbsx_rd_req; 286 return (0); 287 } else if (ev <= PMC_EV_CMN600_PMU_rnd_rdb_ord) { 288 *node_type = NODE_TYPE_RN_D; 289 *event = ev - PMC_EV_CMN600_PMU_rnd_s0_rdata_beats; 290 return (0); 291 } else if (ev <= PMC_EV_CMN600_PMU_rni_rdb_ord) { 292 *node_type = NODE_TYPE_RN_I; 293 *event = ev - PMC_EV_CMN600_PMU_rni_s0_rdata_beats; 294 return (0); 295 } else if (ev <= PMC_EV_CMN600_PMU_cxha_snphaz_occ) { 296 *node_type = NODE_TYPE_CXHA; 297 *event = ev - PMC_EV_CMN600_PMU_cxha_rddatbyp; 298 return (0); 299 } else if (ev <= PMC_EV_CMN600_PMU_cxra_ext_dat_stall) { 300 *node_type = NODE_TYPE_CXRA; 301 *event = ev - PMC_EV_CMN600_PMU_cxra_req_trk_occ; 302 return (0); 303 } else if (ev <= PMC_EV_CMN600_PMU_cxla_avg_latency_form_tx_tlp) { 304 *node_type = NODE_TYPE_CXLA; 305 *event = ev - PMC_EV_CMN600_PMU_cxla_rx_tlp_link0; 306 return (0); 307 } 308 return (EINVAL); 309 } 310 311 /* 312 * Check if a given allocation is feasible. 313 */ 314 315 static int 316 cmn600_allocate_pmc(int cpu, int ri, struct pmc *pm, 317 const struct pmc_op_pmcallocate *a) 318 { 319 struct cmn600_descr *desc; 320 const struct pmc_descr *pd; 321 uint64_t caps __unused; 322 int local_counter, node_type; 323 enum pmc_event pe; 324 void *arg; 325 uint8_t e; 326 int err; 327 328 (void) cpu; 329 330 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 331 ("[cmn600,%d] illegal CPU value %d", __LINE__, cpu)); 332 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, 333 ri)); 334 335 desc = cmn600desc(ri); 336 arg = desc->pd_rw_arg; 337 pd = &desc->pd_descr; 338 if (cmn600_pmcs[class_ri2unit(ri)].domain != pcpu_find(cpu)->pc_domain) 339 return (EINVAL); 340 341 /* check class match */ 342 if (pd->pd_class != a->pm_class) 343 return (EINVAL); 344 345 caps = pm->pm_caps; 346 347 PMCDBG3(MDP, ALL, 1, "%s ri=%d caps=0x%x", __func__, ri, caps); 348 349 pe = a->pm_ev; 350 err = cmn600_map_ev2event(pe, pmu_cmn600_rev(arg), &node_type, &e); 351 if (err != 0) 352 return (err); 353 err = pmu_cmn600_alloc_localpmc(arg, 354 a->pm_md.pm_cmn600.pma_cmn600_nodeid, node_type, &local_counter); 355 if (err != 0) 356 return (err); 357 358 pm->pm_md.pm_cmn600.pm_cmn600_config = 359 a->pm_md.pm_cmn600.pma_cmn600_config; 360 pm->pm_md.pm_cmn600.pm_cmn600_occupancy = 361 a->pm_md.pm_cmn600.pma_cmn600_occupancy; 362 desc->pd_nodeid = pm->pm_md.pm_cmn600.pm_cmn600_nodeid = 363 a->pm_md.pm_cmn600.pma_cmn600_nodeid; 364 desc->pd_node_type = pm->pm_md.pm_cmn600.pm_cmn600_node_type = 365 node_type; 366 pm->pm_md.pm_cmn600.pm_cmn600_event = e; 367 desc->pd_local_counter = pm->pm_md.pm_cmn600.pm_cmn600_local_counter = 368 local_counter; 369 370 return (0); 371 } 372 373 /* Release machine dependent state associated with a PMC. */ 374 375 static int 376 cmn600_release_pmc(int cpu, int ri, struct pmc *pmc) 377 { 378 struct cmn600_descr *desc; 379 struct pmc_hw *phw; 380 struct pmc *pm __diagused; 381 int err; 382 383 (void) pmc; 384 385 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 386 ("[cmn600,%d] illegal CPU value %d", __LINE__, cpu)); 387 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, 388 ri)); 389 390 desc = cmn600desc(ri); 391 phw = desc->pd_phw; 392 pm = phw->phw_pmc; 393 err = pmu_cmn600_free_localpmc(desc->pd_rw_arg, desc->pd_nodeid, 394 desc->pd_node_type, desc->pd_local_counter); 395 if (err != 0) 396 return (err); 397 398 KASSERT(pm == NULL, ("[cmn600,%d] PHW pmc %p non-NULL", __LINE__, pm)); 399 400 return (0); 401 } 402 403 static inline uint64_t 404 cmn600_encode_source(int node_type, int counter, int port, int sub) 405 { 406 407 /* Calculate pmevcnt0_input_sel based on list in Table 3-794. */ 408 if (node_type == NODE_TYPE_XP) 409 return (0x4 | counter); 410 411 return (((port + 1) << 4) | (sub << 2) | counter); 412 } 413 414 /* 415 * start a PMC. 416 */ 417 418 static int 419 cmn600_start_pmc(int cpu, int ri, struct pmc *pm) 420 { 421 int counter, local_counter, node_type, shift; 422 uint64_t config, occupancy, source, xp_pmucfg; 423 struct cmn600_descr *desc; 424 uint8_t event, port, sub; 425 uint16_t nodeid; 426 void *arg; 427 428 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 429 ("[cmn600,%d] illegal CPU value %d", __LINE__, cpu)); 430 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, 431 ri)); 432 433 counter = ri % CMN600_COUNTERS_N; 434 desc = cmn600desc(ri); 435 arg = desc->pd_rw_arg; 436 437 PMCDBG3(MDP, STA, 1, "%s cpu=%d ri=%d", __func__, cpu, ri); 438 439 config = pm->pm_md.pm_cmn600.pm_cmn600_config; 440 occupancy = pm->pm_md.pm_cmn600.pm_cmn600_occupancy; 441 node_type = pm->pm_md.pm_cmn600.pm_cmn600_node_type; 442 event = pm->pm_md.pm_cmn600.pm_cmn600_event; 443 nodeid = pm->pm_md.pm_cmn600.pm_cmn600_nodeid; 444 local_counter = pm->pm_md.pm_cmn600.pm_cmn600_local_counter; 445 port = (nodeid >> 2) & 1; 446 sub = nodeid & 3; 447 448 switch (node_type) { 449 case NODE_TYPE_DVM: 450 case NODE_TYPE_HN_F: 451 case NODE_TYPE_CXHA: 452 case NODE_TYPE_CXRA: 453 pmu_cmn600_md8(arg, nodeid, node_type, 454 CMN600_COMMON_PMU_EVENT_SEL, 455 CMN600_COMMON_PMU_EVENT_SEL_OCC_MASK, 456 occupancy << CMN600_COMMON_PMU_EVENT_SEL_OCC_SHIFT); 457 break; 458 case NODE_TYPE_XP: 459 /* Set PC and Interface.*/ 460 event |= config; 461 } 462 463 /* 464 * 5.5.1 Set up PMU counters 465 * 1. Ensure that the NIDEN input is asserted. HW side. */ 466 /* 2. Select event of target node for one of four outputs. */ 467 pmu_cmn600_md8(arg, nodeid, node_type, CMN600_COMMON_PMU_EVENT_SEL, 468 0xff << (local_counter * 8), 469 event << (local_counter * 8)); 470 471 xp_pmucfg = pmu_cmn600_rd8(arg, nodeid, NODE_TYPE_XP, 472 POR_DTM_PMU_CONFIG); 473 /* 474 * 3. configure XP to connect one of four target node outputs to local 475 * counter. 476 */ 477 source = cmn600_encode_source(node_type, local_counter, port, sub); 478 shift = (local_counter * POR_DTM_PMU_CONFIG_VCNT_INPUT_SEL_WIDTH) + 479 POR_DTM_PMU_CONFIG_VCNT_INPUT_SEL_SHIFT; 480 xp_pmucfg &= ~(0xffUL << shift); 481 xp_pmucfg |= source << shift; 482 483 /* 4. Pair with global counters A, B, C, ..., H. */ 484 shift = (local_counter * 4) + 16; 485 xp_pmucfg &= ~(0xfUL << shift); 486 xp_pmucfg |= counter << shift; 487 /* Enable pairing.*/ 488 xp_pmucfg |= 1 << (local_counter + 4); 489 490 /* 5. Combine local counters 0 with 1, 2 with 3 or all four. */ 491 xp_pmucfg &= ~0xeUL; 492 493 /* 6. Enable XP's PMU function. */ 494 xp_pmucfg |= POR_DTM_PMU_CONFIG_PMU_EN; 495 pmu_cmn600_wr8(arg, nodeid, NODE_TYPE_XP, POR_DTM_PMU_CONFIG, xp_pmucfg); 496 if (node_type == NODE_TYPE_CXLA) 497 pmu_cmn600_set8(arg, nodeid, NODE_TYPE_CXLA, 498 POR_CXG_RA_CFG_CTL, EN_CXLA_PMUCMD_PROP); 499 500 /* 7. Enable DTM. */ 501 pmu_cmn600_set8(arg, nodeid, NODE_TYPE_XP, POR_DTM_CONTROL, 502 POR_DTM_CONTROL_DTM_ENABLE); 503 504 /* 8. Reset grouping of global counters. Use 32 bits. */ 505 pmu_cmn600_clr8(arg, nodeid, NODE_TYPE_DTC, POR_DT_PMCR, 506 POR_DT_PMCR_CNTCFG_MASK); 507 508 /* 9. Enable DTC. */ 509 pmu_cmn600_set8(arg, nodeid, NODE_TYPE_DTC, POR_DT_DTC_CTL, 510 POR_DT_DTC_CTL_DT_EN); 511 512 /* 10. Enable Overflow Interrupt. */ 513 pmu_cmn600_set8(arg, nodeid, NODE_TYPE_DTC, POR_DT_PMCR, 514 POR_DT_PMCR_OVFL_INTR_EN); 515 516 /* 11. Run PMC. */ 517 pmu_cmn600_set8(arg, nodeid, NODE_TYPE_DTC, POR_DT_PMCR, 518 POR_DT_PMCR_PMU_EN); 519 520 return (0); 521 } 522 523 /* 524 * Stop a PMC. 525 */ 526 527 static int 528 cmn600_stop_pmc(int cpu, int ri, struct pmc *pm) 529 { 530 struct cmn600_descr *desc; 531 int local_counter; 532 uint64_t val; 533 534 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 535 ("[cmn600,%d] illegal CPU value %d", __LINE__, cpu)); 536 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, 537 ri)); 538 539 desc = cmn600desc(ri); 540 541 PMCDBG2(MDP, STO, 1, "%s ri=%d", __func__, ri); 542 543 /* Disable pairing. */ 544 local_counter = pm->pm_md.pm_cmn600.pm_cmn600_local_counter; 545 pmu_cmn600_clr8(desc->pd_rw_arg, pm->pm_md.pm_cmn600.pm_cmn600_nodeid, 546 NODE_TYPE_XP, POR_DTM_PMU_CONFIG, (1 << (local_counter + 4))); 547 548 /* Shutdown XP's DTM function if no paired counters. */ 549 val = pmu_cmn600_rd8(desc->pd_rw_arg, 550 pm->pm_md.pm_cmn600.pm_cmn600_nodeid, NODE_TYPE_XP, 551 POR_DTM_PMU_CONFIG); 552 if ((val & 0xf0) == 0) 553 pmu_cmn600_clr8(desc->pd_rw_arg, 554 pm->pm_md.pm_cmn600.pm_cmn600_nodeid, NODE_TYPE_XP, 555 POR_DTM_PMU_CONFIG, POR_DTM_CONTROL_DTM_ENABLE); 556 557 return (0); 558 } 559 560 /* 561 * describe a PMC 562 */ 563 static int 564 cmn600_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 565 { 566 struct pmc_descr *pd; 567 struct pmc_hw *phw; 568 569 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 570 ("[cmn600,%d] illegal CPU %d", __LINE__, cpu)); 571 KASSERT(ri >= 0, ("[cmn600,%d] row-index %d out of range", __LINE__, 572 ri)); 573 574 phw = cmn600desc(ri)->pd_phw; 575 pd = &cmn600desc(ri)->pd_descr; 576 577 strlcpy(pi->pm_name, pd->pd_name, sizeof(pi->pm_name)); 578 pi->pm_class = pd->pd_class; 579 580 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 581 pi->pm_enabled = TRUE; 582 *ppmc = phw->phw_pmc; 583 } else { 584 pi->pm_enabled = FALSE; 585 *ppmc = NULL; 586 } 587 588 return (0); 589 } 590 591 /* 592 * processor dependent initialization. 593 */ 594 595 static int 596 cmn600_pcpu_init(struct pmc_mdep *md, int cpu) 597 { 598 int first_ri, n, npmc; 599 struct pmc_hw *phw; 600 struct pmc_cpu *pc; 601 int mdep_class; 602 603 mdep_class = PMC_MDEP_CLASS_INDEX_CMN600; 604 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 605 ("[cmn600,%d] insane cpu number %d", __LINE__, cpu)); 606 607 PMCDBG1(MDP, INI, 1, "cmn600-init cpu=%d", cpu); 608 609 /* 610 * Set the content of the hardware descriptors to a known 611 * state and initialize pointers in the MI per-cpu descriptor. 612 */ 613 614 pc = pmc_pcpu[cpu]; 615 first_ri = md->pmd_classdep[mdep_class].pcd_ri; 616 npmc = md->pmd_classdep[mdep_class].pcd_num; 617 618 for (n = 0; n < npmc; n++, phw++) { 619 phw = cmn600desc(n)->pd_phw; 620 phw->phw_state = PMC_PHW_CPU_TO_STATE(cpu) | 621 PMC_PHW_INDEX_TO_STATE(n); 622 /* Set enabled only if unit present. */ 623 if (cmn600_pmcs[class_ri2unit(n)].arg != NULL) 624 phw->phw_state |= PMC_PHW_FLAG_IS_ENABLED; 625 phw->phw_pmc = NULL; 626 pc->pc_hwpmcs[n + first_ri] = phw; 627 } 628 return (0); 629 } 630 631 /* 632 * processor dependent cleanup prior to the KLD 633 * being unloaded 634 */ 635 636 static int 637 cmn600_pcpu_fini(struct pmc_mdep *md, int cpu) 638 { 639 640 return (0); 641 } 642 643 static int 644 cmn600_pmu_intr(struct trapframe *tf, int unit, int i) 645 { 646 struct pmc_cpu *pc __diagused; 647 struct pmc_hw *phw; 648 struct pmc *pm; 649 int error, cpu, ri; 650 651 ri = i + unit * CMN600_COUNTERS_N; 652 cpu = curcpu; 653 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 654 ("[cmn600,%d] CPU %d out of range", __LINE__, cpu)); 655 pc = pmc_pcpu[cpu]; 656 KASSERT(pc != NULL, ("pc != NULL")); 657 658 phw = cmn600desc(ri)->pd_phw; 659 KASSERT(phw != NULL, ("phw != NULL")); 660 pm = phw->phw_pmc; 661 if (pm == NULL) 662 return (0); 663 664 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 665 /* Always CPU0. */ 666 pm->pm_pcpu_state[0].pps_overflowcnt += 1; 667 return (0); 668 } 669 670 if (pm->pm_state != PMC_STATE_RUNNING) 671 return (0); 672 673 error = pmc_process_interrupt(PMC_HR, pm, tf); 674 if (error) 675 cmn600_stop_pmc(cpu, ri, pm); 676 677 /* Reload sampling count */ 678 cmn600_write_pmc(cpu, ri, pm, pm->pm_sc.pm_reloadcount); 679 680 return (0); 681 } 682 683 /* 684 * Initialize ourselves. 685 */ 686 static int 687 cmn600_init_pmc_units(void) 688 { 689 int i; 690 691 if (cmn600_units > 0) { /* Already initialized. */ 692 return (0); 693 } 694 695 cmn600_units = cmn600_pmc_nunits(); 696 if (cmn600_units == 0) 697 return (ENOENT); 698 699 for (i = 0; i < cmn600_units; i++) { 700 if (cmn600_pmc_getunit(i, &cmn600_pmcs[i].arg, 701 &cmn600_pmcs[i].domain) != 0) 702 cmn600_pmcs[i].arg = NULL; 703 } 704 return (0); 705 } 706 707 int 708 pmc_cmn600_nclasses(void) 709 { 710 711 if (cmn600_pmc_nunits() > 0) 712 return (1); 713 return (0); 714 } 715 716 int 717 pmc_cmn600_initialize(struct pmc_mdep *md) 718 { 719 struct pmc_classdep *pcd; 720 int i, npmc, unit; 721 722 cmn600_init_pmc_units(); 723 KASSERT(md != NULL, ("[cmn600,%d] md is NULL", __LINE__)); 724 KASSERT(cmn600_units < CMN600_UNIT_MAX, 725 ("[cmn600,%d] cmn600_units too big", __LINE__)); 726 727 PMCDBG0(MDP,INI,1, "cmn600-initialize"); 728 729 npmc = CMN600_COUNTERS_N * cmn600_units; 730 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_CMN600]; 731 732 pcd->pcd_caps = PMC_CAP_SYSTEM | PMC_CAP_READ | 733 PMC_CAP_WRITE | PMC_CAP_QUALIFIER | PMC_CAP_INTERRUPT | 734 PMC_CAP_DOMWIDE; 735 pcd->pcd_class = PMC_CLASS_CMN600_PMU; 736 pcd->pcd_num = npmc; 737 pcd->pcd_ri = md->pmd_npmc; 738 pcd->pcd_width = 48; 739 740 pcd->pcd_allocate_pmc = cmn600_allocate_pmc; 741 pcd->pcd_config_pmc = cmn600_config_pmc; 742 pcd->pcd_describe = cmn600_describe; 743 pcd->pcd_get_config = cmn600_get_config; 744 pcd->pcd_get_msr = NULL; 745 pcd->pcd_pcpu_fini = cmn600_pcpu_fini; 746 pcd->pcd_pcpu_init = cmn600_pcpu_init; 747 pcd->pcd_read_pmc = cmn600_read_pmc; 748 pcd->pcd_release_pmc = cmn600_release_pmc; 749 pcd->pcd_start_pmc = cmn600_start_pmc; 750 pcd->pcd_stop_pmc = cmn600_stop_pmc; 751 pcd->pcd_write_pmc = cmn600_write_pmc; 752 753 md->pmd_npmc += npmc; 754 cmn600_pmcdesc = malloc(sizeof(struct cmn600_descr *) * npmc * 755 CMN600_PMU_DEFAULT_UNITS_N, M_PMC, M_WAITOK|M_ZERO); 756 for (i = 0; i < npmc; i++) { 757 cmn600_pmcdesc[i] = malloc(sizeof(struct cmn600_descr), M_PMC, 758 M_WAITOK|M_ZERO); 759 760 unit = i / CMN600_COUNTERS_N; 761 KASSERT(unit >= 0, ("unit >= 0")); 762 KASSERT(cmn600_pmcs[unit].arg != NULL, ("arg != NULL")); 763 764 cmn600_pmcdesc[i]->pd_rw_arg = cmn600_pmcs[unit].arg; 765 cmn600_pmcdesc[i]->pd_descr.pd_class = 766 PMC_CLASS_CMN600_PMU; 767 cmn600_pmcdesc[i]->pd_descr.pd_caps = pcd->pcd_caps; 768 cmn600_pmcdesc[i]->pd_phw = (struct pmc_hw *)malloc( 769 sizeof(struct pmc_hw), M_PMC, M_WAITOK|M_ZERO); 770 snprintf(cmn600_pmcdesc[i]->pd_descr.pd_name, 63, 771 "CMN600_%d", i); 772 cmn600_pmu_intr_cb(cmn600_pmcs[unit].arg, cmn600_pmu_intr); 773 } 774 775 return (0); 776 } 777 778 void 779 pmc_cmn600_finalize(struct pmc_mdep *md) 780 { 781 struct pmc_classdep *pcd; 782 int i, npmc; 783 784 KASSERT(md->pmd_classdep[PMC_MDEP_CLASS_INDEX_CMN600].pcd_class == 785 PMC_CLASS_CMN600_PMU, ("[cmn600,%d] pmc class mismatch", 786 __LINE__)); 787 788 pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_CMN600]; 789 790 npmc = pcd->pcd_num; 791 for (i = 0; i < npmc; i++) { 792 free(cmn600_pmcdesc[i]->pd_phw, M_PMC); 793 free(cmn600_pmcdesc[i], M_PMC); 794 } 795 free(cmn600_pmcdesc, M_PMC); 796 cmn600_pmcdesc = NULL; 797 } 798 799 MODULE_DEPEND(pmc, cmn600, 1, 1, 1); 800