1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 39 #include <machine/pmc_mdep.h> 40 #include <machine/cpu.h> 41 42 static int armv7_npmcs; 43 44 struct armv7_event_code_map { 45 enum pmc_event pe_ev; 46 uint8_t pe_code; 47 }; 48 49 #define PMC_EV_CPU_CYCLES 0xFF 50 51 /* 52 * Per-processor information. 53 */ 54 struct armv7_cpu { 55 struct pmc_hw *pc_armv7pmcs; 56 }; 57 58 static struct armv7_cpu **armv7_pcpu; 59 60 /* 61 * Interrupt Enable Set Register 62 */ 63 static __inline void 64 armv7_interrupt_enable(uint32_t pmc) 65 { 66 uint32_t reg; 67 68 reg = (1 << pmc); 69 cp15_pminten_set(reg); 70 } 71 72 /* 73 * Interrupt Clear Set Register 74 */ 75 static __inline void 76 armv7_interrupt_disable(uint32_t pmc) 77 { 78 uint32_t reg; 79 80 reg = (1 << pmc); 81 cp15_pminten_clr(reg); 82 } 83 84 /* 85 * Counter Set Enable Register 86 */ 87 static __inline void 88 armv7_counter_enable(unsigned int pmc) 89 { 90 uint32_t reg; 91 92 reg = (1 << pmc); 93 cp15_pmcnten_set(reg); 94 } 95 96 /* 97 * Counter Clear Enable Register 98 */ 99 static __inline void 100 armv7_counter_disable(unsigned int pmc) 101 { 102 uint32_t reg; 103 104 reg = (1 << pmc); 105 cp15_pmcnten_clr(reg); 106 } 107 108 /* 109 * Performance Count Register N 110 */ 111 static uint32_t 112 armv7_pmcn_read(unsigned int pmc, uint32_t evsel) 113 { 114 115 if (evsel == PMC_EV_CPU_CYCLES) { 116 return ((uint32_t)cp15_pmccntr_get()); 117 } 118 119 KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 120 121 cp15_pmselr_set(pmc); 122 return (cp15_pmxevcntr_get()); 123 } 124 125 static uint32_t 126 armv7_pmcn_write(unsigned int pmc, uint32_t reg) 127 { 128 129 KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 130 131 cp15_pmselr_set(pmc); 132 cp15_pmxevcntr_set(reg); 133 134 return (reg); 135 } 136 137 static int 138 armv7_allocate_pmc(int cpu, int ri, struct pmc *pm, 139 const struct pmc_op_pmcallocate *a) 140 { 141 enum pmc_event pe; 142 uint32_t config; 143 144 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 145 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 146 KASSERT(ri >= 0 && ri < armv7_npmcs, 147 ("[armv7,%d] illegal row index %d", __LINE__, ri)); 148 149 if (a->pm_class != PMC_CLASS_ARMV7) 150 return (EINVAL); 151 pe = a->pm_ev; 152 153 config = (pe & EVENT_ID_MASK); 154 pm->pm_md.pm_armv7.pm_armv7_evsel = config; 155 156 PMCDBG2(MDP, ALL, 2, "armv7-allocate ri=%d -> config=0x%x", ri, config); 157 158 return 0; 159 } 160 161 162 static int 163 armv7_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v) 164 { 165 pmc_value_t tmp; 166 register_t s; 167 u_int reg; 168 169 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 170 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 171 KASSERT(ri >= 0 && ri < armv7_npmcs, 172 ("[armv7,%d] illegal row index %d", __LINE__, ri)); 173 174 s = intr_disable(); 175 tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel); 176 177 /* Check if counter has overflowed */ 178 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) 179 reg = (1u << 31); 180 else 181 reg = (1u << ri); 182 183 if ((cp15_pmovsr_get() & reg) != 0) { 184 /* Clear Overflow Flag */ 185 cp15_pmovsr_set(reg); 186 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 187 188 /* Reread counter in case we raced. */ 189 tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel); 190 } 191 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 192 intr_restore(s); 193 194 PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp); 195 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 196 /* 197 * Clamp value to 0 if the counter just overflowed, 198 * otherwise the returned reload count would wrap to a 199 * huge value. 200 */ 201 if ((tmp & (1ull << 63)) == 0) 202 tmp = 0; 203 else 204 tmp = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 205 } 206 *v = tmp; 207 208 return 0; 209 } 210 211 static int 212 armv7_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v) 213 { 214 215 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 216 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 217 KASSERT(ri >= 0 && ri < armv7_npmcs, 218 ("[armv7,%d] illegal row-index %d", __LINE__, ri)); 219 220 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 221 v = ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 222 223 PMCDBG3(MDP, WRI, 1, "armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v); 224 225 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 226 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) 227 cp15_pmccntr_set(v); 228 else 229 armv7_pmcn_write(ri, v); 230 231 return 0; 232 } 233 234 static int 235 armv7_config_pmc(int cpu, int ri, struct pmc *pm) 236 { 237 struct pmc_hw *phw; 238 239 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 240 241 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 242 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 243 KASSERT(ri >= 0 && ri < armv7_npmcs, 244 ("[armv7,%d] illegal row-index %d", __LINE__, ri)); 245 246 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 247 248 KASSERT(pm == NULL || phw->phw_pmc == NULL, 249 ("[armv7,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 250 __LINE__, pm, phw->phw_pmc)); 251 252 phw->phw_pmc = pm; 253 254 return 0; 255 } 256 257 static int 258 armv7_start_pmc(int cpu, int ri, struct pmc *pm) 259 { 260 uint32_t config; 261 262 config = pm->pm_md.pm_armv7.pm_armv7_evsel; 263 264 /* 265 * Configure the event selection. 266 */ 267 if (config != PMC_EV_CPU_CYCLES) { 268 cp15_pmselr_set(ri); 269 cp15_pmxevtyper_set(config); 270 } else 271 ri = 31; 272 273 /* 274 * Enable the PMC. 275 */ 276 armv7_interrupt_enable(ri); 277 armv7_counter_enable(ri); 278 279 return 0; 280 } 281 282 static int 283 armv7_stop_pmc(int cpu, int ri, struct pmc *pm) 284 { 285 uint32_t config; 286 287 config = pm->pm_md.pm_armv7.pm_armv7_evsel; 288 if (config == PMC_EV_CPU_CYCLES) 289 ri = 31; 290 291 /* 292 * Disable the PMCs. 293 */ 294 armv7_counter_disable(ri); 295 armv7_interrupt_disable(ri); 296 297 return 0; 298 } 299 300 static int 301 armv7_release_pmc(int cpu, int ri, struct pmc *pmc) 302 { 303 struct pmc_hw *phw __diagused; 304 305 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 306 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 307 KASSERT(ri >= 0 && ri < armv7_npmcs, 308 ("[armv7,%d] illegal row-index %d", __LINE__, ri)); 309 310 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 311 KASSERT(phw->phw_pmc == NULL, 312 ("[armv7,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 313 314 return 0; 315 } 316 317 static int 318 armv7_intr(struct trapframe *tf) 319 { 320 int retval, ri; 321 struct pmc *pm; 322 int error; 323 int reg, cpu; 324 325 cpu = curcpu; 326 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 327 ("[armv7,%d] CPU %d out of range", __LINE__, cpu)); 328 329 retval = 0; 330 331 for (ri = 0; ri < armv7_npmcs; ri++) { 332 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 333 if (pm == NULL) 334 continue; 335 336 /* Check if counter has overflowed */ 337 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) 338 reg = (1u << 31); 339 else 340 reg = (1u << ri); 341 342 if ((cp15_pmovsr_get() & reg) == 0) { 343 continue; 344 } 345 346 /* Clear Overflow Flag */ 347 cp15_pmovsr_set(reg); 348 349 retval = 1; /* Found an interrupting PMC. */ 350 351 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 352 353 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 354 continue; 355 356 if (pm->pm_state != PMC_STATE_RUNNING) 357 continue; 358 359 error = pmc_process_interrupt(PMC_HR, pm, tf); 360 if (error) 361 armv7_stop_pmc(cpu, ri, pm); 362 363 /* Reload sampling count */ 364 armv7_write_pmc(cpu, ri, pm, pm->pm_sc.pm_reloadcount); 365 } 366 367 return (retval); 368 } 369 370 static int 371 armv7_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 372 { 373 struct pmc_hw *phw; 374 375 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 376 ("[armv7,%d], illegal CPU %d", __LINE__, cpu)); 377 KASSERT(ri >= 0 && ri < armv7_npmcs, 378 ("[armv7,%d] row-index %d out of range", __LINE__, ri)); 379 380 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 381 382 snprintf(pi->pm_name, sizeof(pi->pm_name), "ARMV7-%d", ri); 383 pi->pm_class = PMC_CLASS_ARMV7; 384 385 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 386 pi->pm_enabled = TRUE; 387 *ppmc = phw->phw_pmc; 388 } else { 389 pi->pm_enabled = FALSE; 390 *ppmc = NULL; 391 } 392 393 return (0); 394 } 395 396 static int 397 armv7_get_config(int cpu, int ri, struct pmc **ppm) 398 { 399 400 *ppm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 401 402 return 0; 403 } 404 405 static int 406 armv7_pcpu_init(struct pmc_mdep *md, int cpu) 407 { 408 struct armv7_cpu *pac; 409 struct pmc_hw *phw; 410 struct pmc_cpu *pc; 411 uint32_t pmnc; 412 int first_ri; 413 int i; 414 415 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 416 ("[armv7,%d] wrong cpu number %d", __LINE__, cpu)); 417 PMCDBG1(MDP, INI, 1, "armv7-init cpu=%d", cpu); 418 419 armv7_pcpu[cpu] = pac = malloc(sizeof(struct armv7_cpu), M_PMC, 420 M_WAITOK|M_ZERO); 421 422 pac->pc_armv7pmcs = malloc(sizeof(struct pmc_hw) * armv7_npmcs, 423 M_PMC, M_WAITOK|M_ZERO); 424 pc = pmc_pcpu[cpu]; 425 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7].pcd_ri; 426 KASSERT(pc != NULL, ("[armv7,%d] NULL per-cpu pointer", __LINE__)); 427 428 for (i = 0, phw = pac->pc_armv7pmcs; i < armv7_npmcs; i++, phw++) { 429 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 430 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 431 phw->phw_pmc = NULL; 432 pc->pc_hwpmcs[i + first_ri] = phw; 433 } 434 435 pmnc = 0xffffffff; 436 cp15_pmcnten_clr(pmnc); 437 cp15_pminten_clr(pmnc); 438 cp15_pmovsr_set(pmnc); 439 440 /* Enable unit */ 441 pmnc = cp15_pmcr_get(); 442 pmnc |= ARMV7_PMNC_ENABLE; 443 cp15_pmcr_set(pmnc); 444 445 return 0; 446 } 447 448 static int 449 armv7_pcpu_fini(struct pmc_mdep *md, int cpu) 450 { 451 uint32_t pmnc; 452 453 pmnc = cp15_pmcr_get(); 454 pmnc &= ~ARMV7_PMNC_ENABLE; 455 cp15_pmcr_set(pmnc); 456 457 pmnc = 0xffffffff; 458 cp15_pmcnten_clr(pmnc); 459 cp15_pminten_clr(pmnc); 460 cp15_pmovsr_set(pmnc); 461 462 return 0; 463 } 464 465 struct pmc_mdep * 466 pmc_armv7_initialize(void) 467 { 468 struct pmc_mdep *pmc_mdep; 469 struct pmc_classdep *pcd; 470 int idcode; 471 int reg; 472 473 reg = cp15_pmcr_get(); 474 armv7_npmcs = (reg >> ARMV7_PMNC_N_SHIFT) & \ 475 ARMV7_PMNC_N_MASK; 476 idcode = (reg & ARMV7_IDCODE_MASK) >> ARMV7_IDCODE_SHIFT; 477 478 PMCDBG1(MDP, INI, 1, "armv7-init npmcs=%d", armv7_npmcs); 479 480 /* 481 * Allocate space for pointers to PMC HW descriptors and for 482 * the MDEP structure used by MI code. 483 */ 484 armv7_pcpu = malloc(sizeof(struct armv7_cpu *) * pmc_cpu_max(), 485 M_PMC, M_WAITOK | M_ZERO); 486 487 /* Just one class */ 488 pmc_mdep = pmc_mdep_alloc(1); 489 490 switch (idcode) { 491 case ARMV7_IDCODE_CORTEX_A9: 492 pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A9; 493 break; 494 default: 495 case ARMV7_IDCODE_CORTEX_A8: 496 /* 497 * On A8 we implemented common events only, 498 * so use it for the rest of machines. 499 */ 500 pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A8; 501 break; 502 } 503 504 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7]; 505 pcd->pcd_caps = ARMV7_PMC_CAPS; 506 pcd->pcd_class = PMC_CLASS_ARMV7; 507 pcd->pcd_num = armv7_npmcs; 508 pcd->pcd_ri = pmc_mdep->pmd_npmc; 509 pcd->pcd_width = 32; 510 511 pcd->pcd_allocate_pmc = armv7_allocate_pmc; 512 pcd->pcd_config_pmc = armv7_config_pmc; 513 pcd->pcd_pcpu_fini = armv7_pcpu_fini; 514 pcd->pcd_pcpu_init = armv7_pcpu_init; 515 pcd->pcd_describe = armv7_describe; 516 pcd->pcd_get_config = armv7_get_config; 517 pcd->pcd_read_pmc = armv7_read_pmc; 518 pcd->pcd_release_pmc = armv7_release_pmc; 519 pcd->pcd_start_pmc = armv7_start_pmc; 520 pcd->pcd_stop_pmc = armv7_stop_pmc; 521 pcd->pcd_write_pmc = armv7_write_pmc; 522 523 pmc_mdep->pmd_intr = armv7_intr; 524 pmc_mdep->pmd_npmc += armv7_npmcs; 525 526 return (pmc_mdep); 527 } 528 529 void 530 pmc_armv7_finalize(struct pmc_mdep *md) 531 { 532 533 } 534