1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/pmc.h> 37 #include <sys/pmckern.h> 38 39 #include <machine/pmc_mdep.h> 40 #include <machine/cpu.h> 41 42 static int armv7_npmcs; 43 44 struct armv7_event_code_map { 45 enum pmc_event pe_ev; 46 uint8_t pe_code; 47 }; 48 49 #define PMC_EV_CPU_CYCLES 0xFF 50 51 /* 52 * Per-processor information. 53 */ 54 struct armv7_cpu { 55 struct pmc_hw *pc_armv7pmcs; 56 }; 57 58 static struct armv7_cpu **armv7_pcpu; 59 60 /* 61 * Interrupt Enable Set Register 62 */ 63 static __inline void 64 armv7_interrupt_enable(uint32_t pmc) 65 { 66 uint32_t reg; 67 68 reg = (1 << pmc); 69 cp15_pminten_set(reg); 70 } 71 72 /* 73 * Interrupt Clear Set Register 74 */ 75 static __inline void 76 armv7_interrupt_disable(uint32_t pmc) 77 { 78 uint32_t reg; 79 80 reg = (1 << pmc); 81 cp15_pminten_clr(reg); 82 } 83 84 /* 85 * Counter Set Enable Register 86 */ 87 static __inline void 88 armv7_counter_enable(unsigned int pmc) 89 { 90 uint32_t reg; 91 92 reg = (1 << pmc); 93 cp15_pmcnten_set(reg); 94 } 95 96 /* 97 * Counter Clear Enable Register 98 */ 99 static __inline void 100 armv7_counter_disable(unsigned int pmc) 101 { 102 uint32_t reg; 103 104 reg = (1 << pmc); 105 cp15_pmcnten_clr(reg); 106 } 107 108 /* 109 * Performance Count Register N 110 */ 111 static uint32_t 112 armv7_pmcn_read(unsigned int pmc, uint32_t evsel) 113 { 114 115 if (evsel == PMC_EV_CPU_CYCLES) { 116 return ((uint32_t)cp15_pmccntr_get()); 117 } 118 119 KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 120 121 cp15_pmselr_set(pmc); 122 return (cp15_pmxevcntr_get()); 123 } 124 125 static uint32_t 126 armv7_pmcn_write(unsigned int pmc, uint32_t reg) 127 { 128 129 KASSERT(pmc < armv7_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 130 131 cp15_pmselr_set(pmc); 132 cp15_pmxevcntr_set(reg); 133 134 return (reg); 135 } 136 137 static int 138 armv7_allocate_pmc(int cpu, int ri, struct pmc *pm, 139 const struct pmc_op_pmcallocate *a) 140 { 141 struct armv7_cpu *pac; 142 enum pmc_event pe; 143 uint32_t config; 144 145 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 146 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 147 KASSERT(ri >= 0 && ri < armv7_npmcs, 148 ("[armv7,%d] illegal row index %d", __LINE__, ri)); 149 150 pac = armv7_pcpu[cpu]; 151 152 if (a->pm_class != PMC_CLASS_ARMV7) 153 return (EINVAL); 154 pe = a->pm_ev; 155 156 config = (pe & EVENT_ID_MASK); 157 pm->pm_md.pm_armv7.pm_armv7_evsel = config; 158 159 PMCDBG2(MDP, ALL, 2, "armv7-allocate ri=%d -> config=0x%x", ri, config); 160 161 return 0; 162 } 163 164 165 static int 166 armv7_read_pmc(int cpu, int ri, pmc_value_t *v) 167 { 168 pmc_value_t tmp; 169 struct pmc *pm; 170 register_t s; 171 u_int reg; 172 173 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 174 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 175 KASSERT(ri >= 0 && ri < armv7_npmcs, 176 ("[armv7,%d] illegal row index %d", __LINE__, ri)); 177 178 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 179 180 s = intr_disable(); 181 tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel); 182 183 /* Check if counter has overflowed */ 184 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) 185 reg = (1u << 31); 186 else 187 reg = (1u << ri); 188 189 if ((cp15_pmovsr_get() & reg) != 0) { 190 /* Clear Overflow Flag */ 191 cp15_pmovsr_set(reg); 192 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 193 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 194 195 /* Reread counter in case we raced. */ 196 tmp = armv7_pmcn_read(ri, pm->pm_md.pm_armv7.pm_armv7_evsel); 197 } 198 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 199 intr_restore(s); 200 201 PMCDBG2(MDP, REA, 2, "armv7-read id=%d -> %jd", ri, tmp); 202 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 203 *v = ARMV7_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 204 else 205 *v = tmp; 206 207 return 0; 208 } 209 210 static int 211 armv7_write_pmc(int cpu, int ri, pmc_value_t v) 212 { 213 struct pmc *pm; 214 215 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 216 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 217 KASSERT(ri >= 0 && ri < armv7_npmcs, 218 ("[armv7,%d] illegal row-index %d", __LINE__, ri)); 219 220 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 221 222 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 223 v = ARMV7_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 224 225 PMCDBG3(MDP, WRI, 1, "armv7-write cpu=%d ri=%d v=%jx", cpu, ri, v); 226 227 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 228 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) 229 cp15_pmccntr_set(v); 230 else 231 armv7_pmcn_write(ri, v); 232 233 return 0; 234 } 235 236 static int 237 armv7_config_pmc(int cpu, int ri, struct pmc *pm) 238 { 239 struct pmc_hw *phw; 240 241 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 242 243 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 244 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 245 KASSERT(ri >= 0 && ri < armv7_npmcs, 246 ("[armv7,%d] illegal row-index %d", __LINE__, ri)); 247 248 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 249 250 KASSERT(pm == NULL || phw->phw_pmc == NULL, 251 ("[armv7,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 252 __LINE__, pm, phw->phw_pmc)); 253 254 phw->phw_pmc = pm; 255 256 return 0; 257 } 258 259 static int 260 armv7_start_pmc(int cpu, int ri) 261 { 262 struct pmc_hw *phw; 263 uint32_t config; 264 struct pmc *pm; 265 266 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 267 pm = phw->phw_pmc; 268 config = pm->pm_md.pm_armv7.pm_armv7_evsel; 269 270 /* 271 * Configure the event selection. 272 */ 273 if (config != PMC_EV_CPU_CYCLES) { 274 cp15_pmselr_set(ri); 275 cp15_pmxevtyper_set(config); 276 } else 277 ri = 31; 278 279 /* 280 * Enable the PMC. 281 */ 282 armv7_interrupt_enable(ri); 283 armv7_counter_enable(ri); 284 285 return 0; 286 } 287 288 static int 289 armv7_stop_pmc(int cpu, int ri) 290 { 291 struct pmc_hw *phw; 292 struct pmc *pm; 293 uint32_t config; 294 295 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 296 pm = phw->phw_pmc; 297 config = pm->pm_md.pm_armv7.pm_armv7_evsel; 298 if (config == PMC_EV_CPU_CYCLES) 299 ri = 31; 300 301 /* 302 * Disable the PMCs. 303 */ 304 armv7_counter_disable(ri); 305 armv7_interrupt_disable(ri); 306 307 return 0; 308 } 309 310 static int 311 armv7_release_pmc(int cpu, int ri, struct pmc *pmc) 312 { 313 struct pmc_hw *phw; 314 315 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 316 ("[armv7,%d] illegal CPU value %d", __LINE__, cpu)); 317 KASSERT(ri >= 0 && ri < armv7_npmcs, 318 ("[armv7,%d] illegal row-index %d", __LINE__, ri)); 319 320 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 321 KASSERT(phw->phw_pmc == NULL, 322 ("[armv7,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 323 324 return 0; 325 } 326 327 static int 328 armv7_intr(struct trapframe *tf) 329 { 330 struct armv7_cpu *pc; 331 int retval, ri; 332 struct pmc *pm; 333 int error; 334 int reg, cpu; 335 336 cpu = curcpu; 337 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 338 ("[armv7,%d] CPU %d out of range", __LINE__, cpu)); 339 340 retval = 0; 341 pc = armv7_pcpu[cpu]; 342 343 for (ri = 0; ri < armv7_npmcs; ri++) { 344 pm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 345 if (pm == NULL) 346 continue; 347 348 /* Check if counter has overflowed */ 349 if (pm->pm_md.pm_armv7.pm_armv7_evsel == PMC_EV_CPU_CYCLES) 350 reg = (1u << 31); 351 else 352 reg = (1u << ri); 353 354 if ((cp15_pmovsr_get() & reg) == 0) { 355 continue; 356 } 357 358 /* Clear Overflow Flag */ 359 cp15_pmovsr_set(reg); 360 361 retval = 1; /* Found an interrupting PMC. */ 362 363 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 364 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 365 continue; 366 } 367 if (pm->pm_state != PMC_STATE_RUNNING) 368 continue; 369 370 error = pmc_process_interrupt(PMC_HR, pm, tf); 371 if (error) 372 armv7_stop_pmc(cpu, ri); 373 374 /* Reload sampling count */ 375 armv7_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount); 376 } 377 378 return (retval); 379 } 380 381 static int 382 armv7_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 383 { 384 char armv7_name[PMC_NAME_MAX]; 385 struct pmc_hw *phw; 386 int error; 387 388 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 389 ("[armv7,%d], illegal CPU %d", __LINE__, cpu)); 390 KASSERT(ri >= 0 && ri < armv7_npmcs, 391 ("[armv7,%d] row-index %d out of range", __LINE__, ri)); 392 393 phw = &armv7_pcpu[cpu]->pc_armv7pmcs[ri]; 394 snprintf(armv7_name, sizeof(armv7_name), "ARMV7-%d", ri); 395 if ((error = copystr(armv7_name, pi->pm_name, PMC_NAME_MAX, 396 NULL)) != 0) 397 return error; 398 pi->pm_class = PMC_CLASS_ARMV7; 399 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 400 pi->pm_enabled = TRUE; 401 *ppmc = phw->phw_pmc; 402 } else { 403 pi->pm_enabled = FALSE; 404 *ppmc = NULL; 405 } 406 407 return (0); 408 } 409 410 static int 411 armv7_get_config(int cpu, int ri, struct pmc **ppm) 412 { 413 414 *ppm = armv7_pcpu[cpu]->pc_armv7pmcs[ri].phw_pmc; 415 416 return 0; 417 } 418 419 /* 420 * XXX don't know what we should do here. 421 */ 422 static int 423 armv7_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 424 { 425 426 return 0; 427 } 428 429 static int 430 armv7_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 431 { 432 433 return 0; 434 } 435 436 static int 437 armv7_pcpu_init(struct pmc_mdep *md, int cpu) 438 { 439 struct armv7_cpu *pac; 440 struct pmc_hw *phw; 441 struct pmc_cpu *pc; 442 uint32_t pmnc; 443 int first_ri; 444 int i; 445 446 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 447 ("[armv7,%d] wrong cpu number %d", __LINE__, cpu)); 448 PMCDBG1(MDP, INI, 1, "armv7-init cpu=%d", cpu); 449 450 armv7_pcpu[cpu] = pac = malloc(sizeof(struct armv7_cpu), M_PMC, 451 M_WAITOK|M_ZERO); 452 453 pac->pc_armv7pmcs = malloc(sizeof(struct pmc_hw) * armv7_npmcs, 454 M_PMC, M_WAITOK|M_ZERO); 455 pc = pmc_pcpu[cpu]; 456 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7].pcd_ri; 457 KASSERT(pc != NULL, ("[armv7,%d] NULL per-cpu pointer", __LINE__)); 458 459 for (i = 0, phw = pac->pc_armv7pmcs; i < armv7_npmcs; i++, phw++) { 460 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 461 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 462 phw->phw_pmc = NULL; 463 pc->pc_hwpmcs[i + first_ri] = phw; 464 } 465 466 pmnc = 0xffffffff; 467 cp15_pmcnten_clr(pmnc); 468 cp15_pminten_clr(pmnc); 469 cp15_pmovsr_set(pmnc); 470 471 /* Enable unit */ 472 pmnc = cp15_pmcr_get(); 473 pmnc |= ARMV7_PMNC_ENABLE; 474 cp15_pmcr_set(pmnc); 475 476 return 0; 477 } 478 479 static int 480 armv7_pcpu_fini(struct pmc_mdep *md, int cpu) 481 { 482 uint32_t pmnc; 483 484 pmnc = cp15_pmcr_get(); 485 pmnc &= ~ARMV7_PMNC_ENABLE; 486 cp15_pmcr_set(pmnc); 487 488 pmnc = 0xffffffff; 489 cp15_pmcnten_clr(pmnc); 490 cp15_pminten_clr(pmnc); 491 cp15_pmovsr_set(pmnc); 492 493 return 0; 494 } 495 496 struct pmc_mdep * 497 pmc_armv7_initialize() 498 { 499 struct pmc_mdep *pmc_mdep; 500 struct pmc_classdep *pcd; 501 int idcode; 502 int reg; 503 504 reg = cp15_pmcr_get(); 505 armv7_npmcs = (reg >> ARMV7_PMNC_N_SHIFT) & \ 506 ARMV7_PMNC_N_MASK; 507 idcode = (reg & ARMV7_IDCODE_MASK) >> ARMV7_IDCODE_SHIFT; 508 509 PMCDBG1(MDP, INI, 1, "armv7-init npmcs=%d", armv7_npmcs); 510 511 /* 512 * Allocate space for pointers to PMC HW descriptors and for 513 * the MDEP structure used by MI code. 514 */ 515 armv7_pcpu = malloc(sizeof(struct armv7_cpu *) * pmc_cpu_max(), 516 M_PMC, M_WAITOK | M_ZERO); 517 518 /* Just one class */ 519 pmc_mdep = pmc_mdep_alloc(1); 520 521 switch (idcode) { 522 case ARMV7_IDCODE_CORTEX_A9: 523 pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A9; 524 break; 525 default: 526 case ARMV7_IDCODE_CORTEX_A8: 527 /* 528 * On A8 we implemented common events only, 529 * so use it for the rest of machines. 530 */ 531 pmc_mdep->pmd_cputype = PMC_CPU_ARMV7_CORTEX_A8; 532 break; 533 } 534 535 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV7]; 536 pcd->pcd_caps = ARMV7_PMC_CAPS; 537 pcd->pcd_class = PMC_CLASS_ARMV7; 538 pcd->pcd_num = armv7_npmcs; 539 pcd->pcd_ri = pmc_mdep->pmd_npmc; 540 pcd->pcd_width = 32; 541 542 pcd->pcd_allocate_pmc = armv7_allocate_pmc; 543 pcd->pcd_config_pmc = armv7_config_pmc; 544 pcd->pcd_pcpu_fini = armv7_pcpu_fini; 545 pcd->pcd_pcpu_init = armv7_pcpu_init; 546 pcd->pcd_describe = armv7_describe; 547 pcd->pcd_get_config = armv7_get_config; 548 pcd->pcd_read_pmc = armv7_read_pmc; 549 pcd->pcd_release_pmc = armv7_release_pmc; 550 pcd->pcd_start_pmc = armv7_start_pmc; 551 pcd->pcd_stop_pmc = armv7_stop_pmc; 552 pcd->pcd_write_pmc = armv7_write_pmc; 553 554 pmc_mdep->pmd_intr = armv7_intr; 555 pmc_mdep->pmd_switch_in = armv7_switch_in; 556 pmc_mdep->pmd_switch_out = armv7_switch_out; 557 558 pmc_mdep->pmd_npmc += armv7_npmcs; 559 560 return (pmc_mdep); 561 } 562 563 void 564 pmc_armv7_finalize(struct pmc_mdep *md) 565 { 566 567 } 568