1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory with support from ARM Ltd. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/pmc.h> 36 #include <sys/pmckern.h> 37 38 #include <machine/pmc_mdep.h> 39 #include <machine/cpu.h> 40 41 static int arm64_npmcs; 42 43 struct arm64_event_code_map { 44 enum pmc_event pe_ev; 45 uint8_t pe_code; 46 }; 47 48 /* 49 * Per-processor information. 50 */ 51 struct arm64_cpu { 52 struct pmc_hw *pc_arm64pmcs; 53 }; 54 55 static struct arm64_cpu **arm64_pcpu; 56 57 /* 58 * Interrupt Enable Set Register 59 */ 60 static __inline void 61 arm64_interrupt_enable(uint32_t pmc) 62 { 63 uint32_t reg; 64 65 reg = (1 << pmc); 66 WRITE_SPECIALREG(pmintenset_el1, reg); 67 68 isb(); 69 } 70 71 /* 72 * Interrupt Clear Set Register 73 */ 74 static __inline void 75 arm64_interrupt_disable(uint32_t pmc) 76 { 77 uint32_t reg; 78 79 reg = (1 << pmc); 80 WRITE_SPECIALREG(pmintenclr_el1, reg); 81 82 isb(); 83 } 84 85 /* 86 * Counter Set Enable Register 87 */ 88 static __inline void 89 arm64_counter_enable(unsigned int pmc) 90 { 91 uint32_t reg; 92 93 reg = (1 << pmc); 94 WRITE_SPECIALREG(pmcntenset_el0, reg); 95 96 isb(); 97 } 98 99 /* 100 * Counter Clear Enable Register 101 */ 102 static __inline void 103 arm64_counter_disable(unsigned int pmc) 104 { 105 uint32_t reg; 106 107 reg = (1 << pmc); 108 WRITE_SPECIALREG(pmcntenclr_el0, reg); 109 110 isb(); 111 } 112 113 /* 114 * Performance Monitors Control Register 115 */ 116 static uint32_t 117 arm64_pmcr_read(void) 118 { 119 uint32_t reg; 120 121 reg = READ_SPECIALREG(pmcr_el0); 122 123 return (reg); 124 } 125 126 static void 127 arm64_pmcr_write(uint32_t reg) 128 { 129 130 WRITE_SPECIALREG(pmcr_el0, reg); 131 132 isb(); 133 } 134 135 /* 136 * Performance Count Register N 137 */ 138 static uint32_t 139 arm64_pmcn_read(unsigned int pmc) 140 { 141 142 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 143 144 WRITE_SPECIALREG(pmselr_el0, pmc); 145 146 isb(); 147 148 return (READ_SPECIALREG(pmxevcntr_el0)); 149 } 150 151 static void 152 arm64_pmcn_write(unsigned int pmc, uint32_t reg) 153 { 154 155 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 156 157 WRITE_SPECIALREG(pmselr_el0, pmc); 158 WRITE_SPECIALREG(pmxevcntr_el0, reg); 159 160 isb(); 161 } 162 163 static int 164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm, 165 const struct pmc_op_pmcallocate *a) 166 { 167 uint32_t config; 168 struct arm64_cpu *pac; 169 enum pmc_event pe; 170 171 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 172 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 173 KASSERT(ri >= 0 && ri < arm64_npmcs, 174 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 175 176 pac = arm64_pcpu[cpu]; 177 178 if (a->pm_class != PMC_CLASS_ARMV8) { 179 return (EINVAL); 180 } 181 pe = a->pm_ev; 182 183 /* Adjust the config value if needed. */ 184 config = a->pm_md.pm_md_config; 185 if ((a->pm_md.pm_md_flags & PM_MD_RAW_EVENT) == 0) { 186 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST; 187 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST)) 188 return (EINVAL); 189 } 190 191 switch (a->pm_caps & (PMC_CAP_SYSTEM | PMC_CAP_USER)) { 192 case PMC_CAP_SYSTEM: 193 config |= PMEVTYPER_U; 194 break; 195 case PMC_CAP_USER: 196 config |= PMEVTYPER_P; 197 break; 198 default: 199 /* 200 * Trace both USER and SYSTEM if none are specified 201 * (default setting) or if both flags are specified 202 * (user explicitly requested both qualifiers). 203 */ 204 break; 205 } 206 207 pm->pm_md.pm_arm64.pm_arm64_evsel = config; 208 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config); 209 210 return (0); 211 } 212 213 214 static int 215 arm64_read_pmc(int cpu, int ri, pmc_value_t *v) 216 { 217 pmc_value_t tmp; 218 struct pmc *pm; 219 register_t s; 220 int reg; 221 222 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 223 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 224 KASSERT(ri >= 0 && ri < arm64_npmcs, 225 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 226 227 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 228 229 /* 230 * Ensure we don't get interrupted while updating the overflow count. 231 */ 232 s = intr_disable(); 233 tmp = arm64_pmcn_read(ri); 234 reg = (1 << ri); 235 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) { 236 /* Clear Overflow Flag */ 237 WRITE_SPECIALREG(pmovsclr_el0, reg); 238 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 239 240 /* Reread counter in case we raced. */ 241 tmp = arm64_pmcn_read(ri); 242 } 243 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 244 intr_restore(s); 245 246 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); 247 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 248 /* 249 * Clamp value to 0 if the counter just overflowed, 250 * otherwise the returned reload count would wrap to a 251 * huge value. 252 */ 253 if ((tmp & (1ull << 63)) == 0) 254 tmp = 0; 255 else 256 tmp = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 257 } 258 *v = tmp; 259 260 return (0); 261 } 262 263 static int 264 arm64_write_pmc(int cpu, int ri, pmc_value_t v) 265 { 266 struct pmc *pm; 267 268 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 269 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 270 KASSERT(ri >= 0 && ri < arm64_npmcs, 271 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 272 273 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 274 275 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 276 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 277 278 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); 279 280 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 281 arm64_pmcn_write(ri, v); 282 283 return (0); 284 } 285 286 static int 287 arm64_config_pmc(int cpu, int ri, struct pmc *pm) 288 { 289 struct pmc_hw *phw; 290 291 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 292 293 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 294 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 295 KASSERT(ri >= 0 && ri < arm64_npmcs, 296 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 297 298 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 299 300 KASSERT(pm == NULL || phw->phw_pmc == NULL, 301 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 302 __LINE__, pm, phw->phw_pmc)); 303 304 phw->phw_pmc = pm; 305 306 return (0); 307 } 308 309 static int 310 arm64_start_pmc(int cpu, int ri) 311 { 312 struct pmc_hw *phw; 313 uint32_t config; 314 struct pmc *pm; 315 316 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 317 pm = phw->phw_pmc; 318 config = pm->pm_md.pm_arm64.pm_arm64_evsel; 319 320 /* 321 * Configure the event selection. 322 */ 323 WRITE_SPECIALREG(pmselr_el0, ri); 324 WRITE_SPECIALREG(pmxevtyper_el0, config); 325 326 isb(); 327 328 /* 329 * Enable the PMC. 330 */ 331 arm64_interrupt_enable(ri); 332 arm64_counter_enable(ri); 333 334 return (0); 335 } 336 337 static int 338 arm64_stop_pmc(int cpu, int ri) 339 { 340 struct pmc_hw *phw; 341 struct pmc *pm; 342 343 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 344 pm = phw->phw_pmc; 345 346 /* 347 * Disable the PMCs. 348 */ 349 arm64_counter_disable(ri); 350 arm64_interrupt_disable(ri); 351 352 return (0); 353 } 354 355 static int 356 arm64_release_pmc(int cpu, int ri, struct pmc *pmc) 357 { 358 struct pmc_hw *phw; 359 360 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 361 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 362 KASSERT(ri >= 0 && ri < arm64_npmcs, 363 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 364 365 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 366 KASSERT(phw->phw_pmc == NULL, 367 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 368 369 return (0); 370 } 371 372 static int 373 arm64_intr(struct trapframe *tf) 374 { 375 struct arm64_cpu *pc; 376 int retval, ri; 377 struct pmc *pm; 378 int error; 379 int reg, cpu; 380 381 cpu = curcpu; 382 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 383 ("[arm64,%d] CPU %d out of range", __LINE__, cpu)); 384 385 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf, 386 TRAPF_USERMODE(tf)); 387 388 retval = 0; 389 pc = arm64_pcpu[cpu]; 390 391 for (ri = 0; ri < arm64_npmcs; ri++) { 392 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 393 if (pm == NULL) 394 continue; 395 /* Check if counter is overflowed */ 396 reg = (1 << ri); 397 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) 398 continue; 399 /* Clear Overflow Flag */ 400 WRITE_SPECIALREG(pmovsclr_el0, reg); 401 402 isb(); 403 404 retval = 1; /* Found an interrupting PMC. */ 405 406 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 407 408 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 409 continue; 410 411 if (pm->pm_state != PMC_STATE_RUNNING) 412 continue; 413 414 error = pmc_process_interrupt(PMC_HR, pm, tf); 415 if (error) 416 arm64_stop_pmc(cpu, ri); 417 418 /* Reload sampling count */ 419 arm64_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount); 420 } 421 422 return (retval); 423 } 424 425 static int 426 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 427 { 428 char arm64_name[PMC_NAME_MAX]; 429 struct pmc_hw *phw; 430 int error; 431 432 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 433 ("[arm64,%d], illegal CPU %d", __LINE__, cpu)); 434 KASSERT(ri >= 0 && ri < arm64_npmcs, 435 ("[arm64,%d] row-index %d out of range", __LINE__, ri)); 436 437 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 438 snprintf(arm64_name, sizeof(arm64_name), "ARMV8-%d", ri); 439 if ((error = copystr(arm64_name, pi->pm_name, PMC_NAME_MAX, 440 NULL)) != 0) 441 return (error); 442 pi->pm_class = PMC_CLASS_ARMV8; 443 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 444 pi->pm_enabled = TRUE; 445 *ppmc = phw->phw_pmc; 446 } else { 447 pi->pm_enabled = FALSE; 448 *ppmc = NULL; 449 } 450 451 return (0); 452 } 453 454 static int 455 arm64_get_config(int cpu, int ri, struct pmc **ppm) 456 { 457 458 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 459 460 return (0); 461 } 462 463 /* 464 * XXX don't know what we should do here. 465 */ 466 static int 467 arm64_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 468 { 469 470 return (0); 471 } 472 473 static int 474 arm64_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 475 { 476 477 return (0); 478 } 479 480 static int 481 arm64_pcpu_init(struct pmc_mdep *md, int cpu) 482 { 483 struct arm64_cpu *pac; 484 struct pmc_hw *phw; 485 struct pmc_cpu *pc; 486 uint64_t pmcr; 487 int first_ri; 488 int i; 489 490 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 491 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu)); 492 PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu); 493 494 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC, 495 M_WAITOK | M_ZERO); 496 497 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs, 498 M_PMC, M_WAITOK | M_ZERO); 499 pc = pmc_pcpu[cpu]; 500 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri; 501 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__)); 502 503 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) { 504 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 505 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 506 phw->phw_pmc = NULL; 507 pc->pc_hwpmcs[i + first_ri] = phw; 508 } 509 510 /* 511 * Disable all counters and overflow interrupts. Upon reset they are in 512 * an undefined state. 513 * 514 * Don't issue an isb here, just wait for the one in arm64_pmcr_write() 515 * to make the writes visible. 516 */ 517 WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff); 518 WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff); 519 520 /* Enable unit */ 521 pmcr = arm64_pmcr_read(); 522 pmcr |= PMCR_E; 523 arm64_pmcr_write(pmcr); 524 525 return (0); 526 } 527 528 static int 529 arm64_pcpu_fini(struct pmc_mdep *md, int cpu) 530 { 531 uint32_t pmcr; 532 533 pmcr = arm64_pmcr_read(); 534 pmcr &= ~PMCR_E; 535 arm64_pmcr_write(pmcr); 536 537 return (0); 538 } 539 540 struct pmc_mdep * 541 pmc_arm64_initialize() 542 { 543 struct pmc_mdep *pmc_mdep; 544 struct pmc_classdep *pcd; 545 int idcode, impcode; 546 int reg; 547 uint64_t midr; 548 549 reg = arm64_pmcr_read(); 550 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; 551 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT; 552 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT; 553 554 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); 555 556 /* 557 * Write the CPU model to kern.hwpmc.cpuid. 558 * 559 * We zero the variant and revision fields. 560 * 561 * TODO: how to handle differences between cores due to big.LITTLE? 562 * For now, just use MIDR from CPU 0. 563 */ 564 midr = (uint64_t)(pcpu_find(0)->pc_midr); 565 midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); 566 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); 567 568 /* 569 * Allocate space for pointers to PMC HW descriptors and for 570 * the MDEP structure used by MI code. 571 */ 572 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(), 573 M_PMC, M_WAITOK | M_ZERO); 574 575 /* Just one class */ 576 pmc_mdep = pmc_mdep_alloc(1); 577 578 switch(impcode) { 579 case PMCR_IMP_ARM: 580 switch (idcode) { 581 case PMCR_IDCODE_CORTEX_A76: 582 case PMCR_IDCODE_NEOVERSE_N1: 583 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76; 584 break; 585 case PMCR_IDCODE_CORTEX_A57: 586 case PMCR_IDCODE_CORTEX_A72: 587 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57; 588 break; 589 default: 590 case PMCR_IDCODE_CORTEX_A53: 591 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 592 break; 593 } 594 break; 595 default: 596 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 597 break; 598 } 599 600 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8]; 601 pcd->pcd_caps = ARMV8_PMC_CAPS; 602 pcd->pcd_class = PMC_CLASS_ARMV8; 603 pcd->pcd_num = arm64_npmcs; 604 pcd->pcd_ri = pmc_mdep->pmd_npmc; 605 pcd->pcd_width = 32; 606 607 pcd->pcd_allocate_pmc = arm64_allocate_pmc; 608 pcd->pcd_config_pmc = arm64_config_pmc; 609 pcd->pcd_pcpu_fini = arm64_pcpu_fini; 610 pcd->pcd_pcpu_init = arm64_pcpu_init; 611 pcd->pcd_describe = arm64_describe; 612 pcd->pcd_get_config = arm64_get_config; 613 pcd->pcd_read_pmc = arm64_read_pmc; 614 pcd->pcd_release_pmc = arm64_release_pmc; 615 pcd->pcd_start_pmc = arm64_start_pmc; 616 pcd->pcd_stop_pmc = arm64_stop_pmc; 617 pcd->pcd_write_pmc = arm64_write_pmc; 618 619 pmc_mdep->pmd_intr = arm64_intr; 620 pmc_mdep->pmd_switch_in = arm64_switch_in; 621 pmc_mdep->pmd_switch_out = arm64_switch_out; 622 623 pmc_mdep->pmd_npmc += arm64_npmcs; 624 625 return (pmc_mdep); 626 } 627 628 void 629 pmc_arm64_finalize(struct pmc_mdep *md) 630 { 631 632 } 633