1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory with support from ARM Ltd. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/pmc.h> 36 #include <sys/pmckern.h> 37 38 #include <machine/pmc_mdep.h> 39 #include <machine/cpu.h> 40 41 static int arm64_npmcs; 42 43 struct arm64_event_code_map { 44 enum pmc_event pe_ev; 45 uint8_t pe_code; 46 }; 47 48 /* 49 * Per-processor information. 50 */ 51 struct arm64_cpu { 52 struct pmc_hw *pc_arm64pmcs; 53 }; 54 55 static struct arm64_cpu **arm64_pcpu; 56 57 /* 58 * Interrupt Enable Set Register 59 */ 60 static __inline void 61 arm64_interrupt_enable(uint32_t pmc) 62 { 63 uint32_t reg; 64 65 reg = (1 << pmc); 66 WRITE_SPECIALREG(pmintenset_el1, reg); 67 68 isb(); 69 } 70 71 /* 72 * Interrupt Clear Set Register 73 */ 74 static __inline void 75 arm64_interrupt_disable(uint32_t pmc) 76 { 77 uint32_t reg; 78 79 reg = (1 << pmc); 80 WRITE_SPECIALREG(pmintenclr_el1, reg); 81 82 isb(); 83 } 84 85 /* 86 * Counter Set Enable Register 87 */ 88 static __inline void 89 arm64_counter_enable(unsigned int pmc) 90 { 91 uint32_t reg; 92 93 reg = (1 << pmc); 94 WRITE_SPECIALREG(pmcntenset_el0, reg); 95 96 isb(); 97 } 98 99 /* 100 * Counter Clear Enable Register 101 */ 102 static __inline void 103 arm64_counter_disable(unsigned int pmc) 104 { 105 uint32_t reg; 106 107 reg = (1 << pmc); 108 WRITE_SPECIALREG(pmcntenclr_el0, reg); 109 110 isb(); 111 } 112 113 /* 114 * Performance Monitors Control Register 115 */ 116 static uint32_t 117 arm64_pmcr_read(void) 118 { 119 uint32_t reg; 120 121 reg = READ_SPECIALREG(pmcr_el0); 122 123 return (reg); 124 } 125 126 static void 127 arm64_pmcr_write(uint32_t reg) 128 { 129 130 WRITE_SPECIALREG(pmcr_el0, reg); 131 132 isb(); 133 } 134 135 /* 136 * Performance Count Register N 137 */ 138 static uint32_t 139 arm64_pmcn_read(unsigned int pmc) 140 { 141 142 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 143 144 WRITE_SPECIALREG(pmselr_el0, pmc); 145 146 isb(); 147 148 return (READ_SPECIALREG(pmxevcntr_el0)); 149 } 150 151 static void 152 arm64_pmcn_write(unsigned int pmc, uint32_t reg) 153 { 154 155 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 156 157 WRITE_SPECIALREG(pmselr_el0, pmc); 158 WRITE_SPECIALREG(pmxevcntr_el0, reg); 159 160 isb(); 161 } 162 163 static int 164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm, 165 const struct pmc_op_pmcallocate *a) 166 { 167 uint32_t caps, config; 168 struct arm64_cpu *pac; 169 enum pmc_event pe; 170 171 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 172 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 173 KASSERT(ri >= 0 && ri < arm64_npmcs, 174 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 175 176 pac = arm64_pcpu[cpu]; 177 178 caps = a->pm_caps; 179 if (a->pm_class != PMC_CLASS_ARMV8) { 180 return (EINVAL); 181 } 182 pe = a->pm_ev; 183 184 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST; 185 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST)) 186 return (EINVAL); 187 pm->pm_md.pm_arm64.pm_arm64_evsel = config; 188 189 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config); 190 191 return 0; 192 } 193 194 195 static int 196 arm64_read_pmc(int cpu, int ri, pmc_value_t *v) 197 { 198 pmc_value_t tmp; 199 struct pmc *pm; 200 register_t s; 201 int reg; 202 203 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 204 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 205 KASSERT(ri >= 0 && ri < arm64_npmcs, 206 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 207 208 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 209 210 /* 211 * Ensure we don't get interrupted while updating the overflow count. 212 */ 213 s = intr_disable(); 214 tmp = arm64_pmcn_read(ri); 215 reg = (1 << ri); 216 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) { 217 /* Clear Overflow Flag */ 218 WRITE_SPECIALREG(pmovsclr_el0, reg); 219 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 220 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 221 222 /* Reread counter in case we raced. */ 223 tmp = arm64_pmcn_read(ri); 224 } 225 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 226 intr_restore(s); 227 228 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); 229 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 230 *v = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 231 else 232 *v = tmp; 233 234 return 0; 235 } 236 237 static int 238 arm64_write_pmc(int cpu, int ri, pmc_value_t v) 239 { 240 struct pmc *pm; 241 242 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 243 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 244 KASSERT(ri >= 0 && ri < arm64_npmcs, 245 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 246 247 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 248 249 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 250 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 251 252 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); 253 254 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 255 arm64_pmcn_write(ri, v); 256 257 return 0; 258 } 259 260 static int 261 arm64_config_pmc(int cpu, int ri, struct pmc *pm) 262 { 263 struct pmc_hw *phw; 264 265 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 266 267 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 268 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 269 KASSERT(ri >= 0 && ri < arm64_npmcs, 270 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 271 272 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 273 274 KASSERT(pm == NULL || phw->phw_pmc == NULL, 275 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 276 __LINE__, pm, phw->phw_pmc)); 277 278 phw->phw_pmc = pm; 279 280 return 0; 281 } 282 283 static int 284 arm64_start_pmc(int cpu, int ri) 285 { 286 struct pmc_hw *phw; 287 uint32_t config; 288 struct pmc *pm; 289 290 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 291 pm = phw->phw_pmc; 292 config = pm->pm_md.pm_arm64.pm_arm64_evsel; 293 294 /* 295 * Configure the event selection. 296 */ 297 WRITE_SPECIALREG(pmselr_el0, ri); 298 WRITE_SPECIALREG(pmxevtyper_el0, config); 299 300 isb(); 301 302 /* 303 * Enable the PMC. 304 */ 305 arm64_interrupt_enable(ri); 306 arm64_counter_enable(ri); 307 308 return 0; 309 } 310 311 static int 312 arm64_stop_pmc(int cpu, int ri) 313 { 314 struct pmc_hw *phw; 315 struct pmc *pm; 316 317 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 318 pm = phw->phw_pmc; 319 320 /* 321 * Disable the PMCs. 322 */ 323 arm64_counter_disable(ri); 324 arm64_interrupt_disable(ri); 325 326 return 0; 327 } 328 329 static int 330 arm64_release_pmc(int cpu, int ri, struct pmc *pmc) 331 { 332 struct pmc_hw *phw; 333 334 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 335 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 336 KASSERT(ri >= 0 && ri < arm64_npmcs, 337 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 338 339 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 340 KASSERT(phw->phw_pmc == NULL, 341 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 342 343 return 0; 344 } 345 346 static int 347 arm64_intr(struct trapframe *tf) 348 { 349 struct arm64_cpu *pc; 350 int retval, ri; 351 struct pmc *pm; 352 int error; 353 int reg, cpu; 354 355 cpu = curcpu; 356 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 357 ("[arm64,%d] CPU %d out of range", __LINE__, cpu)); 358 359 retval = 0; 360 pc = arm64_pcpu[cpu]; 361 362 for (ri = 0; ri < arm64_npmcs; ri++) { 363 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 364 if (pm == NULL) 365 continue; 366 /* Check if counter is overflowed */ 367 reg = (1 << ri); 368 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) 369 continue; 370 /* Clear Overflow Flag */ 371 WRITE_SPECIALREG(pmovsclr_el0, reg); 372 373 isb(); 374 375 retval = 1; /* Found an interrupting PMC. */ 376 377 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 378 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 379 continue; 380 } 381 382 if (pm->pm_state != PMC_STATE_RUNNING) 383 continue; 384 385 error = pmc_process_interrupt(PMC_HR, pm, tf); 386 if (error) 387 arm64_stop_pmc(cpu, ri); 388 389 /* Reload sampling count */ 390 arm64_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount); 391 } 392 393 return (retval); 394 } 395 396 static int 397 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 398 { 399 char arm64_name[PMC_NAME_MAX]; 400 struct pmc_hw *phw; 401 int error; 402 403 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 404 ("[arm64,%d], illegal CPU %d", __LINE__, cpu)); 405 KASSERT(ri >= 0 && ri < arm64_npmcs, 406 ("[arm64,%d] row-index %d out of range", __LINE__, ri)); 407 408 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 409 snprintf(arm64_name, sizeof(arm64_name), "ARMV8-%d", ri); 410 if ((error = copystr(arm64_name, pi->pm_name, PMC_NAME_MAX, 411 NULL)) != 0) 412 return (error); 413 pi->pm_class = PMC_CLASS_ARMV8; 414 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 415 pi->pm_enabled = TRUE; 416 *ppmc = phw->phw_pmc; 417 } else { 418 pi->pm_enabled = FALSE; 419 *ppmc = NULL; 420 } 421 422 return (0); 423 } 424 425 static int 426 arm64_get_config(int cpu, int ri, struct pmc **ppm) 427 { 428 429 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 430 431 return (0); 432 } 433 434 /* 435 * XXX don't know what we should do here. 436 */ 437 static int 438 arm64_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 439 { 440 441 return (0); 442 } 443 444 static int 445 arm64_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 446 { 447 448 return (0); 449 } 450 451 static int 452 arm64_pcpu_init(struct pmc_mdep *md, int cpu) 453 { 454 struct arm64_cpu *pac; 455 struct pmc_hw *phw; 456 struct pmc_cpu *pc; 457 uint64_t pmcr; 458 int first_ri; 459 int i; 460 461 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 462 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu)); 463 PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu); 464 465 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC, 466 M_WAITOK | M_ZERO); 467 468 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs, 469 M_PMC, M_WAITOK | M_ZERO); 470 pc = pmc_pcpu[cpu]; 471 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri; 472 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__)); 473 474 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) { 475 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 476 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 477 phw->phw_pmc = NULL; 478 pc->pc_hwpmcs[i + first_ri] = phw; 479 } 480 481 /* Enable unit */ 482 pmcr = arm64_pmcr_read(); 483 pmcr |= PMCR_E; 484 arm64_pmcr_write(pmcr); 485 486 return (0); 487 } 488 489 static int 490 arm64_pcpu_fini(struct pmc_mdep *md, int cpu) 491 { 492 uint32_t pmcr; 493 494 pmcr = arm64_pmcr_read(); 495 pmcr &= ~PMCR_E; 496 arm64_pmcr_write(pmcr); 497 498 return (0); 499 } 500 501 struct pmc_mdep * 502 pmc_arm64_initialize() 503 { 504 struct pmc_mdep *pmc_mdep; 505 struct pmc_classdep *pcd; 506 int idcode, impcode; 507 int reg; 508 509 reg = arm64_pmcr_read(); 510 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; 511 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT; 512 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT; 513 514 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); 515 516 /* 517 * Allocate space for pointers to PMC HW descriptors and for 518 * the MDEP structure used by MI code. 519 */ 520 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(), 521 M_PMC, M_WAITOK | M_ZERO); 522 523 /* Just one class */ 524 pmc_mdep = pmc_mdep_alloc(1); 525 526 switch(impcode) { 527 case PMCR_IMP_ARM: 528 switch (idcode) { 529 case PMCR_IDCODE_CORTEX_A76: 530 case PMCR_IDCODE_NEOVERSE_N1: 531 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76; 532 break; 533 case PMCR_IDCODE_CORTEX_A57: 534 case PMCR_IDCODE_CORTEX_A72: 535 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57; 536 break; 537 default: 538 case PMCR_IDCODE_CORTEX_A53: 539 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 540 break; 541 } 542 break; 543 default: 544 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 545 break; 546 } 547 548 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8]; 549 pcd->pcd_caps = ARMV8_PMC_CAPS; 550 pcd->pcd_class = PMC_CLASS_ARMV8; 551 pcd->pcd_num = arm64_npmcs; 552 pcd->pcd_ri = pmc_mdep->pmd_npmc; 553 pcd->pcd_width = 32; 554 555 pcd->pcd_allocate_pmc = arm64_allocate_pmc; 556 pcd->pcd_config_pmc = arm64_config_pmc; 557 pcd->pcd_pcpu_fini = arm64_pcpu_fini; 558 pcd->pcd_pcpu_init = arm64_pcpu_init; 559 pcd->pcd_describe = arm64_describe; 560 pcd->pcd_get_config = arm64_get_config; 561 pcd->pcd_read_pmc = arm64_read_pmc; 562 pcd->pcd_release_pmc = arm64_release_pmc; 563 pcd->pcd_start_pmc = arm64_start_pmc; 564 pcd->pcd_stop_pmc = arm64_stop_pmc; 565 pcd->pcd_write_pmc = arm64_write_pmc; 566 567 pmc_mdep->pmd_intr = arm64_intr; 568 pmc_mdep->pmd_switch_in = arm64_switch_in; 569 pmc_mdep->pmd_switch_out = arm64_switch_out; 570 571 pmc_mdep->pmd_npmc += arm64_npmcs; 572 573 return (pmc_mdep); 574 } 575 576 void 577 pmc_arm64_finalize(struct pmc_mdep *md) 578 { 579 580 } 581