1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory with support from ARM Ltd. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/pmc.h> 36 #include <sys/pmckern.h> 37 38 #include <machine/pmc_mdep.h> 39 #include <machine/cpu.h> 40 41 #include "opt_acpi.h" 42 43 static int arm64_npmcs; 44 45 struct arm64_event_code_map { 46 enum pmc_event pe_ev; 47 uint8_t pe_code; 48 }; 49 50 /* 51 * Per-processor information. 52 */ 53 struct arm64_cpu { 54 struct pmc_hw *pc_arm64pmcs; 55 }; 56 57 static struct arm64_cpu **arm64_pcpu; 58 59 /* 60 * Interrupt Enable Set Register 61 */ 62 static __inline void 63 arm64_interrupt_enable(uint32_t pmc) 64 { 65 uint32_t reg; 66 67 reg = (1 << pmc); 68 WRITE_SPECIALREG(pmintenset_el1, reg); 69 70 isb(); 71 } 72 73 /* 74 * Interrupt Clear Set Register 75 */ 76 static __inline void 77 arm64_interrupt_disable(uint32_t pmc) 78 { 79 uint32_t reg; 80 81 reg = (1 << pmc); 82 WRITE_SPECIALREG(pmintenclr_el1, reg); 83 84 isb(); 85 } 86 87 /* 88 * Counter Set Enable Register 89 */ 90 static __inline void 91 arm64_counter_enable(unsigned int pmc) 92 { 93 uint32_t reg; 94 95 reg = (1 << pmc); 96 WRITE_SPECIALREG(pmcntenset_el0, reg); 97 98 isb(); 99 } 100 101 /* 102 * Counter Clear Enable Register 103 */ 104 static __inline void 105 arm64_counter_disable(unsigned int pmc) 106 { 107 uint32_t reg; 108 109 reg = (1 << pmc); 110 WRITE_SPECIALREG(pmcntenclr_el0, reg); 111 112 isb(); 113 } 114 115 /* 116 * Performance Monitors Control Register 117 */ 118 static uint32_t 119 arm64_pmcr_read(void) 120 { 121 uint32_t reg; 122 123 reg = READ_SPECIALREG(pmcr_el0); 124 125 return (reg); 126 } 127 128 static void 129 arm64_pmcr_write(uint32_t reg) 130 { 131 132 WRITE_SPECIALREG(pmcr_el0, reg); 133 134 isb(); 135 } 136 137 /* 138 * Performance Count Register N 139 */ 140 static uint32_t 141 arm64_pmcn_read(unsigned int pmc) 142 { 143 144 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 145 146 WRITE_SPECIALREG(pmselr_el0, pmc); 147 148 isb(); 149 150 return (READ_SPECIALREG(pmxevcntr_el0)); 151 } 152 153 static void 154 arm64_pmcn_write(unsigned int pmc, uint32_t reg) 155 { 156 157 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 158 159 WRITE_SPECIALREG(pmselr_el0, pmc); 160 WRITE_SPECIALREG(pmxevcntr_el0, reg); 161 162 isb(); 163 } 164 165 static int 166 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm, 167 const struct pmc_op_pmcallocate *a) 168 { 169 uint32_t config; 170 enum pmc_event pe; 171 172 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 173 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 174 KASSERT(ri >= 0 && ri < arm64_npmcs, 175 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 176 177 if (a->pm_class != PMC_CLASS_ARMV8) { 178 return (EINVAL); 179 } 180 pe = a->pm_ev; 181 182 /* Adjust the config value if needed. */ 183 config = a->pm_md.pm_md_config; 184 if ((a->pm_md.pm_md_flags & PM_MD_RAW_EVENT) == 0) { 185 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST; 186 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST)) 187 return (EINVAL); 188 } 189 190 switch (a->pm_caps & (PMC_CAP_SYSTEM | PMC_CAP_USER)) { 191 case PMC_CAP_SYSTEM: 192 config |= PMEVTYPER_U; 193 break; 194 case PMC_CAP_USER: 195 config |= PMEVTYPER_P; 196 break; 197 default: 198 /* 199 * Trace both USER and SYSTEM if none are specified 200 * (default setting) or if both flags are specified 201 * (user explicitly requested both qualifiers). 202 */ 203 break; 204 } 205 206 pm->pm_md.pm_arm64.pm_arm64_evsel = config; 207 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config); 208 209 return (0); 210 } 211 212 213 static int 214 arm64_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v) 215 { 216 pmc_value_t tmp; 217 register_t s; 218 int reg; 219 220 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 221 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 222 KASSERT(ri >= 0 && ri < arm64_npmcs, 223 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 224 225 /* 226 * Ensure we don't get interrupted while updating the overflow count. 227 */ 228 s = intr_disable(); 229 tmp = arm64_pmcn_read(ri); 230 reg = (1 << ri); 231 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) { 232 /* Clear Overflow Flag */ 233 WRITE_SPECIALREG(pmovsclr_el0, reg); 234 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 235 236 /* Reread counter in case we raced. */ 237 tmp = arm64_pmcn_read(ri); 238 } 239 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 240 intr_restore(s); 241 242 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); 243 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 244 /* 245 * Clamp value to 0 if the counter just overflowed, 246 * otherwise the returned reload count would wrap to a 247 * huge value. 248 */ 249 if ((tmp & (1ull << 63)) == 0) 250 tmp = 0; 251 else 252 tmp = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 253 } 254 *v = tmp; 255 256 return (0); 257 } 258 259 static int 260 arm64_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v) 261 { 262 263 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 264 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 265 KASSERT(ri >= 0 && ri < arm64_npmcs, 266 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 267 268 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 269 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 270 271 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); 272 273 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 274 arm64_pmcn_write(ri, v); 275 276 return (0); 277 } 278 279 static int 280 arm64_config_pmc(int cpu, int ri, struct pmc *pm) 281 { 282 struct pmc_hw *phw; 283 284 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 285 286 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 287 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 288 KASSERT(ri >= 0 && ri < arm64_npmcs, 289 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 290 291 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 292 293 KASSERT(pm == NULL || phw->phw_pmc == NULL, 294 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 295 __LINE__, pm, phw->phw_pmc)); 296 297 phw->phw_pmc = pm; 298 299 return (0); 300 } 301 302 static int 303 arm64_start_pmc(int cpu, int ri, struct pmc *pm) 304 { 305 uint32_t config; 306 307 config = pm->pm_md.pm_arm64.pm_arm64_evsel; 308 309 /* 310 * Configure the event selection. 311 */ 312 WRITE_SPECIALREG(pmselr_el0, ri); 313 WRITE_SPECIALREG(pmxevtyper_el0, config); 314 315 isb(); 316 317 /* 318 * Enable the PMC. 319 */ 320 arm64_interrupt_enable(ri); 321 arm64_counter_enable(ri); 322 323 return (0); 324 } 325 326 static int 327 arm64_stop_pmc(int cpu, int ri, struct pmc *pm __unused) 328 { 329 /* 330 * Disable the PMCs. 331 */ 332 arm64_counter_disable(ri); 333 arm64_interrupt_disable(ri); 334 335 return (0); 336 } 337 338 static int 339 arm64_release_pmc(int cpu, int ri, struct pmc *pmc) 340 { 341 struct pmc_hw *phw __diagused; 342 343 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 344 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 345 KASSERT(ri >= 0 && ri < arm64_npmcs, 346 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 347 348 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 349 KASSERT(phw->phw_pmc == NULL, 350 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 351 352 return (0); 353 } 354 355 static int 356 arm64_intr(struct trapframe *tf) 357 { 358 int retval, ri; 359 struct pmc *pm; 360 int error; 361 int reg, cpu; 362 363 cpu = curcpu; 364 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 365 ("[arm64,%d] CPU %d out of range", __LINE__, cpu)); 366 367 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf, 368 TRAPF_USERMODE(tf)); 369 370 retval = 0; 371 372 for (ri = 0; ri < arm64_npmcs; ri++) { 373 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 374 if (pm == NULL) 375 continue; 376 /* Check if counter is overflowed */ 377 reg = (1 << ri); 378 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) 379 continue; 380 /* Clear Overflow Flag */ 381 WRITE_SPECIALREG(pmovsclr_el0, reg); 382 383 isb(); 384 385 retval = 1; /* Found an interrupting PMC. */ 386 387 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 388 389 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 390 continue; 391 392 if (pm->pm_state != PMC_STATE_RUNNING) 393 continue; 394 395 error = pmc_process_interrupt(PMC_HR, pm, tf); 396 if (error) 397 arm64_stop_pmc(cpu, ri, pm); 398 399 /* Reload sampling count */ 400 arm64_write_pmc(cpu, ri, pm, pm->pm_sc.pm_reloadcount); 401 } 402 403 return (retval); 404 } 405 406 static int 407 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 408 { 409 struct pmc_hw *phw; 410 411 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 412 ("[arm64,%d], illegal CPU %d", __LINE__, cpu)); 413 KASSERT(ri >= 0 && ri < arm64_npmcs, 414 ("[arm64,%d] row-index %d out of range", __LINE__, ri)); 415 416 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 417 418 snprintf(pi->pm_name, sizeof(pi->pm_name), "ARMV8-%d", ri); 419 pi->pm_class = PMC_CLASS_ARMV8; 420 421 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 422 pi->pm_enabled = TRUE; 423 *ppmc = phw->phw_pmc; 424 } else { 425 pi->pm_enabled = FALSE; 426 *ppmc = NULL; 427 } 428 429 return (0); 430 } 431 432 static int 433 arm64_get_config(int cpu, int ri, struct pmc **ppm) 434 { 435 436 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 437 438 return (0); 439 } 440 441 static int 442 arm64_pcpu_init(struct pmc_mdep *md, int cpu) 443 { 444 struct arm64_cpu *pac; 445 struct pmc_hw *phw; 446 struct pmc_cpu *pc; 447 uint64_t pmcr; 448 int first_ri; 449 int i; 450 451 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 452 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu)); 453 PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu); 454 455 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC, 456 M_WAITOK | M_ZERO); 457 458 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs, 459 M_PMC, M_WAITOK | M_ZERO); 460 pc = pmc_pcpu[cpu]; 461 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri; 462 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__)); 463 464 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) { 465 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 466 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 467 phw->phw_pmc = NULL; 468 pc->pc_hwpmcs[i + first_ri] = phw; 469 } 470 471 /* 472 * Disable all counters and overflow interrupts. Upon reset they are in 473 * an undefined state. 474 * 475 * Don't issue an isb here, just wait for the one in arm64_pmcr_write() 476 * to make the writes visible. 477 */ 478 WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff); 479 WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff); 480 481 /* Enable unit */ 482 pmcr = arm64_pmcr_read(); 483 pmcr |= PMCR_E; 484 arm64_pmcr_write(pmcr); 485 486 return (0); 487 } 488 489 static int 490 arm64_pcpu_fini(struct pmc_mdep *md, int cpu) 491 { 492 uint32_t pmcr; 493 494 pmcr = arm64_pmcr_read(); 495 pmcr &= ~PMCR_E; 496 arm64_pmcr_write(pmcr); 497 498 return (0); 499 } 500 501 struct pmc_mdep * 502 pmc_arm64_initialize(void) 503 { 504 struct pmc_mdep *pmc_mdep; 505 struct pmc_classdep *pcd; 506 int classes, idcode, impcode; 507 int reg; 508 uint64_t midr; 509 510 reg = arm64_pmcr_read(); 511 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; 512 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT; 513 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT; 514 515 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); 516 517 /* 518 * Write the CPU model to kern.hwpmc.cpuid. 519 * 520 * We zero the variant and revision fields. 521 * 522 * TODO: how to handle differences between cores due to big.LITTLE? 523 * For now, just use MIDR from CPU 0. 524 */ 525 midr = (uint64_t)(pcpu_find(0)->pc_midr); 526 midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); 527 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); 528 529 /* 530 * Allocate space for pointers to PMC HW descriptors and for 531 * the MDEP structure used by MI code. 532 */ 533 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(), 534 M_PMC, M_WAITOK | M_ZERO); 535 536 /* One AArch64 CPU class */ 537 classes = 1; 538 539 #ifdef DEV_ACPI 540 /* Query presence of optional classes and set max class. */ 541 if (pmc_cmn600_nclasses() > 0) 542 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_CMN600); 543 if (pmc_dmc620_nclasses() > 0) 544 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_DMC620_C); 545 #endif 546 547 pmc_mdep = pmc_mdep_alloc(classes); 548 549 switch(impcode) { 550 case PMCR_IMP_ARM: 551 switch (idcode) { 552 case PMCR_IDCODE_CORTEX_A76: 553 case PMCR_IDCODE_NEOVERSE_N1: 554 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76; 555 break; 556 case PMCR_IDCODE_CORTEX_A57: 557 case PMCR_IDCODE_CORTEX_A72: 558 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57; 559 break; 560 default: 561 case PMCR_IDCODE_CORTEX_A53: 562 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 563 break; 564 } 565 break; 566 default: 567 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 568 break; 569 } 570 571 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8]; 572 pcd->pcd_caps = ARMV8_PMC_CAPS; 573 pcd->pcd_class = PMC_CLASS_ARMV8; 574 pcd->pcd_num = arm64_npmcs; 575 pcd->pcd_ri = pmc_mdep->pmd_npmc; 576 pcd->pcd_width = 32; 577 578 pcd->pcd_allocate_pmc = arm64_allocate_pmc; 579 pcd->pcd_config_pmc = arm64_config_pmc; 580 pcd->pcd_pcpu_fini = arm64_pcpu_fini; 581 pcd->pcd_pcpu_init = arm64_pcpu_init; 582 pcd->pcd_describe = arm64_describe; 583 pcd->pcd_get_config = arm64_get_config; 584 pcd->pcd_read_pmc = arm64_read_pmc; 585 pcd->pcd_release_pmc = arm64_release_pmc; 586 pcd->pcd_start_pmc = arm64_start_pmc; 587 pcd->pcd_stop_pmc = arm64_stop_pmc; 588 pcd->pcd_write_pmc = arm64_write_pmc; 589 590 pmc_mdep->pmd_intr = arm64_intr; 591 pmc_mdep->pmd_npmc += arm64_npmcs; 592 593 #ifdef DEV_ACPI 594 if (pmc_cmn600_nclasses() > 0) 595 pmc_cmn600_initialize(pmc_mdep); 596 if (pmc_dmc620_nclasses() > 0) { 597 pmc_dmc620_initialize_cd2(pmc_mdep); 598 pmc_dmc620_initialize_c(pmc_mdep); 599 } 600 #endif 601 602 return (pmc_mdep); 603 } 604 605 void 606 pmc_arm64_finalize(struct pmc_mdep *md) 607 { 608 609 } 610