1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory with support from ARM Ltd. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/pmc.h> 36 #include <sys/pmckern.h> 37 38 #include <machine/pmc_mdep.h> 39 #include <machine/cpu.h> 40 41 static int arm64_npmcs; 42 43 struct arm64_event_code_map { 44 enum pmc_event pe_ev; 45 uint8_t pe_code; 46 }; 47 48 /* 49 * Per-processor information. 50 */ 51 struct arm64_cpu { 52 struct pmc_hw *pc_arm64pmcs; 53 }; 54 55 static struct arm64_cpu **arm64_pcpu; 56 57 /* 58 * Interrupt Enable Set Register 59 */ 60 static __inline void 61 arm64_interrupt_enable(uint32_t pmc) 62 { 63 uint32_t reg; 64 65 reg = (1 << pmc); 66 WRITE_SPECIALREG(pmintenset_el1, reg); 67 68 isb(); 69 } 70 71 /* 72 * Interrupt Clear Set Register 73 */ 74 static __inline void 75 arm64_interrupt_disable(uint32_t pmc) 76 { 77 uint32_t reg; 78 79 reg = (1 << pmc); 80 WRITE_SPECIALREG(pmintenclr_el1, reg); 81 82 isb(); 83 } 84 85 /* 86 * Counter Set Enable Register 87 */ 88 static __inline void 89 arm64_counter_enable(unsigned int pmc) 90 { 91 uint32_t reg; 92 93 reg = (1 << pmc); 94 WRITE_SPECIALREG(pmcntenset_el0, reg); 95 96 isb(); 97 } 98 99 /* 100 * Counter Clear Enable Register 101 */ 102 static __inline void 103 arm64_counter_disable(unsigned int pmc) 104 { 105 uint32_t reg; 106 107 reg = (1 << pmc); 108 WRITE_SPECIALREG(pmcntenclr_el0, reg); 109 110 isb(); 111 } 112 113 /* 114 * Performance Monitors Control Register 115 */ 116 static uint32_t 117 arm64_pmcr_read(void) 118 { 119 uint32_t reg; 120 121 reg = READ_SPECIALREG(pmcr_el0); 122 123 return (reg); 124 } 125 126 static void 127 arm64_pmcr_write(uint32_t reg) 128 { 129 130 WRITE_SPECIALREG(pmcr_el0, reg); 131 132 isb(); 133 } 134 135 /* 136 * Performance Count Register N 137 */ 138 static uint32_t 139 arm64_pmcn_read(unsigned int pmc) 140 { 141 142 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 143 144 WRITE_SPECIALREG(pmselr_el0, pmc); 145 146 isb(); 147 148 return (READ_SPECIALREG(pmxevcntr_el0)); 149 } 150 151 static void 152 arm64_pmcn_write(unsigned int pmc, uint32_t reg) 153 { 154 155 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 156 157 WRITE_SPECIALREG(pmselr_el0, pmc); 158 WRITE_SPECIALREG(pmxevcntr_el0, reg); 159 160 isb(); 161 } 162 163 static int 164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm, 165 const struct pmc_op_pmcallocate *a) 166 { 167 uint32_t caps, config; 168 struct arm64_cpu *pac; 169 enum pmc_event pe; 170 171 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 172 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 173 KASSERT(ri >= 0 && ri < arm64_npmcs, 174 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 175 176 pac = arm64_pcpu[cpu]; 177 178 caps = a->pm_caps; 179 if (a->pm_class != PMC_CLASS_ARMV8) { 180 return (EINVAL); 181 } 182 pe = a->pm_ev; 183 184 /* Adjust the config value if needed. */ 185 config = a->pm_md.pm_md_config; 186 if ((a->pm_md.pm_md_flags & PM_MD_RAW_EVENT) == 0) { 187 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST; 188 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST)) 189 return (EINVAL); 190 } 191 pm->pm_md.pm_arm64.pm_arm64_evsel = config; 192 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config); 193 194 return (0); 195 } 196 197 198 static int 199 arm64_read_pmc(int cpu, int ri, pmc_value_t *v) 200 { 201 pmc_value_t tmp; 202 struct pmc *pm; 203 register_t s; 204 int reg; 205 206 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 207 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 208 KASSERT(ri >= 0 && ri < arm64_npmcs, 209 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 210 211 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 212 213 /* 214 * Ensure we don't get interrupted while updating the overflow count. 215 */ 216 s = intr_disable(); 217 tmp = arm64_pmcn_read(ri); 218 reg = (1 << ri); 219 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) { 220 /* Clear Overflow Flag */ 221 WRITE_SPECIALREG(pmovsclr_el0, reg); 222 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 223 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 224 225 /* Reread counter in case we raced. */ 226 tmp = arm64_pmcn_read(ri); 227 } 228 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 229 intr_restore(s); 230 231 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); 232 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 233 *v = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 234 else 235 *v = tmp; 236 237 return (0); 238 } 239 240 static int 241 arm64_write_pmc(int cpu, int ri, pmc_value_t v) 242 { 243 struct pmc *pm; 244 245 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 246 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 247 KASSERT(ri >= 0 && ri < arm64_npmcs, 248 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 249 250 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 251 252 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 253 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 254 255 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); 256 257 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 258 arm64_pmcn_write(ri, v); 259 260 return (0); 261 } 262 263 static int 264 arm64_config_pmc(int cpu, int ri, struct pmc *pm) 265 { 266 struct pmc_hw *phw; 267 268 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 269 270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 271 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 272 KASSERT(ri >= 0 && ri < arm64_npmcs, 273 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 274 275 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 276 277 KASSERT(pm == NULL || phw->phw_pmc == NULL, 278 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 279 __LINE__, pm, phw->phw_pmc)); 280 281 phw->phw_pmc = pm; 282 283 return (0); 284 } 285 286 static int 287 arm64_start_pmc(int cpu, int ri) 288 { 289 struct pmc_hw *phw; 290 uint32_t config; 291 struct pmc *pm; 292 293 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 294 pm = phw->phw_pmc; 295 config = pm->pm_md.pm_arm64.pm_arm64_evsel; 296 297 /* 298 * Configure the event selection. 299 */ 300 WRITE_SPECIALREG(pmselr_el0, ri); 301 WRITE_SPECIALREG(pmxevtyper_el0, config); 302 303 isb(); 304 305 /* 306 * Enable the PMC. 307 */ 308 arm64_interrupt_enable(ri); 309 arm64_counter_enable(ri); 310 311 return (0); 312 } 313 314 static int 315 arm64_stop_pmc(int cpu, int ri) 316 { 317 struct pmc_hw *phw; 318 struct pmc *pm; 319 320 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 321 pm = phw->phw_pmc; 322 323 /* 324 * Disable the PMCs. 325 */ 326 arm64_counter_disable(ri); 327 arm64_interrupt_disable(ri); 328 329 return (0); 330 } 331 332 static int 333 arm64_release_pmc(int cpu, int ri, struct pmc *pmc) 334 { 335 struct pmc_hw *phw; 336 337 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 338 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 339 KASSERT(ri >= 0 && ri < arm64_npmcs, 340 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 341 342 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 343 KASSERT(phw->phw_pmc == NULL, 344 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 345 346 return (0); 347 } 348 349 static int 350 arm64_intr(struct trapframe *tf) 351 { 352 struct arm64_cpu *pc; 353 int retval, ri; 354 struct pmc *pm; 355 int error; 356 int reg, cpu; 357 358 cpu = curcpu; 359 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 360 ("[arm64,%d] CPU %d out of range", __LINE__, cpu)); 361 362 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf, 363 TRAPF_USERMODE(tf)); 364 365 retval = 0; 366 pc = arm64_pcpu[cpu]; 367 368 for (ri = 0; ri < arm64_npmcs; ri++) { 369 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 370 if (pm == NULL) 371 continue; 372 /* Check if counter is overflowed */ 373 reg = (1 << ri); 374 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) 375 continue; 376 /* Clear Overflow Flag */ 377 WRITE_SPECIALREG(pmovsclr_el0, reg); 378 379 isb(); 380 381 retval = 1; /* Found an interrupting PMC. */ 382 383 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 384 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 385 continue; 386 } 387 388 if (pm->pm_state != PMC_STATE_RUNNING) 389 continue; 390 391 error = pmc_process_interrupt(PMC_HR, pm, tf); 392 if (error) 393 arm64_stop_pmc(cpu, ri); 394 395 /* Reload sampling count */ 396 arm64_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount); 397 } 398 399 return (retval); 400 } 401 402 static int 403 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 404 { 405 char arm64_name[PMC_NAME_MAX]; 406 struct pmc_hw *phw; 407 int error; 408 409 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 410 ("[arm64,%d], illegal CPU %d", __LINE__, cpu)); 411 KASSERT(ri >= 0 && ri < arm64_npmcs, 412 ("[arm64,%d] row-index %d out of range", __LINE__, ri)); 413 414 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 415 snprintf(arm64_name, sizeof(arm64_name), "ARMV8-%d", ri); 416 if ((error = copystr(arm64_name, pi->pm_name, PMC_NAME_MAX, 417 NULL)) != 0) 418 return (error); 419 pi->pm_class = PMC_CLASS_ARMV8; 420 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 421 pi->pm_enabled = TRUE; 422 *ppmc = phw->phw_pmc; 423 } else { 424 pi->pm_enabled = FALSE; 425 *ppmc = NULL; 426 } 427 428 return (0); 429 } 430 431 static int 432 arm64_get_config(int cpu, int ri, struct pmc **ppm) 433 { 434 435 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 436 437 return (0); 438 } 439 440 /* 441 * XXX don't know what we should do here. 442 */ 443 static int 444 arm64_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 445 { 446 447 return (0); 448 } 449 450 static int 451 arm64_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 452 { 453 454 return (0); 455 } 456 457 static int 458 arm64_pcpu_init(struct pmc_mdep *md, int cpu) 459 { 460 struct arm64_cpu *pac; 461 struct pmc_hw *phw; 462 struct pmc_cpu *pc; 463 uint64_t pmcr; 464 int first_ri; 465 int i; 466 467 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 468 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu)); 469 PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu); 470 471 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC, 472 M_WAITOK | M_ZERO); 473 474 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs, 475 M_PMC, M_WAITOK | M_ZERO); 476 pc = pmc_pcpu[cpu]; 477 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri; 478 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__)); 479 480 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) { 481 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 482 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 483 phw->phw_pmc = NULL; 484 pc->pc_hwpmcs[i + first_ri] = phw; 485 } 486 487 /* Enable unit */ 488 pmcr = arm64_pmcr_read(); 489 pmcr |= PMCR_E; 490 arm64_pmcr_write(pmcr); 491 492 return (0); 493 } 494 495 static int 496 arm64_pcpu_fini(struct pmc_mdep *md, int cpu) 497 { 498 uint32_t pmcr; 499 500 pmcr = arm64_pmcr_read(); 501 pmcr &= ~PMCR_E; 502 arm64_pmcr_write(pmcr); 503 504 return (0); 505 } 506 507 struct pmc_mdep * 508 pmc_arm64_initialize() 509 { 510 struct pmc_mdep *pmc_mdep; 511 struct pmc_classdep *pcd; 512 int idcode, impcode; 513 int reg; 514 uint64_t midr; 515 516 reg = arm64_pmcr_read(); 517 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; 518 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT; 519 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT; 520 521 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); 522 523 /* 524 * Write the CPU model to kern.hwpmc.cpuid. 525 * 526 * We zero the variant and revision fields. 527 * 528 * TODO: how to handle differences between cores due to big.LITTLE? 529 * For now, just use MIDR from CPU 0. 530 */ 531 midr = (uint64_t)(pcpu_find(0)->pc_midr); 532 midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); 533 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); 534 535 /* 536 * Allocate space for pointers to PMC HW descriptors and for 537 * the MDEP structure used by MI code. 538 */ 539 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(), 540 M_PMC, M_WAITOK | M_ZERO); 541 542 /* Just one class */ 543 pmc_mdep = pmc_mdep_alloc(1); 544 545 switch(impcode) { 546 case PMCR_IMP_ARM: 547 switch (idcode) { 548 case PMCR_IDCODE_CORTEX_A76: 549 case PMCR_IDCODE_NEOVERSE_N1: 550 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76; 551 break; 552 case PMCR_IDCODE_CORTEX_A57: 553 case PMCR_IDCODE_CORTEX_A72: 554 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57; 555 break; 556 default: 557 case PMCR_IDCODE_CORTEX_A53: 558 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 559 break; 560 } 561 break; 562 default: 563 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 564 break; 565 } 566 567 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8]; 568 pcd->pcd_caps = ARMV8_PMC_CAPS; 569 pcd->pcd_class = PMC_CLASS_ARMV8; 570 pcd->pcd_num = arm64_npmcs; 571 pcd->pcd_ri = pmc_mdep->pmd_npmc; 572 pcd->pcd_width = 32; 573 574 pcd->pcd_allocate_pmc = arm64_allocate_pmc; 575 pcd->pcd_config_pmc = arm64_config_pmc; 576 pcd->pcd_pcpu_fini = arm64_pcpu_fini; 577 pcd->pcd_pcpu_init = arm64_pcpu_init; 578 pcd->pcd_describe = arm64_describe; 579 pcd->pcd_get_config = arm64_get_config; 580 pcd->pcd_read_pmc = arm64_read_pmc; 581 pcd->pcd_release_pmc = arm64_release_pmc; 582 pcd->pcd_start_pmc = arm64_start_pmc; 583 pcd->pcd_stop_pmc = arm64_stop_pmc; 584 pcd->pcd_write_pmc = arm64_write_pmc; 585 586 pmc_mdep->pmd_intr = arm64_intr; 587 pmc_mdep->pmd_switch_in = arm64_switch_in; 588 pmc_mdep->pmd_switch_out = arm64_switch_out; 589 590 pmc_mdep->pmd_npmc += arm64_npmcs; 591 592 return (pmc_mdep); 593 } 594 595 void 596 pmc_arm64_finalize(struct pmc_mdep *md) 597 { 598 599 } 600