1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory with support from ARM Ltd. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/pmc.h> 36 #include <sys/pmckern.h> 37 38 #include <machine/pmc_mdep.h> 39 #include <machine/cpu.h> 40 41 static int arm64_npmcs; 42 43 struct arm64_event_code_map { 44 enum pmc_event pe_ev; 45 uint8_t pe_code; 46 }; 47 48 /* 49 * Per-processor information. 50 */ 51 struct arm64_cpu { 52 struct pmc_hw *pc_arm64pmcs; 53 }; 54 55 static struct arm64_cpu **arm64_pcpu; 56 57 /* 58 * Interrupt Enable Set Register 59 */ 60 static __inline void 61 arm64_interrupt_enable(uint32_t pmc) 62 { 63 uint32_t reg; 64 65 reg = (1 << pmc); 66 WRITE_SPECIALREG(pmintenset_el1, reg); 67 68 isb(); 69 } 70 71 /* 72 * Interrupt Clear Set Register 73 */ 74 static __inline void 75 arm64_interrupt_disable(uint32_t pmc) 76 { 77 uint32_t reg; 78 79 reg = (1 << pmc); 80 WRITE_SPECIALREG(pmintenclr_el1, reg); 81 82 isb(); 83 } 84 85 /* 86 * Counter Set Enable Register 87 */ 88 static __inline void 89 arm64_counter_enable(unsigned int pmc) 90 { 91 uint32_t reg; 92 93 reg = (1 << pmc); 94 WRITE_SPECIALREG(pmcntenset_el0, reg); 95 96 isb(); 97 } 98 99 /* 100 * Counter Clear Enable Register 101 */ 102 static __inline void 103 arm64_counter_disable(unsigned int pmc) 104 { 105 uint32_t reg; 106 107 reg = (1 << pmc); 108 WRITE_SPECIALREG(pmcntenclr_el0, reg); 109 110 isb(); 111 } 112 113 /* 114 * Performance Monitors Control Register 115 */ 116 static uint32_t 117 arm64_pmcr_read(void) 118 { 119 uint32_t reg; 120 121 reg = READ_SPECIALREG(pmcr_el0); 122 123 return (reg); 124 } 125 126 static void 127 arm64_pmcr_write(uint32_t reg) 128 { 129 130 WRITE_SPECIALREG(pmcr_el0, reg); 131 132 isb(); 133 } 134 135 /* 136 * Performance Count Register N 137 */ 138 static uint32_t 139 arm64_pmcn_read(unsigned int pmc) 140 { 141 142 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 143 144 WRITE_SPECIALREG(pmselr_el0, pmc); 145 146 isb(); 147 148 return (READ_SPECIALREG(pmxevcntr_el0)); 149 } 150 151 static void 152 arm64_pmcn_write(unsigned int pmc, uint32_t reg) 153 { 154 155 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 156 157 WRITE_SPECIALREG(pmselr_el0, pmc); 158 WRITE_SPECIALREG(pmxevcntr_el0, reg); 159 160 isb(); 161 } 162 163 static int 164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm, 165 const struct pmc_op_pmcallocate *a) 166 { 167 uint32_t config; 168 enum pmc_event pe; 169 170 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 171 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 172 KASSERT(ri >= 0 && ri < arm64_npmcs, 173 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 174 175 if (a->pm_class != PMC_CLASS_ARMV8) { 176 return (EINVAL); 177 } 178 pe = a->pm_ev; 179 180 /* Adjust the config value if needed. */ 181 config = a->pm_md.pm_md_config; 182 if ((a->pm_md.pm_md_flags & PM_MD_RAW_EVENT) == 0) { 183 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST; 184 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST)) 185 return (EINVAL); 186 } 187 188 switch (a->pm_caps & (PMC_CAP_SYSTEM | PMC_CAP_USER)) { 189 case PMC_CAP_SYSTEM: 190 config |= PMEVTYPER_U; 191 break; 192 case PMC_CAP_USER: 193 config |= PMEVTYPER_P; 194 break; 195 default: 196 /* 197 * Trace both USER and SYSTEM if none are specified 198 * (default setting) or if both flags are specified 199 * (user explicitly requested both qualifiers). 200 */ 201 break; 202 } 203 204 pm->pm_md.pm_arm64.pm_arm64_evsel = config; 205 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config); 206 207 return (0); 208 } 209 210 211 static int 212 arm64_read_pmc(int cpu, int ri, pmc_value_t *v) 213 { 214 pmc_value_t tmp; 215 struct pmc *pm; 216 register_t s; 217 int reg; 218 219 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 220 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 221 KASSERT(ri >= 0 && ri < arm64_npmcs, 222 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 223 224 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 225 226 /* 227 * Ensure we don't get interrupted while updating the overflow count. 228 */ 229 s = intr_disable(); 230 tmp = arm64_pmcn_read(ri); 231 reg = (1 << ri); 232 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) { 233 /* Clear Overflow Flag */ 234 WRITE_SPECIALREG(pmovsclr_el0, reg); 235 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 236 237 /* Reread counter in case we raced. */ 238 tmp = arm64_pmcn_read(ri); 239 } 240 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 241 intr_restore(s); 242 243 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); 244 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 245 /* 246 * Clamp value to 0 if the counter just overflowed, 247 * otherwise the returned reload count would wrap to a 248 * huge value. 249 */ 250 if ((tmp & (1ull << 63)) == 0) 251 tmp = 0; 252 else 253 tmp = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 254 } 255 *v = tmp; 256 257 return (0); 258 } 259 260 static int 261 arm64_write_pmc(int cpu, int ri, pmc_value_t v) 262 { 263 struct pmc *pm; 264 265 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 266 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 267 KASSERT(ri >= 0 && ri < arm64_npmcs, 268 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 269 270 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 271 272 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 273 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 274 275 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); 276 277 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 278 arm64_pmcn_write(ri, v); 279 280 return (0); 281 } 282 283 static int 284 arm64_config_pmc(int cpu, int ri, struct pmc *pm) 285 { 286 struct pmc_hw *phw; 287 288 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 289 290 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 291 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 292 KASSERT(ri >= 0 && ri < arm64_npmcs, 293 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 294 295 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 296 297 KASSERT(pm == NULL || phw->phw_pmc == NULL, 298 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 299 __LINE__, pm, phw->phw_pmc)); 300 301 phw->phw_pmc = pm; 302 303 return (0); 304 } 305 306 static int 307 arm64_start_pmc(int cpu, int ri) 308 { 309 struct pmc_hw *phw; 310 uint32_t config; 311 struct pmc *pm; 312 313 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 314 pm = phw->phw_pmc; 315 config = pm->pm_md.pm_arm64.pm_arm64_evsel; 316 317 /* 318 * Configure the event selection. 319 */ 320 WRITE_SPECIALREG(pmselr_el0, ri); 321 WRITE_SPECIALREG(pmxevtyper_el0, config); 322 323 isb(); 324 325 /* 326 * Enable the PMC. 327 */ 328 arm64_interrupt_enable(ri); 329 arm64_counter_enable(ri); 330 331 return (0); 332 } 333 334 static int 335 arm64_stop_pmc(int cpu, int ri) 336 { 337 /* 338 * Disable the PMCs. 339 */ 340 arm64_counter_disable(ri); 341 arm64_interrupt_disable(ri); 342 343 return (0); 344 } 345 346 static int 347 arm64_release_pmc(int cpu, int ri, struct pmc *pmc) 348 { 349 struct pmc_hw *phw __diagused; 350 351 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 352 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 353 KASSERT(ri >= 0 && ri < arm64_npmcs, 354 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 355 356 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 357 KASSERT(phw->phw_pmc == NULL, 358 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 359 360 return (0); 361 } 362 363 static int 364 arm64_intr(struct trapframe *tf) 365 { 366 int retval, ri; 367 struct pmc *pm; 368 int error; 369 int reg, cpu; 370 371 cpu = curcpu; 372 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 373 ("[arm64,%d] CPU %d out of range", __LINE__, cpu)); 374 375 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf, 376 TRAPF_USERMODE(tf)); 377 378 retval = 0; 379 380 for (ri = 0; ri < arm64_npmcs; ri++) { 381 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 382 if (pm == NULL) 383 continue; 384 /* Check if counter is overflowed */ 385 reg = (1 << ri); 386 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) 387 continue; 388 /* Clear Overflow Flag */ 389 WRITE_SPECIALREG(pmovsclr_el0, reg); 390 391 isb(); 392 393 retval = 1; /* Found an interrupting PMC. */ 394 395 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 396 397 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 398 continue; 399 400 if (pm->pm_state != PMC_STATE_RUNNING) 401 continue; 402 403 error = pmc_process_interrupt(PMC_HR, pm, tf); 404 if (error) 405 arm64_stop_pmc(cpu, ri); 406 407 /* Reload sampling count */ 408 arm64_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount); 409 } 410 411 return (retval); 412 } 413 414 static int 415 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 416 { 417 char arm64_name[PMC_NAME_MAX]; 418 struct pmc_hw *phw; 419 int error; 420 421 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 422 ("[arm64,%d], illegal CPU %d", __LINE__, cpu)); 423 KASSERT(ri >= 0 && ri < arm64_npmcs, 424 ("[arm64,%d] row-index %d out of range", __LINE__, ri)); 425 426 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 427 snprintf(arm64_name, sizeof(arm64_name), "ARMV8-%d", ri); 428 if ((error = copystr(arm64_name, pi->pm_name, PMC_NAME_MAX, 429 NULL)) != 0) 430 return (error); 431 pi->pm_class = PMC_CLASS_ARMV8; 432 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 433 pi->pm_enabled = TRUE; 434 *ppmc = phw->phw_pmc; 435 } else { 436 pi->pm_enabled = FALSE; 437 *ppmc = NULL; 438 } 439 440 return (0); 441 } 442 443 static int 444 arm64_get_config(int cpu, int ri, struct pmc **ppm) 445 { 446 447 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 448 449 return (0); 450 } 451 452 /* 453 * XXX don't know what we should do here. 454 */ 455 static int 456 arm64_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 457 { 458 459 return (0); 460 } 461 462 static int 463 arm64_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 464 { 465 466 return (0); 467 } 468 469 static int 470 arm64_pcpu_init(struct pmc_mdep *md, int cpu) 471 { 472 struct arm64_cpu *pac; 473 struct pmc_hw *phw; 474 struct pmc_cpu *pc; 475 uint64_t pmcr; 476 int first_ri; 477 int i; 478 479 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 480 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu)); 481 PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu); 482 483 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC, 484 M_WAITOK | M_ZERO); 485 486 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs, 487 M_PMC, M_WAITOK | M_ZERO); 488 pc = pmc_pcpu[cpu]; 489 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri; 490 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__)); 491 492 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) { 493 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 494 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 495 phw->phw_pmc = NULL; 496 pc->pc_hwpmcs[i + first_ri] = phw; 497 } 498 499 /* 500 * Disable all counters and overflow interrupts. Upon reset they are in 501 * an undefined state. 502 * 503 * Don't issue an isb here, just wait for the one in arm64_pmcr_write() 504 * to make the writes visible. 505 */ 506 WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff); 507 WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff); 508 509 /* Enable unit */ 510 pmcr = arm64_pmcr_read(); 511 pmcr |= PMCR_E; 512 arm64_pmcr_write(pmcr); 513 514 return (0); 515 } 516 517 static int 518 arm64_pcpu_fini(struct pmc_mdep *md, int cpu) 519 { 520 uint32_t pmcr; 521 522 pmcr = arm64_pmcr_read(); 523 pmcr &= ~PMCR_E; 524 arm64_pmcr_write(pmcr); 525 526 return (0); 527 } 528 529 struct pmc_mdep * 530 pmc_arm64_initialize(void) 531 { 532 struct pmc_mdep *pmc_mdep; 533 struct pmc_classdep *pcd; 534 int classes, idcode, impcode; 535 int reg; 536 uint64_t midr; 537 538 reg = arm64_pmcr_read(); 539 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; 540 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT; 541 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT; 542 543 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); 544 545 /* 546 * Write the CPU model to kern.hwpmc.cpuid. 547 * 548 * We zero the variant and revision fields. 549 * 550 * TODO: how to handle differences between cores due to big.LITTLE? 551 * For now, just use MIDR from CPU 0. 552 */ 553 midr = (uint64_t)(pcpu_find(0)->pc_midr); 554 midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); 555 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); 556 557 /* 558 * Allocate space for pointers to PMC HW descriptors and for 559 * the MDEP structure used by MI code. 560 */ 561 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(), 562 M_PMC, M_WAITOK | M_ZERO); 563 564 /* One AArch64 CPU class */ 565 classes = 1; 566 567 /* Query presence of optional classes and set max class. */ 568 if (pmc_cmn600_nclasses() > 0) 569 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_CMN600); 570 if (pmc_dmc620_nclasses() > 0) 571 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_DMC620_C); 572 573 pmc_mdep = pmc_mdep_alloc(classes); 574 575 switch(impcode) { 576 case PMCR_IMP_ARM: 577 switch (idcode) { 578 case PMCR_IDCODE_CORTEX_A76: 579 case PMCR_IDCODE_NEOVERSE_N1: 580 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76; 581 break; 582 case PMCR_IDCODE_CORTEX_A57: 583 case PMCR_IDCODE_CORTEX_A72: 584 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57; 585 break; 586 default: 587 case PMCR_IDCODE_CORTEX_A53: 588 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 589 break; 590 } 591 break; 592 default: 593 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 594 break; 595 } 596 597 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8]; 598 pcd->pcd_caps = ARMV8_PMC_CAPS; 599 pcd->pcd_class = PMC_CLASS_ARMV8; 600 pcd->pcd_num = arm64_npmcs; 601 pcd->pcd_ri = pmc_mdep->pmd_npmc; 602 pcd->pcd_width = 32; 603 604 pcd->pcd_allocate_pmc = arm64_allocate_pmc; 605 pcd->pcd_config_pmc = arm64_config_pmc; 606 pcd->pcd_pcpu_fini = arm64_pcpu_fini; 607 pcd->pcd_pcpu_init = arm64_pcpu_init; 608 pcd->pcd_describe = arm64_describe; 609 pcd->pcd_get_config = arm64_get_config; 610 pcd->pcd_read_pmc = arm64_read_pmc; 611 pcd->pcd_release_pmc = arm64_release_pmc; 612 pcd->pcd_start_pmc = arm64_start_pmc; 613 pcd->pcd_stop_pmc = arm64_stop_pmc; 614 pcd->pcd_write_pmc = arm64_write_pmc; 615 616 pmc_mdep->pmd_intr = arm64_intr; 617 pmc_mdep->pmd_switch_in = arm64_switch_in; 618 pmc_mdep->pmd_switch_out = arm64_switch_out; 619 620 pmc_mdep->pmd_npmc += arm64_npmcs; 621 622 if (pmc_cmn600_nclasses() > 0) 623 pmc_cmn600_initialize(pmc_mdep); 624 if (pmc_dmc620_nclasses() > 0) { 625 pmc_dmc620_initialize_cd2(pmc_mdep); 626 pmc_dmc620_initialize_c(pmc_mdep); 627 } 628 629 return (pmc_mdep); 630 } 631 632 void 633 pmc_arm64_finalize(struct pmc_mdep *md) 634 { 635 636 } 637