1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory with support from ARM Ltd. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/pmc.h> 36 #include <sys/pmckern.h> 37 38 #include <machine/pmc_mdep.h> 39 #include <machine/cpu.h> 40 41 static int arm64_npmcs; 42 43 struct arm64_event_code_map { 44 enum pmc_event pe_ev; 45 uint8_t pe_code; 46 }; 47 48 /* 49 * Per-processor information. 50 */ 51 struct arm64_cpu { 52 struct pmc_hw *pc_arm64pmcs; 53 }; 54 55 static struct arm64_cpu **arm64_pcpu; 56 57 /* 58 * Interrupt Enable Set Register 59 */ 60 static __inline void 61 arm64_interrupt_enable(uint32_t pmc) 62 { 63 uint32_t reg; 64 65 reg = (1 << pmc); 66 WRITE_SPECIALREG(pmintenset_el1, reg); 67 68 isb(); 69 } 70 71 /* 72 * Interrupt Clear Set Register 73 */ 74 static __inline void 75 arm64_interrupt_disable(uint32_t pmc) 76 { 77 uint32_t reg; 78 79 reg = (1 << pmc); 80 WRITE_SPECIALREG(pmintenclr_el1, reg); 81 82 isb(); 83 } 84 85 /* 86 * Counter Set Enable Register 87 */ 88 static __inline void 89 arm64_counter_enable(unsigned int pmc) 90 { 91 uint32_t reg; 92 93 reg = (1 << pmc); 94 WRITE_SPECIALREG(pmcntenset_el0, reg); 95 96 isb(); 97 } 98 99 /* 100 * Counter Clear Enable Register 101 */ 102 static __inline void 103 arm64_counter_disable(unsigned int pmc) 104 { 105 uint32_t reg; 106 107 reg = (1 << pmc); 108 WRITE_SPECIALREG(pmcntenclr_el0, reg); 109 110 isb(); 111 } 112 113 /* 114 * Performance Monitors Control Register 115 */ 116 static uint32_t 117 arm64_pmcr_read(void) 118 { 119 uint32_t reg; 120 121 reg = READ_SPECIALREG(pmcr_el0); 122 123 return (reg); 124 } 125 126 static void 127 arm64_pmcr_write(uint32_t reg) 128 { 129 130 WRITE_SPECIALREG(pmcr_el0, reg); 131 132 isb(); 133 } 134 135 /* 136 * Performance Count Register N 137 */ 138 static uint32_t 139 arm64_pmcn_read(unsigned int pmc) 140 { 141 142 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 143 144 WRITE_SPECIALREG(pmselr_el0, pmc); 145 146 isb(); 147 148 return (READ_SPECIALREG(pmxevcntr_el0)); 149 } 150 151 static void 152 arm64_pmcn_write(unsigned int pmc, uint32_t reg) 153 { 154 155 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 156 157 WRITE_SPECIALREG(pmselr_el0, pmc); 158 WRITE_SPECIALREG(pmxevcntr_el0, reg); 159 160 isb(); 161 } 162 163 static int 164 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm, 165 const struct pmc_op_pmcallocate *a) 166 { 167 uint32_t config; 168 struct arm64_cpu *pac; 169 enum pmc_event pe; 170 171 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 172 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 173 KASSERT(ri >= 0 && ri < arm64_npmcs, 174 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 175 176 pac = arm64_pcpu[cpu]; 177 178 if (a->pm_class != PMC_CLASS_ARMV8) { 179 return (EINVAL); 180 } 181 pe = a->pm_ev; 182 183 /* Adjust the config value if needed. */ 184 config = a->pm_md.pm_md_config; 185 if ((a->pm_md.pm_md_flags & PM_MD_RAW_EVENT) == 0) { 186 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST; 187 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST)) 188 return (EINVAL); 189 } 190 pm->pm_md.pm_arm64.pm_arm64_evsel = config; 191 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config); 192 193 return (0); 194 } 195 196 197 static int 198 arm64_read_pmc(int cpu, int ri, pmc_value_t *v) 199 { 200 pmc_value_t tmp; 201 struct pmc *pm; 202 register_t s; 203 int reg; 204 205 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 206 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 207 KASSERT(ri >= 0 && ri < arm64_npmcs, 208 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 209 210 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 211 212 /* 213 * Ensure we don't get interrupted while updating the overflow count. 214 */ 215 s = intr_disable(); 216 tmp = arm64_pmcn_read(ri); 217 reg = (1 << ri); 218 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) { 219 /* Clear Overflow Flag */ 220 WRITE_SPECIALREG(pmovsclr_el0, reg); 221 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 222 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 223 224 /* Reread counter in case we raced. */ 225 tmp = arm64_pmcn_read(ri); 226 } 227 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 228 intr_restore(s); 229 230 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); 231 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 232 *v = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 233 else 234 *v = tmp; 235 236 return (0); 237 } 238 239 static int 240 arm64_write_pmc(int cpu, int ri, pmc_value_t v) 241 { 242 struct pmc *pm; 243 244 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 245 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 246 KASSERT(ri >= 0 && ri < arm64_npmcs, 247 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 248 249 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 250 251 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 252 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 253 254 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); 255 256 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 257 arm64_pmcn_write(ri, v); 258 259 return (0); 260 } 261 262 static int 263 arm64_config_pmc(int cpu, int ri, struct pmc *pm) 264 { 265 struct pmc_hw *phw; 266 267 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 268 269 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 270 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 271 KASSERT(ri >= 0 && ri < arm64_npmcs, 272 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 273 274 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 275 276 KASSERT(pm == NULL || phw->phw_pmc == NULL, 277 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 278 __LINE__, pm, phw->phw_pmc)); 279 280 phw->phw_pmc = pm; 281 282 return (0); 283 } 284 285 static int 286 arm64_start_pmc(int cpu, int ri) 287 { 288 struct pmc_hw *phw; 289 uint32_t config; 290 struct pmc *pm; 291 292 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 293 pm = phw->phw_pmc; 294 config = pm->pm_md.pm_arm64.pm_arm64_evsel; 295 296 /* 297 * Configure the event selection. 298 */ 299 WRITE_SPECIALREG(pmselr_el0, ri); 300 WRITE_SPECIALREG(pmxevtyper_el0, config); 301 302 isb(); 303 304 /* 305 * Enable the PMC. 306 */ 307 arm64_interrupt_enable(ri); 308 arm64_counter_enable(ri); 309 310 return (0); 311 } 312 313 static int 314 arm64_stop_pmc(int cpu, int ri) 315 { 316 struct pmc_hw *phw; 317 struct pmc *pm; 318 319 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 320 pm = phw->phw_pmc; 321 322 /* 323 * Disable the PMCs. 324 */ 325 arm64_counter_disable(ri); 326 arm64_interrupt_disable(ri); 327 328 return (0); 329 } 330 331 static int 332 arm64_release_pmc(int cpu, int ri, struct pmc *pmc) 333 { 334 struct pmc_hw *phw; 335 336 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 337 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 338 KASSERT(ri >= 0 && ri < arm64_npmcs, 339 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 340 341 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 342 KASSERT(phw->phw_pmc == NULL, 343 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 344 345 return (0); 346 } 347 348 static int 349 arm64_intr(struct trapframe *tf) 350 { 351 struct arm64_cpu *pc; 352 int retval, ri; 353 struct pmc *pm; 354 int error; 355 int reg, cpu; 356 357 cpu = curcpu; 358 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 359 ("[arm64,%d] CPU %d out of range", __LINE__, cpu)); 360 361 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf, 362 TRAPF_USERMODE(tf)); 363 364 retval = 0; 365 pc = arm64_pcpu[cpu]; 366 367 for (ri = 0; ri < arm64_npmcs; ri++) { 368 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 369 if (pm == NULL) 370 continue; 371 /* Check if counter is overflowed */ 372 reg = (1 << ri); 373 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) 374 continue; 375 /* Clear Overflow Flag */ 376 WRITE_SPECIALREG(pmovsclr_el0, reg); 377 378 isb(); 379 380 retval = 1; /* Found an interrupting PMC. */ 381 382 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 383 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 384 continue; 385 } 386 387 if (pm->pm_state != PMC_STATE_RUNNING) 388 continue; 389 390 error = pmc_process_interrupt(PMC_HR, pm, tf); 391 if (error) 392 arm64_stop_pmc(cpu, ri); 393 394 /* Reload sampling count */ 395 arm64_write_pmc(cpu, ri, pm->pm_sc.pm_reloadcount); 396 } 397 398 return (retval); 399 } 400 401 static int 402 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 403 { 404 char arm64_name[PMC_NAME_MAX]; 405 struct pmc_hw *phw; 406 int error; 407 408 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 409 ("[arm64,%d], illegal CPU %d", __LINE__, cpu)); 410 KASSERT(ri >= 0 && ri < arm64_npmcs, 411 ("[arm64,%d] row-index %d out of range", __LINE__, ri)); 412 413 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 414 snprintf(arm64_name, sizeof(arm64_name), "ARMV8-%d", ri); 415 if ((error = copystr(arm64_name, pi->pm_name, PMC_NAME_MAX, 416 NULL)) != 0) 417 return (error); 418 pi->pm_class = PMC_CLASS_ARMV8; 419 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 420 pi->pm_enabled = TRUE; 421 *ppmc = phw->phw_pmc; 422 } else { 423 pi->pm_enabled = FALSE; 424 *ppmc = NULL; 425 } 426 427 return (0); 428 } 429 430 static int 431 arm64_get_config(int cpu, int ri, struct pmc **ppm) 432 { 433 434 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 435 436 return (0); 437 } 438 439 /* 440 * XXX don't know what we should do here. 441 */ 442 static int 443 arm64_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 444 { 445 446 return (0); 447 } 448 449 static int 450 arm64_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 451 { 452 453 return (0); 454 } 455 456 static int 457 arm64_pcpu_init(struct pmc_mdep *md, int cpu) 458 { 459 struct arm64_cpu *pac; 460 struct pmc_hw *phw; 461 struct pmc_cpu *pc; 462 uint64_t pmcr; 463 int first_ri; 464 int i; 465 466 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 467 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu)); 468 PMCDBG1(MDP, INI, 1, "arm64-init cpu=%d", cpu); 469 470 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC, 471 M_WAITOK | M_ZERO); 472 473 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs, 474 M_PMC, M_WAITOK | M_ZERO); 475 pc = pmc_pcpu[cpu]; 476 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri; 477 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__)); 478 479 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) { 480 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 481 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 482 phw->phw_pmc = NULL; 483 pc->pc_hwpmcs[i + first_ri] = phw; 484 } 485 486 /* 487 * Disable all counters and overflow interrupts. Upon reset they are in 488 * an undefined state. 489 * 490 * Don't issue an isb here, just wait for the one in arm64_pmcr_write() 491 * to make the writes visible. 492 */ 493 WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff); 494 WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff); 495 496 /* Enable unit */ 497 pmcr = arm64_pmcr_read(); 498 pmcr |= PMCR_E; 499 arm64_pmcr_write(pmcr); 500 501 return (0); 502 } 503 504 static int 505 arm64_pcpu_fini(struct pmc_mdep *md, int cpu) 506 { 507 uint32_t pmcr; 508 509 pmcr = arm64_pmcr_read(); 510 pmcr &= ~PMCR_E; 511 arm64_pmcr_write(pmcr); 512 513 return (0); 514 } 515 516 struct pmc_mdep * 517 pmc_arm64_initialize() 518 { 519 struct pmc_mdep *pmc_mdep; 520 struct pmc_classdep *pcd; 521 int idcode, impcode; 522 int reg; 523 uint64_t midr; 524 525 reg = arm64_pmcr_read(); 526 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; 527 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT; 528 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT; 529 530 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); 531 532 /* 533 * Write the CPU model to kern.hwpmc.cpuid. 534 * 535 * We zero the variant and revision fields. 536 * 537 * TODO: how to handle differences between cores due to big.LITTLE? 538 * For now, just use MIDR from CPU 0. 539 */ 540 midr = (uint64_t)(pcpu_find(0)->pc_midr); 541 midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); 542 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); 543 544 /* 545 * Allocate space for pointers to PMC HW descriptors and for 546 * the MDEP structure used by MI code. 547 */ 548 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(), 549 M_PMC, M_WAITOK | M_ZERO); 550 551 /* Just one class */ 552 pmc_mdep = pmc_mdep_alloc(1); 553 554 switch(impcode) { 555 case PMCR_IMP_ARM: 556 switch (idcode) { 557 case PMCR_IDCODE_CORTEX_A76: 558 case PMCR_IDCODE_NEOVERSE_N1: 559 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76; 560 break; 561 case PMCR_IDCODE_CORTEX_A57: 562 case PMCR_IDCODE_CORTEX_A72: 563 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57; 564 break; 565 default: 566 case PMCR_IDCODE_CORTEX_A53: 567 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 568 break; 569 } 570 break; 571 default: 572 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 573 break; 574 } 575 576 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8]; 577 pcd->pcd_caps = ARMV8_PMC_CAPS; 578 pcd->pcd_class = PMC_CLASS_ARMV8; 579 pcd->pcd_num = arm64_npmcs; 580 pcd->pcd_ri = pmc_mdep->pmd_npmc; 581 pcd->pcd_width = 32; 582 583 pcd->pcd_allocate_pmc = arm64_allocate_pmc; 584 pcd->pcd_config_pmc = arm64_config_pmc; 585 pcd->pcd_pcpu_fini = arm64_pcpu_fini; 586 pcd->pcd_pcpu_init = arm64_pcpu_init; 587 pcd->pcd_describe = arm64_describe; 588 pcd->pcd_get_config = arm64_get_config; 589 pcd->pcd_read_pmc = arm64_read_pmc; 590 pcd->pcd_release_pmc = arm64_release_pmc; 591 pcd->pcd_start_pmc = arm64_start_pmc; 592 pcd->pcd_stop_pmc = arm64_stop_pmc; 593 pcd->pcd_write_pmc = arm64_write_pmc; 594 595 pmc_mdep->pmd_intr = arm64_intr; 596 pmc_mdep->pmd_switch_in = arm64_switch_in; 597 pmc_mdep->pmd_switch_out = arm64_switch_out; 598 599 pmc_mdep->pmd_npmc += arm64_npmcs; 600 601 return (pmc_mdep); 602 } 603 604 void 605 pmc_arm64_finalize(struct pmc_mdep *md) 606 { 607 608 } 609