1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by the University of Cambridge Computer 6 * Laboratory with support from ARM Ltd. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/pmc.h> 33 #include <sys/pmckern.h> 34 35 #include <machine/pmc_mdep.h> 36 #include <machine/cpu.h> 37 38 #include "opt_acpi.h" 39 40 static int arm64_npmcs; 41 42 struct arm64_event_code_map { 43 enum pmc_event pe_ev; 44 uint8_t pe_code; 45 }; 46 47 /* 48 * Per-processor information. 49 */ 50 struct arm64_cpu { 51 struct pmc_hw *pc_arm64pmcs; 52 }; 53 54 static struct arm64_cpu **arm64_pcpu; 55 56 /* 57 * Interrupt Enable Set Register 58 */ 59 static __inline void 60 arm64_interrupt_enable(uint32_t pmc) 61 { 62 uint32_t reg; 63 64 reg = (1 << pmc); 65 WRITE_SPECIALREG(pmintenset_el1, reg); 66 67 isb(); 68 } 69 70 /* 71 * Interrupt Clear Set Register 72 */ 73 static __inline void 74 arm64_interrupt_disable(uint32_t pmc) 75 { 76 uint32_t reg; 77 78 reg = (1 << pmc); 79 WRITE_SPECIALREG(pmintenclr_el1, reg); 80 81 isb(); 82 } 83 84 /* 85 * Counter Set Enable Register 86 */ 87 static __inline void 88 arm64_counter_enable(unsigned int pmc) 89 { 90 uint32_t reg; 91 92 reg = (1 << pmc); 93 WRITE_SPECIALREG(pmcntenset_el0, reg); 94 95 isb(); 96 } 97 98 /* 99 * Counter Clear Enable Register 100 */ 101 static __inline void 102 arm64_counter_disable(unsigned int pmc) 103 { 104 uint32_t reg; 105 106 reg = (1 << pmc); 107 WRITE_SPECIALREG(pmcntenclr_el0, reg); 108 109 isb(); 110 } 111 112 /* 113 * Performance Monitors Control Register 114 */ 115 static uint32_t 116 arm64_pmcr_read(void) 117 { 118 uint32_t reg; 119 120 reg = READ_SPECIALREG(pmcr_el0); 121 122 return (reg); 123 } 124 125 static void 126 arm64_pmcr_write(uint32_t reg) 127 { 128 129 WRITE_SPECIALREG(pmcr_el0, reg); 130 131 isb(); 132 } 133 134 /* 135 * Performance Count Register N 136 */ 137 static uint32_t 138 arm64_pmcn_read(unsigned int pmc) 139 { 140 141 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 142 143 WRITE_SPECIALREG(pmselr_el0, pmc); 144 145 isb(); 146 147 return (READ_SPECIALREG(pmxevcntr_el0)); 148 } 149 150 static void 151 arm64_pmcn_write(unsigned int pmc, uint32_t reg) 152 { 153 154 KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc)); 155 156 WRITE_SPECIALREG(pmselr_el0, pmc); 157 WRITE_SPECIALREG(pmxevcntr_el0, reg); 158 159 isb(); 160 } 161 162 static int 163 arm64_allocate_pmc(int cpu, int ri, struct pmc *pm, 164 const struct pmc_op_pmcallocate *a) 165 { 166 uint32_t config; 167 enum pmc_event pe; 168 169 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 170 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 171 KASSERT(ri >= 0 && ri < arm64_npmcs, 172 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 173 174 if (a->pm_class != PMC_CLASS_ARMV8) { 175 return (EINVAL); 176 } 177 pe = a->pm_ev; 178 179 if ((a->pm_flags & PMC_F_EV_PMU) != 0) { 180 config = a->pm_md.pm_md_config; 181 } else { 182 config = (uint32_t)pe - PMC_EV_ARMV8_FIRST; 183 if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST)) 184 return (EINVAL); 185 } 186 187 switch (a->pm_caps & (PMC_CAP_SYSTEM | PMC_CAP_USER)) { 188 case PMC_CAP_SYSTEM: 189 config |= PMEVTYPER_U; 190 break; 191 case PMC_CAP_USER: 192 config |= PMEVTYPER_P; 193 break; 194 default: 195 /* 196 * Trace both USER and SYSTEM if none are specified 197 * (default setting) or if both flags are specified 198 * (user explicitly requested both qualifiers). 199 */ 200 break; 201 } 202 203 pm->pm_md.pm_arm64.pm_arm64_evsel = config; 204 PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config); 205 206 return (0); 207 } 208 209 210 static int 211 arm64_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v) 212 { 213 pmc_value_t tmp; 214 register_t s; 215 int reg; 216 217 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 218 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 219 KASSERT(ri >= 0 && ri < arm64_npmcs, 220 ("[arm64,%d] illegal row index %d", __LINE__, ri)); 221 222 /* 223 * Ensure we don't get interrupted while updating the overflow count. 224 */ 225 s = intr_disable(); 226 tmp = arm64_pmcn_read(ri); 227 reg = (1 << ri); 228 if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) { 229 /* Clear Overflow Flag */ 230 WRITE_SPECIALREG(pmovsclr_el0, reg); 231 pm->pm_pcpu_state[cpu].pps_overflowcnt++; 232 233 /* Reread counter in case we raced. */ 234 tmp = arm64_pmcn_read(ri); 235 } 236 tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt; 237 intr_restore(s); 238 239 PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp); 240 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 241 /* 242 * Clamp value to 0 if the counter just overflowed, 243 * otherwise the returned reload count would wrap to a 244 * huge value. 245 */ 246 if ((tmp & (1ull << 63)) == 0) 247 tmp = 0; 248 else 249 tmp = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 250 } 251 *v = tmp; 252 253 return (0); 254 } 255 256 static int 257 arm64_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v) 258 { 259 260 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 261 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 262 KASSERT(ri >= 0 && ri < arm64_npmcs, 263 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 264 265 if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 266 v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 267 268 PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v); 269 270 pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32; 271 arm64_pmcn_write(ri, v); 272 273 return (0); 274 } 275 276 static int 277 arm64_config_pmc(int cpu, int ri, struct pmc *pm) 278 { 279 struct pmc_hw *phw; 280 281 PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 282 283 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 284 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 285 KASSERT(ri >= 0 && ri < arm64_npmcs, 286 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 287 288 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 289 290 KASSERT(pm == NULL || phw->phw_pmc == NULL, 291 ("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 292 __LINE__, pm, phw->phw_pmc)); 293 294 phw->phw_pmc = pm; 295 296 return (0); 297 } 298 299 static int 300 arm64_start_pmc(int cpu, int ri, struct pmc *pm) 301 { 302 uint32_t config; 303 304 config = pm->pm_md.pm_arm64.pm_arm64_evsel; 305 306 /* 307 * Configure the event selection. 308 */ 309 WRITE_SPECIALREG(pmselr_el0, ri); 310 WRITE_SPECIALREG(pmxevtyper_el0, config); 311 312 isb(); 313 314 /* 315 * Enable the PMC. 316 */ 317 arm64_interrupt_enable(ri); 318 arm64_counter_enable(ri); 319 320 return (0); 321 } 322 323 static int 324 arm64_stop_pmc(int cpu, int ri, struct pmc *pm __unused) 325 { 326 /* 327 * Disable the PMCs. 328 */ 329 arm64_counter_disable(ri); 330 arm64_interrupt_disable(ri); 331 332 return (0); 333 } 334 335 static int 336 arm64_release_pmc(int cpu, int ri, struct pmc *pmc) 337 { 338 struct pmc_hw *phw __diagused; 339 340 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 341 ("[arm64,%d] illegal CPU value %d", __LINE__, cpu)); 342 KASSERT(ri >= 0 && ri < arm64_npmcs, 343 ("[arm64,%d] illegal row-index %d", __LINE__, ri)); 344 345 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 346 KASSERT(phw->phw_pmc == NULL, 347 ("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 348 349 return (0); 350 } 351 352 static int 353 arm64_intr(struct trapframe *tf) 354 { 355 int retval, ri; 356 struct pmc *pm; 357 int error; 358 int reg, cpu; 359 360 cpu = curcpu; 361 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 362 ("[arm64,%d] CPU %d out of range", __LINE__, cpu)); 363 364 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf, 365 TRAPF_USERMODE(tf)); 366 367 retval = 0; 368 369 for (ri = 0; ri < arm64_npmcs; ri++) { 370 pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 371 if (pm == NULL) 372 continue; 373 /* Check if counter is overflowed */ 374 reg = (1 << ri); 375 if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0) 376 continue; 377 /* Clear Overflow Flag */ 378 WRITE_SPECIALREG(pmovsclr_el0, reg); 379 380 isb(); 381 382 retval = 1; /* Found an interrupting PMC. */ 383 384 pm->pm_pcpu_state[cpu].pps_overflowcnt += 1; 385 386 if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) 387 continue; 388 389 if (pm->pm_state != PMC_STATE_RUNNING) 390 continue; 391 392 error = pmc_process_interrupt(PMC_HR, pm, tf); 393 if (error) 394 arm64_stop_pmc(cpu, ri, pm); 395 396 /* Reload sampling count */ 397 arm64_write_pmc(cpu, ri, pm, pm->pm_sc.pm_reloadcount); 398 } 399 400 return (retval); 401 } 402 403 static int 404 arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 405 { 406 struct pmc_hw *phw; 407 408 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 409 ("[arm64,%d], illegal CPU %d", __LINE__, cpu)); 410 KASSERT(ri >= 0 && ri < arm64_npmcs, 411 ("[arm64,%d] row-index %d out of range", __LINE__, ri)); 412 413 phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri]; 414 415 snprintf(pi->pm_name, sizeof(pi->pm_name), "ARMV8-%d", ri); 416 pi->pm_class = PMC_CLASS_ARMV8; 417 418 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 419 pi->pm_enabled = TRUE; 420 *ppmc = phw->phw_pmc; 421 } else { 422 pi->pm_enabled = FALSE; 423 *ppmc = NULL; 424 } 425 426 return (0); 427 } 428 429 static int 430 arm64_get_config(int cpu, int ri, struct pmc **ppm) 431 { 432 433 *ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc; 434 435 return (0); 436 } 437 438 static int 439 arm64_pcpu_init(struct pmc_mdep *md, int cpu) 440 { 441 struct arm64_cpu *pac; 442 struct pmc_hw *phw; 443 struct pmc_cpu *pc; 444 uint64_t pmcr; 445 int first_ri; 446 int i; 447 448 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 449 ("[arm64,%d] wrong cpu number %d", __LINE__, cpu)); 450 PMCDBG0(MDP, INI, 1, "arm64-pcpu-init"); 451 452 arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC, 453 M_WAITOK | M_ZERO); 454 455 pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs, 456 M_PMC, M_WAITOK | M_ZERO); 457 pc = pmc_pcpu[cpu]; 458 first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri; 459 KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__)); 460 461 for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) { 462 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 463 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i); 464 phw->phw_pmc = NULL; 465 pc->pc_hwpmcs[i + first_ri] = phw; 466 } 467 468 /* 469 * Disable all counters and overflow interrupts. Upon reset they are in 470 * an undefined state. 471 * 472 * Don't issue an isb here, just wait for the one in arm64_pmcr_write() 473 * to make the writes visible. 474 */ 475 WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff); 476 WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff); 477 478 /* Enable unit */ 479 pmcr = arm64_pmcr_read(); 480 pmcr |= PMCR_E; 481 arm64_pmcr_write(pmcr); 482 483 return (0); 484 } 485 486 static int 487 arm64_pcpu_fini(struct pmc_mdep *md, int cpu) 488 { 489 uint32_t pmcr; 490 491 PMCDBG0(MDP, INI, 1, "arm64-pcpu-fini"); 492 493 pmcr = arm64_pmcr_read(); 494 pmcr &= ~PMCR_E; 495 arm64_pmcr_write(pmcr); 496 497 free(arm64_pcpu[cpu]->pc_arm64pmcs, M_PMC); 498 free(arm64_pcpu[cpu], M_PMC); 499 arm64_pcpu[cpu] = NULL; 500 501 return (0); 502 } 503 504 struct pmc_mdep * 505 pmc_arm64_initialize(void) 506 { 507 struct pmc_mdep *pmc_mdep; 508 struct pmc_classdep *pcd; 509 int classes, idcode, impcode; 510 int reg; 511 uint64_t midr; 512 513 reg = arm64_pmcr_read(); 514 arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT; 515 impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT; 516 idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT; 517 518 PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs); 519 520 /* 521 * Write the CPU model to kern.hwpmc.cpuid. 522 * 523 * We zero the variant and revision fields. 524 * 525 * TODO: how to handle differences between cores due to big.LITTLE? 526 * For now, just use MIDR from CPU 0. 527 */ 528 midr = (uint64_t)(pcpu_find(0)->pc_midr); 529 midr &= ~(CPU_VAR_MASK | CPU_REV_MASK); 530 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr); 531 532 /* 533 * Allocate space for pointers to PMC HW descriptors and for 534 * the MDEP structure used by MI code. 535 */ 536 arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(), 537 M_PMC, M_WAITOK | M_ZERO); 538 539 /* One AArch64 CPU class */ 540 classes = 1; 541 542 #ifdef DEV_ACPI 543 /* Query presence of optional classes and set max class. */ 544 if (pmc_cmn600_nclasses() > 0) 545 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_CMN600); 546 if (pmc_dmc620_nclasses() > 0) 547 classes = MAX(classes, PMC_MDEP_CLASS_INDEX_DMC620_C); 548 #endif 549 550 pmc_mdep = pmc_mdep_alloc(classes); 551 552 switch(impcode) { 553 case PMCR_IMP_ARM: 554 switch (idcode) { 555 case PMCR_IDCODE_CORTEX_A76: 556 case PMCR_IDCODE_NEOVERSE_N1: 557 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76; 558 break; 559 case PMCR_IDCODE_CORTEX_A57: 560 case PMCR_IDCODE_CORTEX_A72: 561 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57; 562 break; 563 default: 564 case PMCR_IDCODE_CORTEX_A53: 565 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 566 break; 567 } 568 break; 569 default: 570 pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53; 571 break; 572 } 573 574 pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8]; 575 pcd->pcd_caps = ARMV8_PMC_CAPS; 576 pcd->pcd_class = PMC_CLASS_ARMV8; 577 pcd->pcd_num = arm64_npmcs; 578 pcd->pcd_ri = pmc_mdep->pmd_npmc; 579 pcd->pcd_width = 32; 580 581 pcd->pcd_allocate_pmc = arm64_allocate_pmc; 582 pcd->pcd_config_pmc = arm64_config_pmc; 583 pcd->pcd_pcpu_fini = arm64_pcpu_fini; 584 pcd->pcd_pcpu_init = arm64_pcpu_init; 585 pcd->pcd_describe = arm64_describe; 586 pcd->pcd_get_config = arm64_get_config; 587 pcd->pcd_read_pmc = arm64_read_pmc; 588 pcd->pcd_release_pmc = arm64_release_pmc; 589 pcd->pcd_start_pmc = arm64_start_pmc; 590 pcd->pcd_stop_pmc = arm64_stop_pmc; 591 pcd->pcd_write_pmc = arm64_write_pmc; 592 593 pmc_mdep->pmd_intr = arm64_intr; 594 pmc_mdep->pmd_npmc += arm64_npmcs; 595 596 #ifdef DEV_ACPI 597 if (pmc_cmn600_nclasses() > 0) 598 pmc_cmn600_initialize(pmc_mdep); 599 if (pmc_dmc620_nclasses() > 0) { 600 pmc_dmc620_initialize_cd2(pmc_mdep); 601 pmc_dmc620_initialize_c(pmc_mdep); 602 } 603 #endif 604 605 return (pmc_mdep); 606 } 607 608 void 609 pmc_arm64_finalize(struct pmc_mdep *md) 610 { 611 PMCDBG0(MDP, INI, 1, "arm64-finalize"); 612 613 for (int i = 0; i < pmc_cpu_max(); i++) 614 KASSERT(arm64_pcpu[i] == NULL, 615 ("[arm64,%d] non-null pcpu cpu %d", __LINE__, i)); 616 617 free(arm64_pcpu, M_PMC); 618 } 619