1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005, Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Machine dependent interfaces */ 30 31 #ifndef _DEV_HWPMC_AMD_H_ 32 #define _DEV_HWPMC_AMD_H_ 1 33 34 /* CPUIDs */ 35 #define CPUID_EXTPERFMON 0x80000022 36 #define EXTPERFMON_CORE_PMCS(x) ((x) & 0x0F) 37 #define EXTPERFMON_DF_PMCS(x) (((x) >> 10) & 0x3F) 38 39 /* AMD K8 PMCs */ 40 #define AMD_PMC_EVSEL_0 0xC0010000 41 #define AMD_PMC_EVSEL_1 0xC0010001 42 #define AMD_PMC_EVSEL_2 0xC0010002 43 #define AMD_PMC_EVSEL_3 0xC0010003 44 45 #define AMD_PMC_PERFCTR_0 0xC0010004 46 #define AMD_PMC_PERFCTR_1 0xC0010005 47 #define AMD_PMC_PERFCTR_2 0xC0010006 48 #define AMD_PMC_PERFCTR_3 0xC0010007 49 50 /* 51 * For older AMD processors we have hard coded the original four core counters. 52 * For newer processors we use the cpuid bits to setup the counter table. The 53 * counts below are the default number of registers assuming that you do not 54 * have CPUID leaf 0x80000022. The maximum number of counters is computed 55 * based on the available bits in the CPUID leaf and reserved MSR space. 56 * 57 * Refer to the PPRs for AMD Family 1Ah. 58 */ 59 60 /* CORE */ 61 #define AMD_PMC_CORE_BASE 0xC0010200 62 #define AMD_PMC_CORE_DEFAULT 6 63 #define AMD_PMC_CORE_MAX 16 64 65 /* L3 */ 66 #define AMD_PMC_L3_BASE 0xC0010230 67 #define AMD_PMC_L3_DEFAULT 6 68 #define AMD_PMC_L3_MAX 6 69 70 /* DF */ 71 #define AMD_PMC_DF_BASE 0xC0010240 72 #define AMD_PMC_DF_DEFAULT 4 73 #define AMD_PMC_DF_MAX 64 74 75 #define AMD_NPMCS_K8 4 76 #define AMD_NPMCS_MAX (AMD_PMC_CORE_MAX + AMD_PMC_L3_MAX + \ 77 AMD_PMC_DF_MAX) 78 79 #define AMD_PMC_COUNTERMASK 0xFF000000 80 #define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK) 81 #define AMD_PMC_INVERT (1 << 23) 82 #define AMD_PMC_ENABLE (1 << 22) 83 #define AMD_PMC_INT (1 << 20) 84 #define AMD_PMC_PC (1 << 19) 85 #define AMD_PMC_EDGE (1 << 18) 86 #define AMD_PMC_OS (1 << 17) 87 #define AMD_PMC_USR (1 << 16) 88 #define AMD_PMC_L3SLICEMASK (0x000F000000000000) 89 #define AMD_PMC_L3COREMASK (0xFF00000000000000) 90 #define AMD_PMC_TO_L3SLICE(x) (((x) << 48) & AMD_PMC_L3SLICEMASK) 91 #define AMD_PMC_TO_L3CORE(x) (((x) << 56) & AMD_PMC_L3COREMASK) 92 93 #define AMD_PMC_UNITMASK_M 0x10 94 #define AMD_PMC_UNITMASK_O 0x08 95 #define AMD_PMC_UNITMASK_E 0x04 96 #define AMD_PMC_UNITMASK_S 0x02 97 #define AMD_PMC_UNITMASK_I 0x01 98 #define AMD_PMC_UNITMASK_MOESI 0x1F 99 100 #define AMD_PMC_UNITMASK 0xFF00 101 #define AMD_PMC_EVENTMASK 0xF000000FF 102 103 #define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 104 #define AMD_PMC_TO_EVENTMASK(x) (((x) & 0xFF) | (((uint64_t)(x) & 0xF00) << 24)) 105 #define AMD_PMC_TO_EVENTMASK_DF(x) (((x) & 0xFF) | (((uint64_t)(x) & 0x0F00) << 24)) | (((uint64_t)(x) & 0x3000) << 47) 106 #define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \ 107 AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \ 108 AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK) 109 110 #define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \ 111 PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \ 112 PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER) 113 114 #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0) 115 #define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0) 116 117 #define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V)) 118 #define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) 119 120 enum sub_class { 121 PMC_AMD_SUB_CLASS_CORE, 122 PMC_AMD_SUB_CLASS_L3_CACHE, 123 PMC_AMD_SUB_CLASS_DATA_FABRIC 124 }; 125 126 struct pmc_md_amd_op_pmcallocate { 127 uint64_t pm_amd_config; 128 uint32_t pm_amd_sub_class; 129 }; 130 131 #ifdef _KERNEL 132 133 /* MD extension for 'struct pmc' */ 134 struct pmc_md_amd_pmc { 135 uint64_t pm_amd_evsel; 136 }; 137 138 #endif /* _KERNEL */ 139 #endif /* _DEV_HWPMC_AMD_H_ */ 140