1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005, Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Machine dependent interfaces */ 30 31 #ifndef _DEV_HWPMC_AMD_H_ 32 #define _DEV_HWPMC_AMD_H_ 1 33 34 /* CPUIDs */ 35 #define CPUID_EXTPERFMON 0x80000022 36 #define EXTPERFMON_CORE_PMCS(x) ((x) & 0x0F) 37 #define EXTPERFMON_DF_PMCS(x) (((x) >> 10) & 0x3F) 38 #define EXTPERFMON_UMC_PMCS(x) (((x) >> 16) & 0xFF) 39 #define EXTPERFMON_PERFMONV2(x) ((x) & 0x1) 40 41 /* AMD K8 PMCs */ 42 #define AMD_PMC_EVSEL_0 0xC0010000 43 #define AMD_PMC_EVSEL_1 0xC0010001 44 #define AMD_PMC_EVSEL_2 0xC0010002 45 #define AMD_PMC_EVSEL_3 0xC0010003 46 47 #define AMD_PMC_PERFCTR_0 0xC0010004 48 #define AMD_PMC_PERFCTR_1 0xC0010005 49 #define AMD_PMC_PERFCTR_2 0xC0010006 50 #define AMD_PMC_PERFCTR_3 0xC0010007 51 52 /* 53 * For older AMD processors we have hard coded the original four core counters. 54 * For newer processors we use the cpuid bits to setup the counter table. The 55 * counts below are the default number of registers assuming that you do not 56 * have CPUID leaf 0x80000022. The maximum number of counters is computed 57 * based on the available bits in the CPUID leaf and reserved MSR space. 58 * 59 * Refer to the PPRs for AMD Family 1Ah. 60 */ 61 62 /* CORE */ 63 #define AMD_PMC_CORE_BASE 0xC0010200 64 #define AMD_PMC_CORE_DEFAULT 6 65 #define AMD_PMC_CORE_MAX 16 66 67 /* 68 * These are the PerfMonV2 global-control MSRs (Fam 19h Zen3+ / 1Ah). 69 * They control core counters only. L3 and DF counters keep the 70 * classic per-counter path. 71 */ 72 #define AMD_PMC_GLOBAL_STATUS 0xC0000300 /* RO */ 73 #define AMD_PMC_GLOBAL_CTL 0xC0000301 /* RW */ 74 #define AMD_PMC_GLOBAL_STATUS_CLR 0xC0000302 /* WO */ 75 /* A future LBR v2 change adds GLOBAL_STATUS.LBRS_FROZEN (bit 58) here. */ 76 77 #define AMD_PMC_COUNTERMASK 0xFF000000 78 #define AMD_PMC_PRECISERETIRE (1ULL << 43) /* Only valid for PERF_CTL2 */ 79 #define AMD_PMC_HOST (1ULL << 41) 80 #define AMD_PMC_GUEST (1ULL << 40) 81 #define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK) 82 #define AMD_PMC_INVERT (1 << 23) 83 #define AMD_PMC_ENABLE (1 << 22) 84 #define AMD_PMC_INT (1 << 20) 85 #define AMD_PMC_PC (1 << 19) 86 #define AMD_PMC_EDGE (1 << 18) 87 #define AMD_PMC_OS (1 << 17) 88 #define AMD_PMC_USR (1 << 16) 89 90 #define AMD_PMC_UNITMASK 0xFF00 91 #define AMD_PMC_EVENTMASK 0xF000000FF 92 93 #define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 94 #define AMD_PMC_TO_EVENTMASK(x) (((x) & 0xFF) | (((uint64_t)(x) & 0xF00) << 24)) 95 96 #define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \ 97 AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \ 98 AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK) 99 100 #define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \ 101 PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \ 102 PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER) 103 104 /* L3 */ 105 #define AMD_PMC_L3_BASE 0xC0010230 106 #define AMD_PMC_L3_DEFAULT 6 107 #define AMD_PMC_L3_MAX 6 108 109 /* 110 * L3 counters change their encoding slightly between Family 17h and Family 19h 111 * processors. 112 * 113 * Refer to the following documents for the L3 fields: 114 * PPR for AMD Family 17h Model 20h A1 55772-A1 Rev. 3.08 April 14, 2021 115 * PPR for AMD Family 19h Model 51h A1 56569-A1 Rev. 3.03 September 21, 2021 116 * PPR for AMD Family 1Ah Model 02h C1 57238 Rev. 0.24 September 29, 2024 117 */ 118 #define AMD_PMC_L31_SLICEMASK (0x000F000000000000ULL) 119 #define AMD_PMC_L31_COREMASK (0xFF00000000000000ULL) 120 121 #define AMD_PMC_L31_TO_SLICE(x) (((uint64_t)(x) << 48) & AMD_PMC_L31_SLICEMASK) 122 #define AMD_PMC_L31_TO_CORE(x) (((uint64_t)(x) << 56) & AMD_PMC_L31_COREMASK) 123 124 #define AMD_PMC_L32_THREADMASK (0x0F00000000000000ULL) 125 #define AMD_PMC_L32_SOURCEMASK (0x0007000000000000ULL) 126 #define AMD_PMC_L32_ALLCORES (1ULL << 47) 127 #define AMD_PMC_L32_ALLSOURCES (1ULL << 46) 128 #define AMD_PMC_L32_COREMASK (0x00001C0000000000ULL) 129 130 #define AMD_PMC_L32_TO_THREAD(x) (((uint64_t)(x) << 56) & AMD_PMC_L32_THREADMASK) 131 #define AMD_PMC_L32_TO_SOURCEID(x) (((uint64_t)(x) << 48) & AMD_PMC_L32_SOURCEMASK) 132 #define AMD_PMC_L32_TO_COREID(x) (((uint64_t)(x) << 42) & AMD_PMC_L32_COREMASK) 133 134 #define AMD_PMC_L3_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 135 #define AMD_PMC_L3_TO_EVENTMASK(x) ((x) & 0xFF) 136 137 #define AMD_PMC_L3_FAMILY17_MASK \ 138 (AMD_PMC_ENABLE | AMD_PMC_L3_TO_EVENTMASK(0xff) | \ 139 AMD_PMC_L3_TO_UNITMASK(0xff) | \ 140 AMD_PMC_L31_SLICEMASK | AMD_PMC_L31_COREMASK) 141 142 #define AMD_PMC_L3_FAMILY19_MASK \ 143 (AMD_PMC_ENABLE | AMD_PMC_L3_TO_EVENTMASK(0xff) | \ 144 AMD_PMC_L3_TO_UNITMASK(0xff) | \ 145 AMD_PMC_L32_THREADMASK | AMD_PMC_L32_SOURCEMASK | \ 146 AMD_PMC_L32_ALLCORES | AMD_PMC_L32_ALLSOURCES | \ 147 AMD_PMC_L32_COREMASK) 148 149 #define AMD_PMC_L3_CAPS (PMC_CAP_READ | PMC_CAP_WRITE | \ 150 PMC_CAP_QUALIFIER | PMC_CAP_DOMWIDE) 151 152 /* DF */ 153 #define AMD_PMC_DF_BASE 0xC0010240 154 #define AMD_PMC_DF_DEFAULT 4 155 #define AMD_PMC_DF_MAX 64 156 157 #define AMD_PMC_DF_CAPS (PMC_CAP_READ | PMC_CAP_WRITE | \ 158 PMC_CAP_QUALIFIER | PMC_CAP_DOMWIDE) 159 160 /* 161 * DF counters change their encoding between Family 19h and Family 1Ah 162 * processors. 163 * 164 * Refer to the same documents as the L3 counters. 165 */ 166 #define AMD_PMC_DF1_TO_EVENTMASK(x) (((x) & 0xFF) | \ 167 (((uint64_t)(x) & 0x0F00) << 24) | (((uint64_t)(x) & 0x3000) << 47)) 168 #define AMD_PMC_DF1_TO_UNITMASK(x) (((x) & 0xFF) << 8) 169 170 #define AMD_PMC_DF2_TO_EVENTMASK(x) (((x) & 0xFF) | \ 171 (((uint64_t)(x) & 0x7F00) << 24)) 172 #define AMD_PMC_DF2_TO_UNITMASK(x) ((((x) & 0xFF) << 8) | \ 173 (((uint64_t)(x) & 0x0F00) << 16)) 174 175 #define AMD_PMC_DF_FAMILY17_MASK \ 176 (AMD_PMC_ENABLE | \ 177 AMD_PMC_DF1_TO_EVENTMASK(0x3fff) | \ 178 AMD_PMC_DF1_TO_UNITMASK(0xff)) 179 180 #define AMD_PMC_DF_FAMILY1A_MASK \ 181 (AMD_PMC_ENABLE | \ 182 AMD_PMC_DF2_TO_EVENTMASK(0x7fff) | \ 183 AMD_PMC_DF2_TO_UNITMASK(0xfff)) 184 185 /* 186 * UMC counters 187 * 188 * Refer to the following documents: 189 * PPR for AMD Family 1Ah Model 02h C1 57238 Rev. 0.49 March 6, 2026 190 */ 191 192 #define AMD_PMC_UMC_BASE 0xC0010800 193 #define AMD_PMC_UMC_MAX 256 194 195 #define AMD_PMC_UMC_CAPS (PMC_CAP_READ | PMC_CAP_WRITE | \ 196 PMC_CAP_QUALIFIER | PMC_CAP_DOMWIDE) 197 198 #define AMD_PMC_UMC_ENABLE 0x80000000 199 #define AMD_PMC_UMC_RDWRMASK 0x00000300 200 #define AMD_PMC_UMC_EVENTMASK 0x000000FF 201 202 #define AMD_PMC_UMC_MASK (AMD_PMC_UMC_ENABLE | AMD_PMC_UMC_RDWRMASK | \ 203 AMD_PMC_UMC_EVENTMASK) 204 205 #define AMD_PMC_UMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_UMC_ENABLE) == 0) 206 207 #define AMD_PMC_UMC_TO_EVENTMASK(x) ((x) & AMD_PMC_UMC_EVENTMASK) 208 #define AMD_PMC_UMC_TO_RDWRMASK(x) (((x) << 8) & AMD_PMC_UMC_RDWRMASK) 209 210 #define AMD_NPMCS_K8 4 211 /* Compile-time upper bound; npmcs_total must not exceed this. */ 212 #define AMD_NPMCS_MAX (AMD_PMC_CORE_MAX + AMD_PMC_L3_MAX + \ 213 AMD_PMC_DF_MAX + AMD_PMC_UMC_MAX) 214 215 #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0) 216 #define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0) 217 218 #define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V)) 219 #define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) 220 221 enum sub_class { 222 PMC_AMD_SUB_CLASS_CORE, 223 PMC_AMD_SUB_CLASS_L3_CACHE, 224 PMC_AMD_SUB_CLASS_DATA_FABRIC, 225 PMC_AMD_SUB_CLASS_UMC 226 }; 227 228 struct pmc_md_amd_op_pmcallocate { 229 uint64_t pm_amd_config; 230 uint32_t pm_amd_sub_class; 231 }; 232 233 #ifdef _KERNEL 234 235 /* MD extension for 'struct pmc' */ 236 struct pmc_md_amd_pmc { 237 uint64_t pm_amd_evsel; 238 }; 239 240 #endif /* _KERNEL */ 241 #endif /* _DEV_HWPMC_AMD_H_ */ 242