1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2005, Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* Machine dependent interfaces */ 30 31 #ifndef _DEV_HWPMC_AMD_H_ 32 #define _DEV_HWPMC_AMD_H_ 1 33 34 /* CPUIDs */ 35 #define CPUID_EXTPERFMON 0x80000022 36 #define EXTPERFMON_CORE_PMCS(x) ((x) & 0x0F) 37 #define EXTPERFMON_DF_PMCS(x) (((x) >> 10) & 0x3F) 38 #define EXTPERFMON_UMC_PMCS(x) (((x) >> 16) & 0xFF) 39 40 /* AMD K8 PMCs */ 41 #define AMD_PMC_EVSEL_0 0xC0010000 42 #define AMD_PMC_EVSEL_1 0xC0010001 43 #define AMD_PMC_EVSEL_2 0xC0010002 44 #define AMD_PMC_EVSEL_3 0xC0010003 45 46 #define AMD_PMC_PERFCTR_0 0xC0010004 47 #define AMD_PMC_PERFCTR_1 0xC0010005 48 #define AMD_PMC_PERFCTR_2 0xC0010006 49 #define AMD_PMC_PERFCTR_3 0xC0010007 50 51 /* 52 * For older AMD processors we have hard coded the original four core counters. 53 * For newer processors we use the cpuid bits to setup the counter table. The 54 * counts below are the default number of registers assuming that you do not 55 * have CPUID leaf 0x80000022. The maximum number of counters is computed 56 * based on the available bits in the CPUID leaf and reserved MSR space. 57 * 58 * Refer to the PPRs for AMD Family 1Ah. 59 */ 60 61 /* CORE */ 62 #define AMD_PMC_CORE_BASE 0xC0010200 63 #define AMD_PMC_CORE_DEFAULT 6 64 #define AMD_PMC_CORE_MAX 16 65 66 #define AMD_PMC_COUNTERMASK 0xFF000000 67 #define AMD_PMC_PRECISERETIRE (1ULL << 43) /* Only valid for PERF_CTL2 */ 68 #define AMD_PMC_HOST (1ULL << 41) 69 #define AMD_PMC_GUEST (1ULL << 40) 70 #define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK) 71 #define AMD_PMC_INVERT (1 << 23) 72 #define AMD_PMC_ENABLE (1 << 22) 73 #define AMD_PMC_INT (1 << 20) 74 #define AMD_PMC_PC (1 << 19) 75 #define AMD_PMC_EDGE (1 << 18) 76 #define AMD_PMC_OS (1 << 17) 77 #define AMD_PMC_USR (1 << 16) 78 79 #define AMD_PMC_UNITMASK 0xFF00 80 #define AMD_PMC_EVENTMASK 0xF000000FF 81 82 #define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 83 #define AMD_PMC_TO_EVENTMASK(x) (((x) & 0xFF) | (((uint64_t)(x) & 0xF00) << 24)) 84 85 #define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \ 86 AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \ 87 AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK) 88 89 #define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \ 90 PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \ 91 PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER) 92 93 /* L3 */ 94 #define AMD_PMC_L3_BASE 0xC0010230 95 #define AMD_PMC_L3_DEFAULT 6 96 #define AMD_PMC_L3_MAX 6 97 98 /* 99 * L3 counters change their encoding slightly between Family 17h and Family 19h 100 * processors. 101 * 102 * Refer to the following documents for the L3 fields: 103 * PPR for AMD Family 17h Model 20h A1 55772-A1 Rev. 3.08 April 14, 2021 104 * PPR for AMD Family 19h Model 51h A1 56569-A1 Rev. 3.03 September 21, 2021 105 * PPR for AMD Family 1Ah Model 02h C1 57238 Rev. 0.24 September 29, 2024 106 */ 107 #define AMD_PMC_L31_SLICEMASK (0x000F000000000000ULL) 108 #define AMD_PMC_L31_COREMASK (0xFF00000000000000ULL) 109 110 #define AMD_PMC_L31_TO_SLICE(x) (((uint64_t)(x) << 48) & AMD_PMC_L31_SLICEMASK) 111 #define AMD_PMC_L31_TO_CORE(x) (((uint64_t)(x) << 56) & AMD_PMC_L31_COREMASK) 112 113 #define AMD_PMC_L32_THREADMASK (0x0F00000000000000ULL) 114 #define AMD_PMC_L32_SOURCEMASK (0x0007000000000000ULL) 115 #define AMD_PMC_L32_ALLCORES (1ULL << 47) 116 #define AMD_PMC_L32_ALLSOURCES (1ULL << 46) 117 #define AMD_PMC_L32_COREMASK (0x00001C0000000000ULL) 118 119 #define AMD_PMC_L32_TO_THREAD(x) (((uint64_t)(x) << 56) & AMD_PMC_L32_THREADMASK) 120 #define AMD_PMC_L32_TO_SOURCEID(x) (((uint64_t)(x) << 48) & AMD_PMC_L32_SOURCEMASK) 121 #define AMD_PMC_L32_TO_COREID(x) (((uint64_t)(x) << 42) & AMD_PMC_L32_COREMASK) 122 123 #define AMD_PMC_L3_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) 124 #define AMD_PMC_L3_TO_EVENTMASK(x) ((x) & 0xFF) 125 126 #define AMD_PMC_L3_FAMILY17_MASK \ 127 (AMD_PMC_ENABLE | AMD_PMC_L3_TO_EVENTMASK(0xff) | \ 128 AMD_PMC_L3_TO_UNITMASK(0xff) | \ 129 AMD_PMC_L31_SLICEMASK | AMD_PMC_L31_COREMASK) 130 131 #define AMD_PMC_L3_FAMILY19_MASK \ 132 (AMD_PMC_ENABLE | AMD_PMC_L3_TO_EVENTMASK(0xff) | \ 133 AMD_PMC_L3_TO_UNITMASK(0xff) | \ 134 AMD_PMC_L32_THREADMASK | AMD_PMC_L32_SOURCEMASK | \ 135 AMD_PMC_L32_ALLCORES | AMD_PMC_L32_ALLSOURCES | \ 136 AMD_PMC_L32_COREMASK) 137 138 #define AMD_PMC_L3_CAPS (PMC_CAP_READ | PMC_CAP_WRITE | \ 139 PMC_CAP_QUALIFIER | PMC_CAP_DOMWIDE) 140 141 /* DF */ 142 #define AMD_PMC_DF_BASE 0xC0010240 143 #define AMD_PMC_DF_DEFAULT 4 144 #define AMD_PMC_DF_MAX 64 145 146 #define AMD_PMC_DF_CAPS (PMC_CAP_READ | PMC_CAP_WRITE | \ 147 PMC_CAP_QUALIFIER | PMC_CAP_DOMWIDE) 148 149 /* 150 * DF counters change their encoding between Family 19h and Family 1Ah 151 * processors. 152 * 153 * Refer to the same documents as the L3 counters. 154 */ 155 #define AMD_PMC_DF1_TO_EVENTMASK(x) (((x) & 0xFF) | \ 156 (((uint64_t)(x) & 0x0F00) << 24) | (((uint64_t)(x) & 0x3000) << 47)) 157 #define AMD_PMC_DF1_TO_UNITMASK(x) (((x) & 0xFF) << 8) 158 159 #define AMD_PMC_DF2_TO_EVENTMASK(x) (((x) & 0xFF) | \ 160 (((uint64_t)(x) & 0x7F00) << 24)) 161 #define AMD_PMC_DF2_TO_UNITMASK(x) ((((x) & 0xFF) << 8) | \ 162 (((uint64_t)(x) & 0x0F00) << 16)) 163 164 #define AMD_PMC_DF_FAMILY17_MASK \ 165 (AMD_PMC_ENABLE | \ 166 AMD_PMC_DF1_TO_EVENTMASK(0x3fff) | \ 167 AMD_PMC_DF1_TO_UNITMASK(0xff)) 168 169 #define AMD_PMC_DF_FAMILY1A_MASK \ 170 (AMD_PMC_ENABLE | \ 171 AMD_PMC_DF2_TO_EVENTMASK(0x7fff) | \ 172 AMD_PMC_DF2_TO_UNITMASK(0xfff)) 173 174 /* 175 * UMC counters 176 * 177 * Refer to the following documents: 178 * PPR for AMD Family 1Ah Model 02h C1 57238 Rev. 0.49 March 6, 2026 179 */ 180 181 #define AMD_PMC_UMC_BASE 0xC0010800 182 #define AMD_PMC_UMC_MAX 256 183 184 #define AMD_PMC_UMC_CAPS (PMC_CAP_READ | PMC_CAP_WRITE | \ 185 PMC_CAP_QUALIFIER | PMC_CAP_DOMWIDE) 186 187 #define AMD_PMC_UMC_ENABLE 0x80000000 188 #define AMD_PMC_UMC_RDWRMASK 0x00000300 189 #define AMD_PMC_UMC_EVENTMASK 0x000000FF 190 191 #define AMD_PMC_UMC_MASK (AMD_PMC_UMC_ENABLE | AMD_PMC_UMC_RDWRMASK | \ 192 AMD_PMC_UMC_EVENTMASK) 193 194 #define AMD_PMC_UMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_UMC_ENABLE) == 0) 195 196 #define AMD_PMC_UMC_TO_EVENTMASK(x) ((x) & AMD_PMC_UMC_EVENTMASK) 197 #define AMD_PMC_UMC_TO_RDWRMASK(x) (((x) << 8) & AMD_PMC_UMC_RDWRMASK) 198 199 #define AMD_NPMCS_K8 4 200 #define AMD_NPMCS_MAX (AMD_PMC_CORE_MAX + AMD_PMC_L3_MAX + \ 201 AMD_PMC_DF_MAX + AMD_PMC_UMC_MAX) 202 203 #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0) 204 #define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0) 205 206 #define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V)) 207 #define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) 208 209 enum sub_class { 210 PMC_AMD_SUB_CLASS_CORE, 211 PMC_AMD_SUB_CLASS_L3_CACHE, 212 PMC_AMD_SUB_CLASS_DATA_FABRIC, 213 PMC_AMD_SUB_CLASS_UMC 214 }; 215 216 struct pmc_md_amd_op_pmcallocate { 217 uint64_t pm_amd_config; 218 uint32_t pm_amd_sub_class; 219 }; 220 221 #ifdef _KERNEL 222 223 /* MD extension for 'struct pmc' */ 224 struct pmc_md_amd_pmc { 225 uint64_t pm_amd_evsel; 226 }; 227 228 #endif /* _KERNEL */ 229 #endif /* _DEV_HWPMC_AMD_H_ */ 230