xref: /freebsd/sys/dev/hwpmc/hwpmc_amd.h (revision 1de7b4b805ddbf2429da511c053686ac4591ed89)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2005, Joseph Koshy
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 /* Machine dependent interfaces */
32 
33 #ifndef _DEV_HWPMC_AMD_H_
34 #define	_DEV_HWPMC_AMD_H_ 1
35 
36 /* AMD K7 and K8 PMCs */
37 
38 #define	AMD_PMC_EVSEL_0		0xC0010000
39 #define	AMD_PMC_EVSEL_1		0xC0010001
40 #define	AMD_PMC_EVSEL_2		0xC0010002
41 #define	AMD_PMC_EVSEL_3		0xC0010003
42 
43 #define	AMD_PMC_PERFCTR_0	0xC0010004
44 #define	AMD_PMC_PERFCTR_1	0xC0010005
45 #define	AMD_PMC_PERFCTR_2	0xC0010006
46 #define	AMD_PMC_PERFCTR_3	0xC0010007
47 
48 
49 #define	AMD_NPMCS		4
50 
51 #define	AMD_PMC_COUNTERMASK	0xFF000000
52 #define	AMD_PMC_TO_COUNTER(x)	(((x) << 24) & AMD_PMC_COUNTERMASK)
53 #define	AMD_PMC_INVERT		(1 << 23)
54 #define	AMD_PMC_ENABLE		(1 << 22)
55 #define	AMD_PMC_INT		(1 << 20)
56 #define	AMD_PMC_PC		(1 << 19)
57 #define	AMD_PMC_EDGE		(1 << 18)
58 #define	AMD_PMC_OS		(1 << 17)
59 #define	AMD_PMC_USR		(1 << 16)
60 
61 #define	AMD_PMC_UNITMASK_M	0x10
62 #define	AMD_PMC_UNITMASK_O	0x08
63 #define	AMD_PMC_UNITMASK_E	0x04
64 #define	AMD_PMC_UNITMASK_S	0x02
65 #define	AMD_PMC_UNITMASK_I	0x01
66 #define	AMD_PMC_UNITMASK_MOESI	0x1F
67 
68 #define	AMD_PMC_UNITMASK	0xFF00
69 #define	AMD_PMC_EVENTMASK 	0xF000000FF
70 
71 #define	AMD_PMC_TO_UNITMASK(x)	(((x) << 8) & AMD_PMC_UNITMASK)
72 #define	AMD_PMC_TO_EVENTMASK(x)	(((x) & 0xFF) | (((uint64_t)(x) & 0xF00) << 24))
73 #define	AMD_VALID_BITS		(AMD_PMC_COUNTERMASK | AMD_PMC_INVERT |	\
74 	AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | 	\
75 	AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK)
76 
77 #define AMD_PMC_CAPS		(PMC_CAP_INTERRUPT | PMC_CAP_USER | 	\
78 	PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | 		\
79 	PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER)
80 
81 #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0)
82 #define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0)
83 
84 #define	AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V)	(-(V))
85 #define	AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P)	(-(P))
86 
87 struct pmc_md_amd_op_pmcallocate {
88 	uint32_t	pm_amd_config;
89 };
90 
91 #ifdef _KERNEL
92 
93 /* MD extension for 'struct pmc' */
94 struct pmc_md_amd_pmc {
95 	uint32_t	pm_amd_evsel;
96 };
97 
98 #endif /* _KERNEL */
99 #endif /* _DEV_HWPMC_AMD_H_ */
100