1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* Support for the AMD K7 and later processors */ 37 38 #include <sys/param.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/pmc.h> 43 #include <sys/pmckern.h> 44 #include <sys/smp.h> 45 #include <sys/systm.h> 46 47 #include <machine/cpu.h> 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #ifdef HWPMC_DEBUG 53 enum pmc_class amd_pmc_class; 54 #endif 55 56 /* AMD K7 & K8 PMCs */ 57 struct amd_descr { 58 struct pmc_descr pm_descr; /* "base class" */ 59 uint32_t pm_evsel; /* address of EVSEL register */ 60 uint32_t pm_perfctr; /* address of PERFCTR register */ 61 }; 62 63 static struct amd_descr amd_pmcdesc[AMD_NPMCS] = 64 { 65 { 66 .pm_descr = 67 { 68 .pd_name = "", 69 .pd_class = -1, 70 .pd_caps = AMD_PMC_CAPS, 71 .pd_width = 48 72 }, 73 .pm_evsel = AMD_PMC_EVSEL_0, 74 .pm_perfctr = AMD_PMC_PERFCTR_0 75 }, 76 { 77 .pm_descr = 78 { 79 .pd_name = "", 80 .pd_class = -1, 81 .pd_caps = AMD_PMC_CAPS, 82 .pd_width = 48 83 }, 84 .pm_evsel = AMD_PMC_EVSEL_1, 85 .pm_perfctr = AMD_PMC_PERFCTR_1 86 }, 87 { 88 .pm_descr = 89 { 90 .pd_name = "", 91 .pd_class = -1, 92 .pd_caps = AMD_PMC_CAPS, 93 .pd_width = 48 94 }, 95 .pm_evsel = AMD_PMC_EVSEL_2, 96 .pm_perfctr = AMD_PMC_PERFCTR_2 97 }, 98 { 99 .pm_descr = 100 { 101 .pd_name = "", 102 .pd_class = -1, 103 .pd_caps = AMD_PMC_CAPS, 104 .pd_width = 48 105 }, 106 .pm_evsel = AMD_PMC_EVSEL_3, 107 .pm_perfctr = AMD_PMC_PERFCTR_3 108 }, 109 { 110 .pm_descr = 111 { 112 .pd_name = "", 113 .pd_class = -1, 114 .pd_caps = AMD_PMC_CAPS, 115 .pd_width = 48 116 }, 117 .pm_evsel = AMD_PMC_EVSEL_4, 118 .pm_perfctr = AMD_PMC_PERFCTR_4 119 }, 120 { 121 .pm_descr = 122 { 123 .pd_name = "", 124 .pd_class = -1, 125 .pd_caps = AMD_PMC_CAPS, 126 .pd_width = 48 127 }, 128 .pm_evsel = AMD_PMC_EVSEL_5, 129 .pm_perfctr = AMD_PMC_PERFCTR_5 130 }, 131 { 132 .pm_descr = 133 { 134 .pd_name = "", 135 .pd_class = -1, 136 .pd_caps = AMD_PMC_CAPS, 137 .pd_width = 48 138 }, 139 .pm_evsel = AMD_PMC_EVSEL_EP_L3_0, 140 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_0 141 }, 142 { 143 .pm_descr = 144 { 145 .pd_name = "", 146 .pd_class = -1, 147 .pd_caps = AMD_PMC_CAPS, 148 .pd_width = 48 149 }, 150 .pm_evsel = AMD_PMC_EVSEL_EP_L3_1, 151 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_1 152 }, 153 { 154 .pm_descr = 155 { 156 .pd_name = "", 157 .pd_class = -1, 158 .pd_caps = AMD_PMC_CAPS, 159 .pd_width = 48 160 }, 161 .pm_evsel = AMD_PMC_EVSEL_EP_L3_2, 162 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_2 163 }, 164 { 165 .pm_descr = 166 { 167 .pd_name = "", 168 .pd_class = -1, 169 .pd_caps = AMD_PMC_CAPS, 170 .pd_width = 48 171 }, 172 .pm_evsel = AMD_PMC_EVSEL_EP_L3_3, 173 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_3 174 }, 175 { 176 .pm_descr = 177 { 178 .pd_name = "", 179 .pd_class = -1, 180 .pd_caps = AMD_PMC_CAPS, 181 .pd_width = 48 182 }, 183 .pm_evsel = AMD_PMC_EVSEL_EP_L3_4, 184 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_4 185 }, 186 { 187 .pm_descr = 188 { 189 .pd_name = "", 190 .pd_class = -1, 191 .pd_caps = AMD_PMC_CAPS, 192 .pd_width = 48 193 }, 194 .pm_evsel = AMD_PMC_EVSEL_EP_L3_5, 195 .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_5 196 }, 197 { 198 .pm_descr = 199 { 200 .pd_name = "", 201 .pd_class = -1, 202 .pd_caps = AMD_PMC_CAPS, 203 .pd_width = 48 204 }, 205 .pm_evsel = AMD_PMC_EVSEL_EP_DF_0, 206 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_0 207 }, 208 { 209 .pm_descr = 210 { 211 .pd_name = "", 212 .pd_class = -1, 213 .pd_caps = AMD_PMC_CAPS, 214 .pd_width = 48 215 }, 216 .pm_evsel = AMD_PMC_EVSEL_EP_DF_1, 217 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_1 218 }, 219 { 220 .pm_descr = 221 { 222 .pd_name = "", 223 .pd_class = -1, 224 .pd_caps = AMD_PMC_CAPS, 225 .pd_width = 48 226 }, 227 .pm_evsel = AMD_PMC_EVSEL_EP_DF_2, 228 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_2 229 }, 230 { 231 .pm_descr = 232 { 233 .pd_name = "", 234 .pd_class = -1, 235 .pd_caps = AMD_PMC_CAPS, 236 .pd_width = 48 237 }, 238 .pm_evsel = AMD_PMC_EVSEL_EP_DF_3, 239 .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_3 240 } 241 }; 242 243 struct amd_event_code_map { 244 enum pmc_event pe_ev; /* enum value */ 245 uint16_t pe_code; /* encoded event mask */ 246 uint8_t pe_mask; /* bits allowed in unit mask */ 247 }; 248 249 const struct amd_event_code_map amd_event_codes[] = { 250 #if defined(__i386__) /* 32 bit Athlon (K7) only */ 251 { PMC_EV_K7_DC_ACCESSES, 0x40, 0 }, 252 { PMC_EV_K7_DC_MISSES, 0x41, 0 }, 253 { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI }, 254 { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI }, 255 { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI }, 256 { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 }, 257 { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 }, 258 { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 }, 259 260 { PMC_EV_K7_IC_FETCHES, 0x80, 0 }, 261 { PMC_EV_K7_IC_MISSES, 0x81, 0 }, 262 263 { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 }, 264 { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 }, 265 266 { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 }, 267 { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 }, 268 { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 }, 269 { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 }, 270 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 }, 271 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 }, 272 { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 }, 273 { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 }, 274 { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 }, 275 { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 }, 276 { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 }, 277 #endif 278 279 { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F }, 280 { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 }, 281 { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 }, 282 283 { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F }, 284 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE, 285 0x21, 0x00 }, 286 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 }, 287 { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 }, 288 { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 }, 289 { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 }, 290 { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 }, 291 { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 }, 292 293 { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 }, 294 { PMC_EV_K8_DC_MISS, 0x41, 0x00 }, 295 { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F }, 296 { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F }, 297 { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F }, 298 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 }, 299 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 }, 300 { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 }, 301 { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 }, 302 { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 }, 303 { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 }, 304 { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 }, 305 { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 }, 306 307 { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 }, 308 { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F }, 309 { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 }, 310 { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 }, 311 312 { PMC_EV_K8_IC_FETCH, 0x80, 0x00 }, 313 { PMC_EV_K8_IC_MISS, 0x81, 0x00 }, 314 { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 }, 315 { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 }, 316 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 }, 317 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 }, 318 { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 }, 319 { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 }, 320 { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 }, 321 { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 }, 322 323 { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 }, 324 { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 }, 325 { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 }, 326 { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 }, 327 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 }, 328 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 }, 329 { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 }, 330 { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 }, 331 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 }, 332 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 }, 333 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE, 334 0xCA, 0x00 }, 335 { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F }, 336 { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS, 337 0xCC, 0x07 }, 338 { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 }, 339 { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 }, 340 { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 }, 341 342 { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 }, 343 { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 }, 344 { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE, 345 0xD2, 0x00 }, 346 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 }, 347 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 }, 348 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL, 349 0xD5, 0x00 }, 350 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL, 351 0xD6, 0x00 }, 352 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 }, 353 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 }, 354 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET, 355 0xD9, 0x00 }, 356 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING, 357 0xDA, 0x00 }, 358 { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F }, 359 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 }, 360 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 }, 361 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 }, 362 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 }, 363 364 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 }, 365 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 }, 366 { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED, 367 0xE2, 0x00 }, 368 { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 }, 369 { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F }, 370 { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F }, 371 { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F }, 372 { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F }, 373 { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F }, 374 { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F } 375 376 }; 377 378 const int amd_event_codes_size = nitems(amd_event_codes); 379 380 /* 381 * Per-processor information 382 */ 383 384 struct amd_cpu { 385 struct pmc_hw pc_amdpmcs[AMD_NPMCS]; 386 }; 387 388 static struct amd_cpu **amd_pcpu; 389 390 /* 391 * read a pmc register 392 */ 393 394 static int 395 amd_read_pmc(int cpu, int ri, pmc_value_t *v) 396 { 397 enum pmc_mode mode; 398 const struct amd_descr *pd; 399 struct pmc *pm; 400 pmc_value_t tmp; 401 402 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 403 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 404 KASSERT(ri >= 0 && ri < AMD_NPMCS, 405 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 406 KASSERT(amd_pcpu[cpu], 407 ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu)); 408 409 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 410 pd = &amd_pmcdesc[ri]; 411 412 KASSERT(pm != NULL, 413 ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__, 414 cpu, ri)); 415 416 mode = PMC_TO_MODE(pm); 417 418 PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class); 419 420 #ifdef HWPMC_DEBUG 421 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 422 ("[amd,%d] unknown PMC class (%d)", __LINE__, 423 pd->pm_descr.pd_class)); 424 #endif 425 426 tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */ 427 PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp); 428 if (PMC_IS_SAMPLING_MODE(mode)) { 429 /* Sign extend 48 bit value to 64 bits. */ 430 tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16); 431 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 432 } 433 *v = tmp; 434 435 PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v); 436 437 return 0; 438 } 439 440 /* 441 * Write a PMC MSR. 442 */ 443 444 static int 445 amd_write_pmc(int cpu, int ri, pmc_value_t v) 446 { 447 const struct amd_descr *pd; 448 enum pmc_mode mode; 449 struct pmc *pm; 450 451 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 452 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 453 KASSERT(ri >= 0 && ri < AMD_NPMCS, 454 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 455 456 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 457 pd = &amd_pmcdesc[ri]; 458 459 KASSERT(pm != NULL, 460 ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__, 461 cpu, ri)); 462 463 mode = PMC_TO_MODE(pm); 464 465 #ifdef HWPMC_DEBUG 466 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 467 ("[amd,%d] unknown PMC class (%d)", __LINE__, 468 pd->pm_descr.pd_class)); 469 #endif 470 471 /* use 2's complement of the count for sampling mode PMCs */ 472 if (PMC_IS_SAMPLING_MODE(mode)) 473 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 474 475 PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v); 476 477 /* write the PMC value */ 478 wrmsr(pd->pm_perfctr, v); 479 return 0; 480 } 481 482 /* 483 * configure hardware pmc according to the configuration recorded in 484 * pmc 'pm'. 485 */ 486 487 static int 488 amd_config_pmc(int cpu, int ri, struct pmc *pm) 489 { 490 struct pmc_hw *phw; 491 492 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 493 494 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 495 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 496 KASSERT(ri >= 0 && ri < AMD_NPMCS, 497 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 498 499 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 500 501 KASSERT(pm == NULL || phw->phw_pmc == NULL, 502 ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 503 __LINE__, pm, phw->phw_pmc)); 504 505 phw->phw_pmc = pm; 506 return 0; 507 } 508 509 /* 510 * Retrieve a configured PMC pointer from hardware state. 511 */ 512 513 static int 514 amd_get_config(int cpu, int ri, struct pmc **ppm) 515 { 516 *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 517 518 return 0; 519 } 520 521 /* 522 * Machine dependent actions taken during the context switch in of a 523 * thread. 524 */ 525 526 static int 527 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 528 { 529 (void) pc; 530 531 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 532 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0); 533 534 /* enable the RDPMC instruction if needed */ 535 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 536 load_cr4(rcr4() | CR4_PCE); 537 538 return 0; 539 } 540 541 /* 542 * Machine dependent actions taken during the context switch out of a 543 * thread. 544 */ 545 546 static int 547 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 548 { 549 (void) pc; 550 (void) pp; /* can be NULL */ 551 552 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ? 553 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0); 554 555 /* always turn off the RDPMC instruction */ 556 load_cr4(rcr4() & ~CR4_PCE); 557 558 return 0; 559 } 560 561 /* 562 * Check if a given allocation is feasible. 563 */ 564 565 static int 566 amd_allocate_pmc(int cpu, int ri, struct pmc *pm, 567 const struct pmc_op_pmcallocate *a) 568 { 569 int i; 570 uint64_t allowed_unitmask, caps, config, unitmask; 571 enum pmc_event pe; 572 const struct pmc_descr *pd; 573 574 (void) cpu; 575 576 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 577 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 578 KASSERT(ri >= 0 && ri < AMD_NPMCS, 579 ("[amd,%d] illegal row index %d", __LINE__, ri)); 580 581 pd = &amd_pmcdesc[ri].pm_descr; 582 583 /* check class match */ 584 if (pd->pd_class != a->pm_class) 585 return EINVAL; 586 587 caps = pm->pm_caps; 588 589 PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps); 590 591 if((ri >= 0 && ri < 6) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_CORE)) 592 return EINVAL; 593 if((ri >= 6 && ri < 12) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_L3_CACHE)) 594 return EINVAL; 595 if((ri >= 12 && ri < 16) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_DATA_FABRIC)) 596 return EINVAL; 597 598 if ((pd->pd_caps & caps) != caps) 599 return EPERM; 600 if (strlen(pmc_cpuid) != 0) { 601 pm->pm_md.pm_amd.pm_amd_evsel = 602 a->pm_md.pm_amd.pm_amd_config; 603 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, a->pm_md.pm_amd.pm_amd_config); 604 return (0); 605 } 606 607 pe = a->pm_ev; 608 609 /* map ev to the correct event mask code */ 610 config = allowed_unitmask = 0; 611 for (i = 0; i < amd_event_codes_size; i++) 612 if (amd_event_codes[i].pe_ev == pe) { 613 config = 614 AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code); 615 allowed_unitmask = 616 AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask); 617 break; 618 } 619 if (i == amd_event_codes_size) 620 return EINVAL; 621 622 unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK; 623 if (unitmask & ~allowed_unitmask) /* disallow reserved bits */ 624 return EINVAL; 625 626 if (unitmask && (caps & PMC_CAP_QUALIFIER)) 627 config |= unitmask; 628 629 if (caps & PMC_CAP_THRESHOLD) 630 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK; 631 632 /* set at least one of the 'usr' or 'os' caps */ 633 if (caps & PMC_CAP_USER) 634 config |= AMD_PMC_USR; 635 if (caps & PMC_CAP_SYSTEM) 636 config |= AMD_PMC_OS; 637 if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0) 638 config |= (AMD_PMC_USR|AMD_PMC_OS); 639 640 if (caps & PMC_CAP_EDGE) 641 config |= AMD_PMC_EDGE; 642 if (caps & PMC_CAP_INVERT) 643 config |= AMD_PMC_INVERT; 644 if (caps & PMC_CAP_INTERRUPT) 645 config |= AMD_PMC_INT; 646 647 pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */ 648 649 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config); 650 651 return 0; 652 } 653 654 /* 655 * Release machine dependent state associated with a PMC. This is a 656 * no-op on this architecture. 657 * 658 */ 659 660 /* ARGSUSED0 */ 661 static int 662 amd_release_pmc(int cpu, int ri, struct pmc *pmc) 663 { 664 #ifdef HWPMC_DEBUG 665 const struct amd_descr *pd; 666 #endif 667 struct pmc_hw *phw; 668 669 (void) pmc; 670 671 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 672 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 673 KASSERT(ri >= 0 && ri < AMD_NPMCS, 674 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 675 676 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 677 678 KASSERT(phw->phw_pmc == NULL, 679 ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 680 681 #ifdef HWPMC_DEBUG 682 pd = &amd_pmcdesc[ri]; 683 if (pd->pm_descr.pd_class == amd_pmc_class) 684 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 685 ("[amd,%d] PMC %d released while active", __LINE__, ri)); 686 #endif 687 688 return 0; 689 } 690 691 /* 692 * start a PMC. 693 */ 694 695 static int 696 amd_start_pmc(int cpu, int ri) 697 { 698 uint64_t config; 699 struct pmc *pm; 700 struct pmc_hw *phw; 701 const struct amd_descr *pd; 702 703 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 704 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 705 KASSERT(ri >= 0 && ri < AMD_NPMCS, 706 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 707 708 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 709 pm = phw->phw_pmc; 710 pd = &amd_pmcdesc[ri]; 711 712 KASSERT(pm != NULL, 713 ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__, 714 cpu, ri)); 715 716 PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri); 717 718 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 719 ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__, 720 ri, cpu, pd->pm_descr.pd_name)); 721 722 /* turn on the PMC ENABLE bit */ 723 config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE; 724 725 PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config); 726 727 wrmsr(pd->pm_evsel, config); 728 return 0; 729 } 730 731 /* 732 * Stop a PMC. 733 */ 734 735 static int 736 amd_stop_pmc(int cpu, int ri) 737 { 738 struct pmc *pm; 739 struct pmc_hw *phw; 740 const struct amd_descr *pd; 741 uint64_t config; 742 743 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 744 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 745 KASSERT(ri >= 0 && ri < AMD_NPMCS, 746 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 747 748 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 749 pm = phw->phw_pmc; 750 pd = &amd_pmcdesc[ri]; 751 752 KASSERT(pm != NULL, 753 ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__, 754 cpu, ri)); 755 KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel), 756 ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped", 757 __LINE__, ri, cpu, pd->pm_descr.pd_name)); 758 759 PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri); 760 761 /* turn off the PMC ENABLE bit */ 762 config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE; 763 wrmsr(pd->pm_evsel, config); 764 return 0; 765 } 766 767 /* 768 * Interrupt handler. This function needs to return '1' if the 769 * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed 770 * to sleep or do anything a 'fast' interrupt handler is not allowed 771 * to do. 772 */ 773 774 static int 775 amd_intr(struct trapframe *tf) 776 { 777 int i, error, retval, cpu; 778 uint64_t config, evsel, perfctr; 779 struct pmc *pm; 780 struct amd_cpu *pac; 781 pmc_value_t v; 782 783 cpu = curcpu; 784 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 785 ("[amd,%d] out of range CPU %d", __LINE__, cpu)); 786 787 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf, 788 TRAPF_USERMODE(tf)); 789 790 retval = 0; 791 792 pac = amd_pcpu[cpu]; 793 794 /* 795 * look for all PMCs that have interrupted: 796 * - look for a running, sampling PMC which has overflowed 797 * and which has a valid 'struct pmc' association 798 * 799 * If found, we call a helper to process the interrupt. 800 * 801 * If multiple PMCs interrupt at the same time, the AMD64 802 * processor appears to deliver as many NMIs as there are 803 * outstanding PMC interrupts. So we process only one NMI 804 * interrupt at a time. 805 */ 806 807 for (i = 0; retval == 0 && i < AMD_NPMCS; i++) { 808 809 if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL || 810 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 811 continue; 812 } 813 814 if (!AMD_PMC_HAS_OVERFLOWED(i)) 815 continue; 816 817 retval = 1; /* Found an interrupting PMC. */ 818 819 if (pm->pm_state != PMC_STATE_RUNNING) 820 continue; 821 822 /* Stop the PMC, reload count. */ 823 evsel = AMD_PMC_EVSEL_0 + i; 824 perfctr = AMD_PMC_PERFCTR_0 + i; 825 v = pm->pm_sc.pm_reloadcount; 826 config = rdmsr(evsel); 827 828 KASSERT((config & ~AMD_PMC_ENABLE) == 829 (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE), 830 ("[amd,%d] config mismatch reg=0x%jx pm=0x%jx", __LINE__, 831 (uintmax_t)config, (uintmax_t)pm->pm_md.pm_amd.pm_amd_evsel)); 832 833 wrmsr(evsel, config & ~AMD_PMC_ENABLE); 834 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); 835 836 /* Restart the counter if logging succeeded. */ 837 error = pmc_process_interrupt(PMC_HR, pm, tf); 838 if (error == 0) 839 wrmsr(evsel, config); 840 } 841 842 if (retval) 843 counter_u64_add(pmc_stats.pm_intr_processed, 1); 844 else 845 counter_u64_add(pmc_stats.pm_intr_ignored, 1); 846 847 PMCDBG1(MDP,INT,2, "retval=%d", retval); 848 return (retval); 849 } 850 851 /* 852 * describe a PMC 853 */ 854 static int 855 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 856 { 857 int error; 858 size_t copied; 859 const struct amd_descr *pd; 860 struct pmc_hw *phw; 861 862 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 863 ("[amd,%d] illegal CPU %d", __LINE__, cpu)); 864 KASSERT(ri >= 0 && ri < AMD_NPMCS, 865 ("[amd,%d] row-index %d out of range", __LINE__, ri)); 866 867 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 868 pd = &amd_pmcdesc[ri]; 869 870 if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name, 871 PMC_NAME_MAX, &copied)) != 0) 872 return error; 873 874 pi->pm_class = pd->pm_descr.pd_class; 875 876 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 877 pi->pm_enabled = TRUE; 878 *ppmc = phw->phw_pmc; 879 } else { 880 pi->pm_enabled = FALSE; 881 *ppmc = NULL; 882 } 883 884 return 0; 885 } 886 887 /* 888 * i386 specific entry points 889 */ 890 891 /* 892 * return the MSR address of the given PMC. 893 */ 894 895 static int 896 amd_get_msr(int ri, uint32_t *msr) 897 { 898 KASSERT(ri >= 0 && ri < AMD_NPMCS, 899 ("[amd,%d] ri %d out of range", __LINE__, ri)); 900 901 *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; 902 903 return (0); 904 } 905 906 /* 907 * processor dependent initialization. 908 */ 909 910 static int 911 amd_pcpu_init(struct pmc_mdep *md, int cpu) 912 { 913 int classindex, first_ri, n; 914 struct pmc_cpu *pc; 915 struct amd_cpu *pac; 916 struct pmc_hw *phw; 917 918 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 919 ("[amd,%d] insane cpu number %d", __LINE__, cpu)); 920 921 PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu); 922 923 amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC, 924 M_WAITOK|M_ZERO); 925 926 /* 927 * Set the content of the hardware descriptors to a known 928 * state and initialize pointers in the MI per-cpu descriptor. 929 */ 930 pc = pmc_pcpu[cpu]; 931 #if defined(__amd64__) 932 classindex = PMC_MDEP_CLASS_INDEX_K8; 933 #elif defined(__i386__) 934 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? 935 PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7; 936 #endif 937 first_ri = md->pmd_classdep[classindex].pcd_ri; 938 939 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__)); 940 941 for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) { 942 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 943 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); 944 phw->phw_pmc = NULL; 945 pc->pc_hwpmcs[n + first_ri] = phw; 946 } 947 948 return (0); 949 } 950 951 952 /* 953 * processor dependent cleanup prior to the KLD 954 * being unloaded 955 */ 956 957 static int 958 amd_pcpu_fini(struct pmc_mdep *md, int cpu) 959 { 960 int classindex, first_ri, i; 961 uint32_t evsel; 962 struct pmc_cpu *pc; 963 struct amd_cpu *pac; 964 965 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 966 ("[amd,%d] insane cpu number (%d)", __LINE__, cpu)); 967 968 PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu); 969 970 /* 971 * First, turn off all PMCs on this CPU. 972 */ 973 for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */ 974 evsel = rdmsr(AMD_PMC_EVSEL_0 + i); 975 evsel &= ~AMD_PMC_ENABLE; 976 wrmsr(AMD_PMC_EVSEL_0 + i, evsel); 977 } 978 979 /* 980 * Next, free up allocated space. 981 */ 982 if ((pac = amd_pcpu[cpu]) == NULL) 983 return (0); 984 985 amd_pcpu[cpu] = NULL; 986 987 #ifdef HWPMC_DEBUG 988 for (i = 0; i < AMD_NPMCS; i++) { 989 KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL, 990 ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i)); 991 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i), 992 ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i)); 993 } 994 #endif 995 996 pc = pmc_pcpu[cpu]; 997 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__)); 998 999 #if defined(__amd64__) 1000 classindex = PMC_MDEP_CLASS_INDEX_K8; 1001 #elif defined(__i386__) 1002 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 : 1003 PMC_MDEP_CLASS_INDEX_K7; 1004 #endif 1005 first_ri = md->pmd_classdep[classindex].pcd_ri; 1006 1007 /* 1008 * Reset pointers in the MI 'per-cpu' state. 1009 */ 1010 for (i = 0; i < AMD_NPMCS; i++) { 1011 pc->pc_hwpmcs[i + first_ri] = NULL; 1012 } 1013 1014 1015 free(pac, M_PMC); 1016 1017 return (0); 1018 } 1019 1020 /* 1021 * Initialize ourselves. 1022 */ 1023 1024 struct pmc_mdep * 1025 pmc_amd_initialize(void) 1026 { 1027 int classindex, error, i, ncpus; 1028 struct pmc_classdep *pcd; 1029 enum pmc_cputype cputype; 1030 struct pmc_mdep *pmc_mdep; 1031 enum pmc_class class; 1032 int model; 1033 char *name; 1034 1035 /* 1036 * The presence of hardware performance counters on the AMD 1037 * Athlon, Duron or later processors, is _not_ indicated by 1038 * any of the processor feature flags set by the 'CPUID' 1039 * instruction, so we only check the 'instruction family' 1040 * field returned by CPUID for instruction family >= 6. 1041 */ 1042 1043 name = NULL; 1044 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 1045 if (CPUID_TO_FAMILY(cpu_id) == 0x17) 1046 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "AuthenticAMD-%d-%02X", 1047 CPUID_TO_FAMILY(cpu_id), model); 1048 1049 switch (cpu_id & 0xF00) { 1050 #if defined(__i386__) 1051 case 0x600: /* Athlon(tm) processor */ 1052 classindex = PMC_MDEP_CLASS_INDEX_K7; 1053 cputype = PMC_CPU_AMD_K7; 1054 class = PMC_CLASS_K7; 1055 name = "K7"; 1056 break; 1057 #endif 1058 case 0xF00: /* Athlon64/Opteron processor */ 1059 classindex = PMC_MDEP_CLASS_INDEX_K8; 1060 cputype = PMC_CPU_AMD_K8; 1061 class = PMC_CLASS_K8; 1062 name = "K8"; 1063 break; 1064 1065 default: 1066 (void) printf("pmc: Unknown AMD CPU %x %d-%d.\n", cpu_id, (cpu_id & 0xF00) >> 8, model); 1067 return NULL; 1068 } 1069 1070 #ifdef HWPMC_DEBUG 1071 amd_pmc_class = class; 1072 #endif 1073 1074 /* 1075 * Allocate space for pointers to PMC HW descriptors and for 1076 * the MDEP structure used by MI code. 1077 */ 1078 amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC, 1079 M_WAITOK|M_ZERO); 1080 1081 /* 1082 * These processors have two classes of PMCs: the TSC and 1083 * programmable PMCs. 1084 */ 1085 pmc_mdep = pmc_mdep_alloc(2); 1086 1087 pmc_mdep->pmd_cputype = cputype; 1088 1089 ncpus = pmc_cpu_max(); 1090 1091 /* Initialize the TSC. */ 1092 error = pmc_tsc_initialize(pmc_mdep, ncpus); 1093 if (error) 1094 goto error; 1095 1096 /* Initialize AMD K7 and K8 PMC handling. */ 1097 pcd = &pmc_mdep->pmd_classdep[classindex]; 1098 1099 pcd->pcd_caps = AMD_PMC_CAPS; 1100 pcd->pcd_class = class; 1101 pcd->pcd_num = AMD_NPMCS; 1102 pcd->pcd_ri = pmc_mdep->pmd_npmc; 1103 pcd->pcd_width = 48; 1104 1105 /* fill in the correct pmc name and class */ 1106 for (i = 0; i < AMD_NPMCS; i++) { 1107 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name, 1108 sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d", 1109 name, i); 1110 amd_pmcdesc[i].pm_descr.pd_class = class; 1111 } 1112 1113 pcd->pcd_allocate_pmc = amd_allocate_pmc; 1114 pcd->pcd_config_pmc = amd_config_pmc; 1115 pcd->pcd_describe = amd_describe; 1116 pcd->pcd_get_config = amd_get_config; 1117 pcd->pcd_get_msr = amd_get_msr; 1118 pcd->pcd_pcpu_fini = amd_pcpu_fini; 1119 pcd->pcd_pcpu_init = amd_pcpu_init; 1120 pcd->pcd_read_pmc = amd_read_pmc; 1121 pcd->pcd_release_pmc = amd_release_pmc; 1122 pcd->pcd_start_pmc = amd_start_pmc; 1123 pcd->pcd_stop_pmc = amd_stop_pmc; 1124 pcd->pcd_write_pmc = amd_write_pmc; 1125 1126 pmc_mdep->pmd_pcpu_init = NULL; 1127 pmc_mdep->pmd_pcpu_fini = NULL; 1128 pmc_mdep->pmd_intr = amd_intr; 1129 pmc_mdep->pmd_switch_in = amd_switch_in; 1130 pmc_mdep->pmd_switch_out = amd_switch_out; 1131 1132 pmc_mdep->pmd_npmc += AMD_NPMCS; 1133 1134 PMCDBG0(MDP,INI,0,"amd-initialize"); 1135 1136 return (pmc_mdep); 1137 1138 error: 1139 if (error) { 1140 free(pmc_mdep, M_PMC); 1141 pmc_mdep = NULL; 1142 } 1143 1144 return (NULL); 1145 } 1146 1147 /* 1148 * Finalization code for AMD CPUs. 1149 */ 1150 1151 void 1152 pmc_amd_finalize(struct pmc_mdep *md) 1153 { 1154 #if defined(INVARIANTS) 1155 int classindex, i, ncpus, pmcclass; 1156 #endif 1157 1158 pmc_tsc_finalize(md); 1159 1160 KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer", 1161 __LINE__)); 1162 1163 #if defined(INVARIANTS) 1164 switch (md->pmd_cputype) { 1165 #if defined(__i386__) 1166 case PMC_CPU_AMD_K7: 1167 classindex = PMC_MDEP_CLASS_INDEX_K7; 1168 pmcclass = PMC_CLASS_K7; 1169 break; 1170 #endif 1171 default: 1172 classindex = PMC_MDEP_CLASS_INDEX_K8; 1173 pmcclass = PMC_CLASS_K8; 1174 } 1175 1176 KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass, 1177 ("[amd,%d] pmc class mismatch", __LINE__)); 1178 1179 ncpus = pmc_cpu_max(); 1180 1181 for (i = 0; i < ncpus; i++) 1182 KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu", 1183 __LINE__)); 1184 #endif 1185 1186 free(amd_pcpu, M_PMC); 1187 amd_pcpu = NULL; 1188 } 1189