1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2003-2008 Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* Support for the AMD K7 and later processors */ 37 38 #include <sys/param.h> 39 #include <sys/lock.h> 40 #include <sys/malloc.h> 41 #include <sys/mutex.h> 42 #include <sys/pmc.h> 43 #include <sys/pmckern.h> 44 #include <sys/smp.h> 45 #include <sys/systm.h> 46 47 #include <machine/cpu.h> 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #ifdef HWPMC_DEBUG 53 enum pmc_class amd_pmc_class; 54 #endif 55 56 /* AMD K7 & K8 PMCs */ 57 struct amd_descr { 58 struct pmc_descr pm_descr; /* "base class" */ 59 uint32_t pm_evsel; /* address of EVSEL register */ 60 uint32_t pm_perfctr; /* address of PERFCTR register */ 61 }; 62 63 static struct amd_descr amd_pmcdesc[AMD_NPMCS] = 64 { 65 { 66 .pm_descr = 67 { 68 .pd_name = "", 69 .pd_class = -1, 70 .pd_caps = AMD_PMC_CAPS, 71 .pd_width = 48 72 }, 73 .pm_evsel = AMD_PMC_EVSEL_0, 74 .pm_perfctr = AMD_PMC_PERFCTR_0 75 }, 76 { 77 .pm_descr = 78 { 79 .pd_name = "", 80 .pd_class = -1, 81 .pd_caps = AMD_PMC_CAPS, 82 .pd_width = 48 83 }, 84 .pm_evsel = AMD_PMC_EVSEL_1, 85 .pm_perfctr = AMD_PMC_PERFCTR_1 86 }, 87 { 88 .pm_descr = 89 { 90 .pd_name = "", 91 .pd_class = -1, 92 .pd_caps = AMD_PMC_CAPS, 93 .pd_width = 48 94 }, 95 .pm_evsel = AMD_PMC_EVSEL_2, 96 .pm_perfctr = AMD_PMC_PERFCTR_2 97 }, 98 { 99 .pm_descr = 100 { 101 .pd_name = "", 102 .pd_class = -1, 103 .pd_caps = AMD_PMC_CAPS, 104 .pd_width = 48 105 }, 106 .pm_evsel = AMD_PMC_EVSEL_3, 107 .pm_perfctr = AMD_PMC_PERFCTR_3 108 } 109 }; 110 111 struct amd_event_code_map { 112 enum pmc_event pe_ev; /* enum value */ 113 uint16_t pe_code; /* encoded event mask */ 114 uint8_t pe_mask; /* bits allowed in unit mask */ 115 }; 116 117 const struct amd_event_code_map amd_event_codes[] = { 118 #if defined(__i386__) /* 32 bit Athlon (K7) only */ 119 { PMC_EV_K7_DC_ACCESSES, 0x40, 0 }, 120 { PMC_EV_K7_DC_MISSES, 0x41, 0 }, 121 { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI }, 122 { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI }, 123 { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI }, 124 { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 }, 125 { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 }, 126 { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 }, 127 128 { PMC_EV_K7_IC_FETCHES, 0x80, 0 }, 129 { PMC_EV_K7_IC_MISSES, 0x81, 0 }, 130 131 { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 }, 132 { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 }, 133 134 { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 }, 135 { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 }, 136 { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 }, 137 { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 }, 138 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 }, 139 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 }, 140 { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 }, 141 { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 }, 142 { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 }, 143 { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 }, 144 { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 }, 145 #endif 146 147 { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F }, 148 { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 }, 149 { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 }, 150 151 { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F }, 152 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE, 153 0x21, 0x00 }, 154 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 }, 155 { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 }, 156 { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 }, 157 { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 }, 158 { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 }, 159 { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 }, 160 161 { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 }, 162 { PMC_EV_K8_DC_MISS, 0x41, 0x00 }, 163 { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F }, 164 { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F }, 165 { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F }, 166 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 }, 167 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 }, 168 { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 }, 169 { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 }, 170 { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 }, 171 { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 }, 172 { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 }, 173 { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 }, 174 175 { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 }, 176 { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F }, 177 { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 }, 178 { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 }, 179 180 { PMC_EV_K8_IC_FETCH, 0x80, 0x00 }, 181 { PMC_EV_K8_IC_MISS, 0x81, 0x00 }, 182 { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 }, 183 { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 }, 184 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 }, 185 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 }, 186 { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 }, 187 { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 }, 188 { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 }, 189 { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 }, 190 191 { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 }, 192 { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 }, 193 { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 }, 194 { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 }, 195 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 }, 196 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 }, 197 { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 }, 198 { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 }, 199 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 }, 200 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 }, 201 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE, 202 0xCA, 0x00 }, 203 { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F }, 204 { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS, 205 0xCC, 0x07 }, 206 { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 }, 207 { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 }, 208 { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 }, 209 210 { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 }, 211 { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 }, 212 { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE, 213 0xD2, 0x00 }, 214 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 }, 215 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 }, 216 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL, 217 0xD5, 0x00 }, 218 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL, 219 0xD6, 0x00 }, 220 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 }, 221 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 }, 222 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET, 223 0xD9, 0x00 }, 224 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING, 225 0xDA, 0x00 }, 226 { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F }, 227 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 }, 228 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 }, 229 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 }, 230 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 }, 231 232 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 }, 233 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 }, 234 { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED, 235 0xE2, 0x00 }, 236 { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 }, 237 { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F }, 238 { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F }, 239 { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F }, 240 { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F }, 241 { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F }, 242 { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F } 243 244 }; 245 246 const int amd_event_codes_size = nitems(amd_event_codes); 247 248 /* 249 * Per-processor information 250 */ 251 252 struct amd_cpu { 253 struct pmc_hw pc_amdpmcs[AMD_NPMCS]; 254 }; 255 256 static struct amd_cpu **amd_pcpu; 257 258 /* 259 * read a pmc register 260 */ 261 262 static int 263 amd_read_pmc(int cpu, int ri, pmc_value_t *v) 264 { 265 enum pmc_mode mode; 266 const struct amd_descr *pd; 267 struct pmc *pm; 268 pmc_value_t tmp; 269 270 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 271 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 272 KASSERT(ri >= 0 && ri < AMD_NPMCS, 273 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 274 KASSERT(amd_pcpu[cpu], 275 ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu)); 276 277 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 278 pd = &amd_pmcdesc[ri]; 279 280 KASSERT(pm != NULL, 281 ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__, 282 cpu, ri)); 283 284 mode = PMC_TO_MODE(pm); 285 286 PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class); 287 288 #ifdef HWPMC_DEBUG 289 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 290 ("[amd,%d] unknown PMC class (%d)", __LINE__, 291 pd->pm_descr.pd_class)); 292 #endif 293 294 tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */ 295 PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp); 296 if (PMC_IS_SAMPLING_MODE(mode)) { 297 /* Sign extend 48 bit value to 64 bits. */ 298 tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16); 299 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 300 } 301 *v = tmp; 302 303 PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v); 304 305 return 0; 306 } 307 308 /* 309 * Write a PMC MSR. 310 */ 311 312 static int 313 amd_write_pmc(int cpu, int ri, pmc_value_t v) 314 { 315 const struct amd_descr *pd; 316 enum pmc_mode mode; 317 struct pmc *pm; 318 319 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 320 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 321 KASSERT(ri >= 0 && ri < AMD_NPMCS, 322 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 323 324 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 325 pd = &amd_pmcdesc[ri]; 326 327 KASSERT(pm != NULL, 328 ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__, 329 cpu, ri)); 330 331 mode = PMC_TO_MODE(pm); 332 333 #ifdef HWPMC_DEBUG 334 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 335 ("[amd,%d] unknown PMC class (%d)", __LINE__, 336 pd->pm_descr.pd_class)); 337 #endif 338 339 /* use 2's complement of the count for sampling mode PMCs */ 340 if (PMC_IS_SAMPLING_MODE(mode)) 341 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 342 343 PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v); 344 345 /* write the PMC value */ 346 wrmsr(pd->pm_perfctr, v); 347 return 0; 348 } 349 350 /* 351 * configure hardware pmc according to the configuration recorded in 352 * pmc 'pm'. 353 */ 354 355 static int 356 amd_config_pmc(int cpu, int ri, struct pmc *pm) 357 { 358 struct pmc_hw *phw; 359 360 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 361 362 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 363 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 364 KASSERT(ri >= 0 && ri < AMD_NPMCS, 365 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 366 367 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 368 369 KASSERT(pm == NULL || phw->phw_pmc == NULL, 370 ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 371 __LINE__, pm, phw->phw_pmc)); 372 373 phw->phw_pmc = pm; 374 return 0; 375 } 376 377 /* 378 * Retrieve a configured PMC pointer from hardware state. 379 */ 380 381 static int 382 amd_get_config(int cpu, int ri, struct pmc **ppm) 383 { 384 *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 385 386 return 0; 387 } 388 389 /* 390 * Machine dependent actions taken during the context switch in of a 391 * thread. 392 */ 393 394 static int 395 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 396 { 397 (void) pc; 398 399 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 400 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0); 401 402 /* enable the RDPMC instruction if needed */ 403 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 404 load_cr4(rcr4() | CR4_PCE); 405 406 return 0; 407 } 408 409 /* 410 * Machine dependent actions taken during the context switch out of a 411 * thread. 412 */ 413 414 static int 415 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 416 { 417 (void) pc; 418 (void) pp; /* can be NULL */ 419 420 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ? 421 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0); 422 423 /* always turn off the RDPMC instruction */ 424 load_cr4(rcr4() & ~CR4_PCE); 425 426 return 0; 427 } 428 429 /* 430 * Check if a given allocation is feasible. 431 */ 432 433 static int 434 amd_allocate_pmc(int cpu, int ri, struct pmc *pm, 435 const struct pmc_op_pmcallocate *a) 436 { 437 int i; 438 uint32_t allowed_unitmask, caps, config, unitmask; 439 enum pmc_event pe; 440 const struct pmc_descr *pd; 441 442 (void) cpu; 443 444 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 445 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 446 KASSERT(ri >= 0 && ri < AMD_NPMCS, 447 ("[amd,%d] illegal row index %d", __LINE__, ri)); 448 449 pd = &amd_pmcdesc[ri].pm_descr; 450 451 /* check class match */ 452 if (pd->pd_class != a->pm_class) 453 return EINVAL; 454 455 caps = pm->pm_caps; 456 457 PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps); 458 459 if ((pd->pd_caps & caps) != caps) 460 return EPERM; 461 if (strlen(pmc_cpuid) != 0) { 462 pm->pm_md.pm_amd.pm_amd_evsel = 463 a->pm_md.pm_amd.pm_amd_config; 464 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, a->pm_md.pm_amd.pm_amd_config); 465 return (0); 466 } 467 468 pe = a->pm_ev; 469 470 /* map ev to the correct event mask code */ 471 config = allowed_unitmask = 0; 472 for (i = 0; i < amd_event_codes_size; i++) 473 if (amd_event_codes[i].pe_ev == pe) { 474 config = 475 AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code); 476 allowed_unitmask = 477 AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask); 478 break; 479 } 480 if (i == amd_event_codes_size) 481 return EINVAL; 482 483 unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK; 484 if (unitmask & ~allowed_unitmask) /* disallow reserved bits */ 485 return EINVAL; 486 487 if (unitmask && (caps & PMC_CAP_QUALIFIER)) 488 config |= unitmask; 489 490 if (caps & PMC_CAP_THRESHOLD) 491 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK; 492 493 /* set at least one of the 'usr' or 'os' caps */ 494 if (caps & PMC_CAP_USER) 495 config |= AMD_PMC_USR; 496 if (caps & PMC_CAP_SYSTEM) 497 config |= AMD_PMC_OS; 498 if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0) 499 config |= (AMD_PMC_USR|AMD_PMC_OS); 500 501 if (caps & PMC_CAP_EDGE) 502 config |= AMD_PMC_EDGE; 503 if (caps & PMC_CAP_INVERT) 504 config |= AMD_PMC_INVERT; 505 if (caps & PMC_CAP_INTERRUPT) 506 config |= AMD_PMC_INT; 507 508 pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */ 509 510 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config); 511 512 return 0; 513 } 514 515 /* 516 * Release machine dependent state associated with a PMC. This is a 517 * no-op on this architecture. 518 * 519 */ 520 521 /* ARGSUSED0 */ 522 static int 523 amd_release_pmc(int cpu, int ri, struct pmc *pmc) 524 { 525 #ifdef HWPMC_DEBUG 526 const struct amd_descr *pd; 527 #endif 528 struct pmc_hw *phw; 529 530 (void) pmc; 531 532 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 533 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 534 KASSERT(ri >= 0 && ri < AMD_NPMCS, 535 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 536 537 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 538 539 KASSERT(phw->phw_pmc == NULL, 540 ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 541 542 #ifdef HWPMC_DEBUG 543 pd = &amd_pmcdesc[ri]; 544 if (pd->pm_descr.pd_class == amd_pmc_class) 545 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 546 ("[amd,%d] PMC %d released while active", __LINE__, ri)); 547 #endif 548 549 return 0; 550 } 551 552 /* 553 * start a PMC. 554 */ 555 556 static int 557 amd_start_pmc(int cpu, int ri) 558 { 559 uint32_t config; 560 struct pmc *pm; 561 struct pmc_hw *phw; 562 const struct amd_descr *pd; 563 564 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 565 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 566 KASSERT(ri >= 0 && ri < AMD_NPMCS, 567 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 568 569 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 570 pm = phw->phw_pmc; 571 pd = &amd_pmcdesc[ri]; 572 573 KASSERT(pm != NULL, 574 ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__, 575 cpu, ri)); 576 577 PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri); 578 579 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 580 ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__, 581 ri, cpu, pd->pm_descr.pd_name)); 582 583 /* turn on the PMC ENABLE bit */ 584 config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE; 585 586 PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config); 587 588 wrmsr(pd->pm_evsel, config); 589 return 0; 590 } 591 592 /* 593 * Stop a PMC. 594 */ 595 596 static int 597 amd_stop_pmc(int cpu, int ri) 598 { 599 struct pmc *pm; 600 struct pmc_hw *phw; 601 const struct amd_descr *pd; 602 uint64_t config; 603 604 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 605 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 606 KASSERT(ri >= 0 && ri < AMD_NPMCS, 607 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 608 609 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 610 pm = phw->phw_pmc; 611 pd = &amd_pmcdesc[ri]; 612 613 KASSERT(pm != NULL, 614 ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__, 615 cpu, ri)); 616 KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel), 617 ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped", 618 __LINE__, ri, cpu, pd->pm_descr.pd_name)); 619 620 PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri); 621 622 /* turn off the PMC ENABLE bit */ 623 config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE; 624 wrmsr(pd->pm_evsel, config); 625 return 0; 626 } 627 628 /* 629 * Interrupt handler. This function needs to return '1' if the 630 * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed 631 * to sleep or do anything a 'fast' interrupt handler is not allowed 632 * to do. 633 */ 634 635 static int 636 amd_intr(struct trapframe *tf) 637 { 638 int i, error, retval, cpu; 639 uint32_t config, evsel, perfctr; 640 struct pmc *pm; 641 struct amd_cpu *pac; 642 pmc_value_t v; 643 644 cpu = curcpu; 645 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 646 ("[amd,%d] out of range CPU %d", __LINE__, cpu)); 647 648 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf, 649 TRAPF_USERMODE(tf)); 650 651 retval = 0; 652 653 pac = amd_pcpu[cpu]; 654 655 /* 656 * look for all PMCs that have interrupted: 657 * - look for a running, sampling PMC which has overflowed 658 * and which has a valid 'struct pmc' association 659 * 660 * If found, we call a helper to process the interrupt. 661 * 662 * If multiple PMCs interrupt at the same time, the AMD64 663 * processor appears to deliver as many NMIs as there are 664 * outstanding PMC interrupts. So we process only one NMI 665 * interrupt at a time. 666 */ 667 668 for (i = 0; retval == 0 && i < AMD_NPMCS; i++) { 669 670 if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL || 671 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 672 continue; 673 } 674 675 if (!AMD_PMC_HAS_OVERFLOWED(i)) 676 continue; 677 678 retval = 1; /* Found an interrupting PMC. */ 679 680 if (pm->pm_state != PMC_STATE_RUNNING) 681 continue; 682 683 /* Stop the PMC, reload count. */ 684 evsel = AMD_PMC_EVSEL_0 + i; 685 perfctr = AMD_PMC_PERFCTR_0 + i; 686 v = pm->pm_sc.pm_reloadcount; 687 config = rdmsr(evsel); 688 689 KASSERT((config & ~AMD_PMC_ENABLE) == 690 (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE), 691 ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__, 692 config, pm->pm_md.pm_amd.pm_amd_evsel)); 693 694 wrmsr(evsel, config & ~AMD_PMC_ENABLE); 695 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); 696 697 /* Restart the counter if logging succeeded. */ 698 error = pmc_process_interrupt(PMC_HR, pm, tf); 699 if (error == 0) 700 wrmsr(evsel, config); 701 } 702 703 if (retval) 704 counter_u64_add(pmc_stats.pm_intr_processed, 1); 705 else 706 counter_u64_add(pmc_stats.pm_intr_ignored, 1); 707 708 PMCDBG1(MDP,INT,2, "retval=%d", retval); 709 return (retval); 710 } 711 712 /* 713 * describe a PMC 714 */ 715 static int 716 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 717 { 718 int error; 719 size_t copied; 720 const struct amd_descr *pd; 721 struct pmc_hw *phw; 722 723 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 724 ("[amd,%d] illegal CPU %d", __LINE__, cpu)); 725 KASSERT(ri >= 0 && ri < AMD_NPMCS, 726 ("[amd,%d] row-index %d out of range", __LINE__, ri)); 727 728 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 729 pd = &amd_pmcdesc[ri]; 730 731 if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name, 732 PMC_NAME_MAX, &copied)) != 0) 733 return error; 734 735 pi->pm_class = pd->pm_descr.pd_class; 736 737 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 738 pi->pm_enabled = TRUE; 739 *ppmc = phw->phw_pmc; 740 } else { 741 pi->pm_enabled = FALSE; 742 *ppmc = NULL; 743 } 744 745 return 0; 746 } 747 748 /* 749 * i386 specific entry points 750 */ 751 752 /* 753 * return the MSR address of the given PMC. 754 */ 755 756 static int 757 amd_get_msr(int ri, uint32_t *msr) 758 { 759 KASSERT(ri >= 0 && ri < AMD_NPMCS, 760 ("[amd,%d] ri %d out of range", __LINE__, ri)); 761 762 *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; 763 764 return (0); 765 } 766 767 /* 768 * processor dependent initialization. 769 */ 770 771 static int 772 amd_pcpu_init(struct pmc_mdep *md, int cpu) 773 { 774 int classindex, first_ri, n; 775 struct pmc_cpu *pc; 776 struct amd_cpu *pac; 777 struct pmc_hw *phw; 778 779 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 780 ("[amd,%d] insane cpu number %d", __LINE__, cpu)); 781 782 PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu); 783 784 amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC, 785 M_WAITOK|M_ZERO); 786 787 /* 788 * Set the content of the hardware descriptors to a known 789 * state and initialize pointers in the MI per-cpu descriptor. 790 */ 791 pc = pmc_pcpu[cpu]; 792 #if defined(__amd64__) 793 classindex = PMC_MDEP_CLASS_INDEX_K8; 794 #elif defined(__i386__) 795 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? 796 PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7; 797 #endif 798 first_ri = md->pmd_classdep[classindex].pcd_ri; 799 800 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__)); 801 802 for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) { 803 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 804 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); 805 phw->phw_pmc = NULL; 806 pc->pc_hwpmcs[n + first_ri] = phw; 807 } 808 809 return (0); 810 } 811 812 813 /* 814 * processor dependent cleanup prior to the KLD 815 * being unloaded 816 */ 817 818 static int 819 amd_pcpu_fini(struct pmc_mdep *md, int cpu) 820 { 821 int classindex, first_ri, i; 822 uint32_t evsel; 823 struct pmc_cpu *pc; 824 struct amd_cpu *pac; 825 826 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 827 ("[amd,%d] insane cpu number (%d)", __LINE__, cpu)); 828 829 PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu); 830 831 /* 832 * First, turn off all PMCs on this CPU. 833 */ 834 for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */ 835 evsel = rdmsr(AMD_PMC_EVSEL_0 + i); 836 evsel &= ~AMD_PMC_ENABLE; 837 wrmsr(AMD_PMC_EVSEL_0 + i, evsel); 838 } 839 840 /* 841 * Next, free up allocated space. 842 */ 843 if ((pac = amd_pcpu[cpu]) == NULL) 844 return (0); 845 846 amd_pcpu[cpu] = NULL; 847 848 #ifdef HWPMC_DEBUG 849 for (i = 0; i < AMD_NPMCS; i++) { 850 KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL, 851 ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i)); 852 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i), 853 ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i)); 854 } 855 #endif 856 857 pc = pmc_pcpu[cpu]; 858 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__)); 859 860 #if defined(__amd64__) 861 classindex = PMC_MDEP_CLASS_INDEX_K8; 862 #elif defined(__i386__) 863 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 : 864 PMC_MDEP_CLASS_INDEX_K7; 865 #endif 866 first_ri = md->pmd_classdep[classindex].pcd_ri; 867 868 /* 869 * Reset pointers in the MI 'per-cpu' state. 870 */ 871 for (i = 0; i < AMD_NPMCS; i++) { 872 pc->pc_hwpmcs[i + first_ri] = NULL; 873 } 874 875 876 free(pac, M_PMC); 877 878 return (0); 879 } 880 881 /* 882 * Initialize ourselves. 883 */ 884 885 struct pmc_mdep * 886 pmc_amd_initialize(void) 887 { 888 int classindex, error, i, ncpus; 889 struct pmc_classdep *pcd; 890 enum pmc_cputype cputype; 891 struct pmc_mdep *pmc_mdep; 892 enum pmc_class class; 893 int model; 894 char *name; 895 896 /* 897 * The presence of hardware performance counters on the AMD 898 * Athlon, Duron or later processors, is _not_ indicated by 899 * any of the processor feature flags set by the 'CPUID' 900 * instruction, so we only check the 'instruction family' 901 * field returned by CPUID for instruction family >= 6. 902 */ 903 904 name = NULL; 905 model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); 906 if (CPUID_TO_FAMILY(cpu_id) == 0x17) 907 snprintf(pmc_cpuid, sizeof(pmc_cpuid), "AuthenticAMD-%d-%02X", 908 CPUID_TO_FAMILY(cpu_id), model); 909 910 switch (cpu_id & 0xF00) { 911 #if defined(__i386__) 912 case 0x600: /* Athlon(tm) processor */ 913 classindex = PMC_MDEP_CLASS_INDEX_K7; 914 cputype = PMC_CPU_AMD_K7; 915 class = PMC_CLASS_K7; 916 name = "K7"; 917 break; 918 #endif 919 case 0xF00: /* Athlon64/Opteron processor */ 920 classindex = PMC_MDEP_CLASS_INDEX_K8; 921 cputype = PMC_CPU_AMD_K8; 922 class = PMC_CLASS_K8; 923 name = "K8"; 924 break; 925 926 default: 927 (void) printf("pmc: Unknown AMD CPU %x %d-%d.\n", cpu_id, (cpu_id & 0xF00) >> 8, model); 928 return NULL; 929 } 930 931 #ifdef HWPMC_DEBUG 932 amd_pmc_class = class; 933 #endif 934 935 /* 936 * Allocate space for pointers to PMC HW descriptors and for 937 * the MDEP structure used by MI code. 938 */ 939 amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC, 940 M_WAITOK|M_ZERO); 941 942 /* 943 * These processors have two classes of PMCs: the TSC and 944 * programmable PMCs. 945 */ 946 pmc_mdep = pmc_mdep_alloc(2); 947 948 pmc_mdep->pmd_cputype = cputype; 949 950 ncpus = pmc_cpu_max(); 951 952 /* Initialize the TSC. */ 953 error = pmc_tsc_initialize(pmc_mdep, ncpus); 954 if (error) 955 goto error; 956 957 /* Initialize AMD K7 and K8 PMC handling. */ 958 pcd = &pmc_mdep->pmd_classdep[classindex]; 959 960 pcd->pcd_caps = AMD_PMC_CAPS; 961 pcd->pcd_class = class; 962 pcd->pcd_num = AMD_NPMCS; 963 pcd->pcd_ri = pmc_mdep->pmd_npmc; 964 pcd->pcd_width = 48; 965 966 /* fill in the correct pmc name and class */ 967 for (i = 0; i < AMD_NPMCS; i++) { 968 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name, 969 sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d", 970 name, i); 971 amd_pmcdesc[i].pm_descr.pd_class = class; 972 } 973 974 pcd->pcd_allocate_pmc = amd_allocate_pmc; 975 pcd->pcd_config_pmc = amd_config_pmc; 976 pcd->pcd_describe = amd_describe; 977 pcd->pcd_get_config = amd_get_config; 978 pcd->pcd_get_msr = amd_get_msr; 979 pcd->pcd_pcpu_fini = amd_pcpu_fini; 980 pcd->pcd_pcpu_init = amd_pcpu_init; 981 pcd->pcd_read_pmc = amd_read_pmc; 982 pcd->pcd_release_pmc = amd_release_pmc; 983 pcd->pcd_start_pmc = amd_start_pmc; 984 pcd->pcd_stop_pmc = amd_stop_pmc; 985 pcd->pcd_write_pmc = amd_write_pmc; 986 987 pmc_mdep->pmd_pcpu_init = NULL; 988 pmc_mdep->pmd_pcpu_fini = NULL; 989 pmc_mdep->pmd_intr = amd_intr; 990 pmc_mdep->pmd_switch_in = amd_switch_in; 991 pmc_mdep->pmd_switch_out = amd_switch_out; 992 993 pmc_mdep->pmd_npmc += AMD_NPMCS; 994 995 PMCDBG0(MDP,INI,0,"amd-initialize"); 996 997 return (pmc_mdep); 998 999 error: 1000 if (error) { 1001 free(pmc_mdep, M_PMC); 1002 pmc_mdep = NULL; 1003 } 1004 1005 return (NULL); 1006 } 1007 1008 /* 1009 * Finalization code for AMD CPUs. 1010 */ 1011 1012 void 1013 pmc_amd_finalize(struct pmc_mdep *md) 1014 { 1015 #if defined(INVARIANTS) 1016 int classindex, i, ncpus, pmcclass; 1017 #endif 1018 1019 pmc_tsc_finalize(md); 1020 1021 KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer", 1022 __LINE__)); 1023 1024 #if defined(INVARIANTS) 1025 switch (md->pmd_cputype) { 1026 #if defined(__i386__) 1027 case PMC_CPU_AMD_K7: 1028 classindex = PMC_MDEP_CLASS_INDEX_K7; 1029 pmcclass = PMC_CLASS_K7; 1030 break; 1031 #endif 1032 default: 1033 classindex = PMC_MDEP_CLASS_INDEX_K8; 1034 pmcclass = PMC_CLASS_K8; 1035 } 1036 1037 KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass, 1038 ("[amd,%d] pmc class mismatch", __LINE__)); 1039 1040 ncpus = pmc_cpu_max(); 1041 1042 for (i = 0; i < ncpus; i++) 1043 KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu", 1044 __LINE__)); 1045 #endif 1046 1047 free(amd_pcpu, M_PMC); 1048 amd_pcpu = NULL; 1049 } 1050