1 /*- 2 * Copyright (c) 2003-2008 Joseph Koshy 3 * Copyright (c) 2007 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by A. Joseph Koshy under 7 * sponsorship from the FreeBSD Foundation and Google, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* Support for the AMD K7 and later processors */ 35 36 #include <sys/param.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mutex.h> 40 #include <sys/pmc.h> 41 #include <sys/pmckern.h> 42 #include <sys/smp.h> 43 #include <sys/systm.h> 44 45 #include <machine/cpu.h> 46 #include <machine/cpufunc.h> 47 #include <machine/md_var.h> 48 #include <machine/specialreg.h> 49 50 #ifdef HWPMC_DEBUG 51 enum pmc_class amd_pmc_class; 52 #endif 53 54 /* AMD K7 & K8 PMCs */ 55 struct amd_descr { 56 struct pmc_descr pm_descr; /* "base class" */ 57 uint32_t pm_evsel; /* address of EVSEL register */ 58 uint32_t pm_perfctr; /* address of PERFCTR register */ 59 }; 60 61 static struct amd_descr amd_pmcdesc[AMD_NPMCS] = 62 { 63 { 64 .pm_descr = 65 { 66 .pd_name = "", 67 .pd_class = -1, 68 .pd_caps = AMD_PMC_CAPS, 69 .pd_width = 48 70 }, 71 .pm_evsel = AMD_PMC_EVSEL_0, 72 .pm_perfctr = AMD_PMC_PERFCTR_0 73 }, 74 { 75 .pm_descr = 76 { 77 .pd_name = "", 78 .pd_class = -1, 79 .pd_caps = AMD_PMC_CAPS, 80 .pd_width = 48 81 }, 82 .pm_evsel = AMD_PMC_EVSEL_1, 83 .pm_perfctr = AMD_PMC_PERFCTR_1 84 }, 85 { 86 .pm_descr = 87 { 88 .pd_name = "", 89 .pd_class = -1, 90 .pd_caps = AMD_PMC_CAPS, 91 .pd_width = 48 92 }, 93 .pm_evsel = AMD_PMC_EVSEL_2, 94 .pm_perfctr = AMD_PMC_PERFCTR_2 95 }, 96 { 97 .pm_descr = 98 { 99 .pd_name = "", 100 .pd_class = -1, 101 .pd_caps = AMD_PMC_CAPS, 102 .pd_width = 48 103 }, 104 .pm_evsel = AMD_PMC_EVSEL_3, 105 .pm_perfctr = AMD_PMC_PERFCTR_3 106 } 107 }; 108 109 struct amd_event_code_map { 110 enum pmc_event pe_ev; /* enum value */ 111 uint8_t pe_code; /* encoded event mask */ 112 uint8_t pe_mask; /* bits allowed in unit mask */ 113 }; 114 115 const struct amd_event_code_map amd_event_codes[] = { 116 #if defined(__i386__) /* 32 bit Athlon (K7) only */ 117 { PMC_EV_K7_DC_ACCESSES, 0x40, 0 }, 118 { PMC_EV_K7_DC_MISSES, 0x41, 0 }, 119 { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI }, 120 { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI }, 121 { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI }, 122 { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 }, 123 { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 }, 124 { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 }, 125 126 { PMC_EV_K7_IC_FETCHES, 0x80, 0 }, 127 { PMC_EV_K7_IC_MISSES, 0x81, 0 }, 128 129 { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 }, 130 { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 }, 131 132 { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 }, 133 { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 }, 134 { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 }, 135 { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 }, 136 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 }, 137 { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 }, 138 { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 }, 139 { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 }, 140 { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 }, 141 { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 }, 142 { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 }, 143 #endif 144 145 { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F }, 146 { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 }, 147 { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 }, 148 149 { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F }, 150 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE, 151 0x21, 0x00 }, 152 { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 }, 153 { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 }, 154 { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 }, 155 { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 }, 156 { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 }, 157 { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 }, 158 159 { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 }, 160 { PMC_EV_K8_DC_MISS, 0x41, 0x00 }, 161 { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F }, 162 { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F }, 163 { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F }, 164 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 }, 165 { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 }, 166 { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 }, 167 { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 }, 168 { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 }, 169 { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 }, 170 { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 }, 171 { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 }, 172 173 { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 }, 174 { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F }, 175 { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 }, 176 { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 }, 177 178 { PMC_EV_K8_IC_FETCH, 0x80, 0x00 }, 179 { PMC_EV_K8_IC_MISS, 0x81, 0x00 }, 180 { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 }, 181 { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 }, 182 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 }, 183 { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 }, 184 { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 }, 185 { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 }, 186 { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 }, 187 { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 }, 188 189 { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 }, 190 { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 }, 191 { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 }, 192 { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 }, 193 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 }, 194 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 }, 195 { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 }, 196 { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 }, 197 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 }, 198 { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 }, 199 { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE, 200 0xCA, 0x00 }, 201 { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F }, 202 { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS, 203 0xCC, 0x07 }, 204 { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 }, 205 { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 }, 206 { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 }, 207 208 { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 }, 209 { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 }, 210 { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE, 211 0xD2, 0x00 }, 212 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 }, 213 { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 }, 214 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL, 215 0xD5, 0x00 }, 216 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL, 217 0xD6, 0x00 }, 218 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 }, 219 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 }, 220 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET, 221 0xD9, 0x00 }, 222 { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING, 223 0xDA, 0x00 }, 224 { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F }, 225 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 }, 226 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 }, 227 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 }, 228 { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 }, 229 230 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 }, 231 { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 }, 232 { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED, 233 0xE2, 0x00 }, 234 { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 }, 235 { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F }, 236 { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F }, 237 { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F }, 238 { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F }, 239 { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F }, 240 { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F } 241 242 }; 243 244 const int amd_event_codes_size = nitems(amd_event_codes); 245 246 /* 247 * Per-processor information 248 */ 249 250 struct amd_cpu { 251 struct pmc_hw pc_amdpmcs[AMD_NPMCS]; 252 }; 253 254 static struct amd_cpu **amd_pcpu; 255 256 /* 257 * read a pmc register 258 */ 259 260 static int 261 amd_read_pmc(int cpu, int ri, pmc_value_t *v) 262 { 263 enum pmc_mode mode; 264 const struct amd_descr *pd; 265 struct pmc *pm; 266 pmc_value_t tmp; 267 268 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 269 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 270 KASSERT(ri >= 0 && ri < AMD_NPMCS, 271 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 272 KASSERT(amd_pcpu[cpu], 273 ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu)); 274 275 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 276 pd = &amd_pmcdesc[ri]; 277 278 KASSERT(pm != NULL, 279 ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__, 280 cpu, ri)); 281 282 mode = PMC_TO_MODE(pm); 283 284 PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class); 285 286 #ifdef HWPMC_DEBUG 287 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 288 ("[amd,%d] unknown PMC class (%d)", __LINE__, 289 pd->pm_descr.pd_class)); 290 #endif 291 292 tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */ 293 PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp); 294 if (PMC_IS_SAMPLING_MODE(mode)) { 295 /* Sign extend 48 bit value to 64 bits. */ 296 tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16); 297 tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); 298 } 299 *v = tmp; 300 301 PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v); 302 303 return 0; 304 } 305 306 /* 307 * Write a PMC MSR. 308 */ 309 310 static int 311 amd_write_pmc(int cpu, int ri, pmc_value_t v) 312 { 313 const struct amd_descr *pd; 314 enum pmc_mode mode; 315 struct pmc *pm; 316 317 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 318 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 319 KASSERT(ri >= 0 && ri < AMD_NPMCS, 320 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 321 322 pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 323 pd = &amd_pmcdesc[ri]; 324 325 KASSERT(pm != NULL, 326 ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__, 327 cpu, ri)); 328 329 mode = PMC_TO_MODE(pm); 330 331 #ifdef HWPMC_DEBUG 332 KASSERT(pd->pm_descr.pd_class == amd_pmc_class, 333 ("[amd,%d] unknown PMC class (%d)", __LINE__, 334 pd->pm_descr.pd_class)); 335 #endif 336 337 /* use 2's complement of the count for sampling mode PMCs */ 338 if (PMC_IS_SAMPLING_MODE(mode)) 339 v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v); 340 341 PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v); 342 343 /* write the PMC value */ 344 wrmsr(pd->pm_perfctr, v); 345 return 0; 346 } 347 348 /* 349 * configure hardware pmc according to the configuration recorded in 350 * pmc 'pm'. 351 */ 352 353 static int 354 amd_config_pmc(int cpu, int ri, struct pmc *pm) 355 { 356 struct pmc_hw *phw; 357 358 PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); 359 360 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 361 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 362 KASSERT(ri >= 0 && ri < AMD_NPMCS, 363 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 364 365 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 366 367 KASSERT(pm == NULL || phw->phw_pmc == NULL, 368 ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured", 369 __LINE__, pm, phw->phw_pmc)); 370 371 phw->phw_pmc = pm; 372 return 0; 373 } 374 375 /* 376 * Retrieve a configured PMC pointer from hardware state. 377 */ 378 379 static int 380 amd_get_config(int cpu, int ri, struct pmc **ppm) 381 { 382 *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; 383 384 return 0; 385 } 386 387 /* 388 * Machine dependent actions taken during the context switch in of a 389 * thread. 390 */ 391 392 static int 393 amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) 394 { 395 (void) pc; 396 397 PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, 398 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0); 399 400 /* enable the RDPMC instruction if needed */ 401 if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) 402 load_cr4(rcr4() | CR4_PCE); 403 404 return 0; 405 } 406 407 /* 408 * Machine dependent actions taken during the context switch out of a 409 * thread. 410 */ 411 412 static int 413 amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) 414 { 415 (void) pc; 416 (void) pp; /* can be NULL */ 417 418 PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ? 419 (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0); 420 421 /* always turn off the RDPMC instruction */ 422 load_cr4(rcr4() & ~CR4_PCE); 423 424 return 0; 425 } 426 427 /* 428 * Check if a given allocation is feasible. 429 */ 430 431 static int 432 amd_allocate_pmc(int cpu, int ri, struct pmc *pm, 433 const struct pmc_op_pmcallocate *a) 434 { 435 int i; 436 uint32_t allowed_unitmask, caps, config, unitmask; 437 enum pmc_event pe; 438 const struct pmc_descr *pd; 439 440 (void) cpu; 441 442 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 443 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 444 KASSERT(ri >= 0 && ri < AMD_NPMCS, 445 ("[amd,%d] illegal row index %d", __LINE__, ri)); 446 447 pd = &amd_pmcdesc[ri].pm_descr; 448 449 /* check class match */ 450 if (pd->pd_class != a->pm_class) 451 return EINVAL; 452 453 caps = pm->pm_caps; 454 455 PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps); 456 457 if ((pd->pd_caps & caps) != caps) 458 return EPERM; 459 460 pe = a->pm_ev; 461 462 /* map ev to the correct event mask code */ 463 config = allowed_unitmask = 0; 464 for (i = 0; i < amd_event_codes_size; i++) 465 if (amd_event_codes[i].pe_ev == pe) { 466 config = 467 AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code); 468 allowed_unitmask = 469 AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask); 470 break; 471 } 472 if (i == amd_event_codes_size) 473 return EINVAL; 474 475 unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK; 476 if (unitmask & ~allowed_unitmask) /* disallow reserved bits */ 477 return EINVAL; 478 479 if (unitmask && (caps & PMC_CAP_QUALIFIER)) 480 config |= unitmask; 481 482 if (caps & PMC_CAP_THRESHOLD) 483 config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK; 484 485 /* set at least one of the 'usr' or 'os' caps */ 486 if (caps & PMC_CAP_USER) 487 config |= AMD_PMC_USR; 488 if (caps & PMC_CAP_SYSTEM) 489 config |= AMD_PMC_OS; 490 if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0) 491 config |= (AMD_PMC_USR|AMD_PMC_OS); 492 493 if (caps & PMC_CAP_EDGE) 494 config |= AMD_PMC_EDGE; 495 if (caps & PMC_CAP_INVERT) 496 config |= AMD_PMC_INVERT; 497 if (caps & PMC_CAP_INTERRUPT) 498 config |= AMD_PMC_INT; 499 500 pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */ 501 502 PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config); 503 504 return 0; 505 } 506 507 /* 508 * Release machine dependent state associated with a PMC. This is a 509 * no-op on this architecture. 510 * 511 */ 512 513 /* ARGSUSED0 */ 514 static int 515 amd_release_pmc(int cpu, int ri, struct pmc *pmc) 516 { 517 #ifdef HWPMC_DEBUG 518 const struct amd_descr *pd; 519 #endif 520 struct pmc_hw *phw; 521 522 (void) pmc; 523 524 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 525 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 526 KASSERT(ri >= 0 && ri < AMD_NPMCS, 527 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 528 529 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 530 531 KASSERT(phw->phw_pmc == NULL, 532 ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); 533 534 #ifdef HWPMC_DEBUG 535 pd = &amd_pmcdesc[ri]; 536 if (pd->pm_descr.pd_class == amd_pmc_class) 537 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 538 ("[amd,%d] PMC %d released while active", __LINE__, ri)); 539 #endif 540 541 return 0; 542 } 543 544 /* 545 * start a PMC. 546 */ 547 548 static int 549 amd_start_pmc(int cpu, int ri) 550 { 551 uint32_t config; 552 struct pmc *pm; 553 struct pmc_hw *phw; 554 const struct amd_descr *pd; 555 556 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 557 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 558 KASSERT(ri >= 0 && ri < AMD_NPMCS, 559 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 560 561 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 562 pm = phw->phw_pmc; 563 pd = &amd_pmcdesc[ri]; 564 565 KASSERT(pm != NULL, 566 ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__, 567 cpu, ri)); 568 569 PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri); 570 571 KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), 572 ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__, 573 ri, cpu, pd->pm_descr.pd_name)); 574 575 /* turn on the PMC ENABLE bit */ 576 config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE; 577 578 PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config); 579 580 wrmsr(pd->pm_evsel, config); 581 return 0; 582 } 583 584 /* 585 * Stop a PMC. 586 */ 587 588 static int 589 amd_stop_pmc(int cpu, int ri) 590 { 591 struct pmc *pm; 592 struct pmc_hw *phw; 593 const struct amd_descr *pd; 594 uint64_t config; 595 596 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 597 ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); 598 KASSERT(ri >= 0 && ri < AMD_NPMCS, 599 ("[amd,%d] illegal row-index %d", __LINE__, ri)); 600 601 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 602 pm = phw->phw_pmc; 603 pd = &amd_pmcdesc[ri]; 604 605 KASSERT(pm != NULL, 606 ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__, 607 cpu, ri)); 608 KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel), 609 ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped", 610 __LINE__, ri, cpu, pd->pm_descr.pd_name)); 611 612 PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri); 613 614 /* turn off the PMC ENABLE bit */ 615 config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE; 616 wrmsr(pd->pm_evsel, config); 617 return 0; 618 } 619 620 /* 621 * Interrupt handler. This function needs to return '1' if the 622 * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed 623 * to sleep or do anything a 'fast' interrupt handler is not allowed 624 * to do. 625 */ 626 627 static int 628 amd_intr(int cpu, struct trapframe *tf) 629 { 630 int i, error, retval; 631 uint32_t config, evsel, perfctr; 632 struct pmc *pm; 633 struct amd_cpu *pac; 634 pmc_value_t v; 635 636 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 637 ("[amd,%d] out of range CPU %d", __LINE__, cpu)); 638 639 PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf, 640 TRAPF_USERMODE(tf)); 641 642 retval = 0; 643 644 pac = amd_pcpu[cpu]; 645 646 /* 647 * look for all PMCs that have interrupted: 648 * - look for a running, sampling PMC which has overflowed 649 * and which has a valid 'struct pmc' association 650 * 651 * If found, we call a helper to process the interrupt. 652 * 653 * If multiple PMCs interrupt at the same time, the AMD64 654 * processor appears to deliver as many NMIs as there are 655 * outstanding PMC interrupts. So we process only one NMI 656 * interrupt at a time. 657 */ 658 659 for (i = 0; retval == 0 && i < AMD_NPMCS; i++) { 660 661 if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL || 662 !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { 663 continue; 664 } 665 666 if (!AMD_PMC_HAS_OVERFLOWED(i)) 667 continue; 668 669 retval = 1; /* Found an interrupting PMC. */ 670 671 if (pm->pm_state != PMC_STATE_RUNNING) 672 continue; 673 674 /* Stop the PMC, reload count. */ 675 evsel = AMD_PMC_EVSEL_0 + i; 676 perfctr = AMD_PMC_PERFCTR_0 + i; 677 v = pm->pm_sc.pm_reloadcount; 678 config = rdmsr(evsel); 679 680 KASSERT((config & ~AMD_PMC_ENABLE) == 681 (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE), 682 ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__, 683 config, pm->pm_md.pm_amd.pm_amd_evsel)); 684 685 wrmsr(evsel, config & ~AMD_PMC_ENABLE); 686 wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); 687 688 /* Restart the counter if logging succeeded. */ 689 error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, 690 TRAPF_USERMODE(tf)); 691 if (error == 0) 692 wrmsr(evsel, config | AMD_PMC_ENABLE); 693 } 694 695 atomic_add_int(retval ? &pmc_stats.pm_intr_processed : 696 &pmc_stats.pm_intr_ignored, 1); 697 698 return (retval); 699 } 700 701 /* 702 * describe a PMC 703 */ 704 static int 705 amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) 706 { 707 int error; 708 size_t copied; 709 const struct amd_descr *pd; 710 struct pmc_hw *phw; 711 712 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 713 ("[amd,%d] illegal CPU %d", __LINE__, cpu)); 714 KASSERT(ri >= 0 && ri < AMD_NPMCS, 715 ("[amd,%d] row-index %d out of range", __LINE__, ri)); 716 717 phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; 718 pd = &amd_pmcdesc[ri]; 719 720 if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name, 721 PMC_NAME_MAX, &copied)) != 0) 722 return error; 723 724 pi->pm_class = pd->pm_descr.pd_class; 725 726 if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { 727 pi->pm_enabled = TRUE; 728 *ppmc = phw->phw_pmc; 729 } else { 730 pi->pm_enabled = FALSE; 731 *ppmc = NULL; 732 } 733 734 return 0; 735 } 736 737 /* 738 * i386 specific entry points 739 */ 740 741 /* 742 * return the MSR address of the given PMC. 743 */ 744 745 static int 746 amd_get_msr(int ri, uint32_t *msr) 747 { 748 KASSERT(ri >= 0 && ri < AMD_NPMCS, 749 ("[amd,%d] ri %d out of range", __LINE__, ri)); 750 751 *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; 752 753 return (0); 754 } 755 756 /* 757 * processor dependent initialization. 758 */ 759 760 static int 761 amd_pcpu_init(struct pmc_mdep *md, int cpu) 762 { 763 int classindex, first_ri, n; 764 struct pmc_cpu *pc; 765 struct amd_cpu *pac; 766 struct pmc_hw *phw; 767 768 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 769 ("[amd,%d] insane cpu number %d", __LINE__, cpu)); 770 771 PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu); 772 773 amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC, 774 M_WAITOK|M_ZERO); 775 776 /* 777 * Set the content of the hardware descriptors to a known 778 * state and initialize pointers in the MI per-cpu descriptor. 779 */ 780 pc = pmc_pcpu[cpu]; 781 #if defined(__amd64__) 782 classindex = PMC_MDEP_CLASS_INDEX_K8; 783 #elif defined(__i386__) 784 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? 785 PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7; 786 #endif 787 first_ri = md->pmd_classdep[classindex].pcd_ri; 788 789 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__)); 790 791 for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) { 792 phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | 793 PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); 794 phw->phw_pmc = NULL; 795 pc->pc_hwpmcs[n + first_ri] = phw; 796 } 797 798 return (0); 799 } 800 801 802 /* 803 * processor dependent cleanup prior to the KLD 804 * being unloaded 805 */ 806 807 static int 808 amd_pcpu_fini(struct pmc_mdep *md, int cpu) 809 { 810 int classindex, first_ri, i; 811 uint32_t evsel; 812 struct pmc_cpu *pc; 813 struct amd_cpu *pac; 814 815 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), 816 ("[amd,%d] insane cpu number (%d)", __LINE__, cpu)); 817 818 PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu); 819 820 /* 821 * First, turn off all PMCs on this CPU. 822 */ 823 for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */ 824 evsel = rdmsr(AMD_PMC_EVSEL_0 + i); 825 evsel &= ~AMD_PMC_ENABLE; 826 wrmsr(AMD_PMC_EVSEL_0 + i, evsel); 827 } 828 829 /* 830 * Next, free up allocated space. 831 */ 832 if ((pac = amd_pcpu[cpu]) == NULL) 833 return (0); 834 835 amd_pcpu[cpu] = NULL; 836 837 #ifdef HWPMC_DEBUG 838 for (i = 0; i < AMD_NPMCS; i++) { 839 KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL, 840 ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i)); 841 KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i), 842 ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i)); 843 } 844 #endif 845 846 pc = pmc_pcpu[cpu]; 847 KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__)); 848 849 #if defined(__amd64__) 850 classindex = PMC_MDEP_CLASS_INDEX_K8; 851 #elif defined(__i386__) 852 classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 : 853 PMC_MDEP_CLASS_INDEX_K7; 854 #endif 855 first_ri = md->pmd_classdep[classindex].pcd_ri; 856 857 /* 858 * Reset pointers in the MI 'per-cpu' state. 859 */ 860 for (i = 0; i < AMD_NPMCS; i++) { 861 pc->pc_hwpmcs[i + first_ri] = NULL; 862 } 863 864 865 free(pac, M_PMC); 866 867 return (0); 868 } 869 870 /* 871 * Initialize ourselves. 872 */ 873 874 struct pmc_mdep * 875 pmc_amd_initialize(void) 876 { 877 int classindex, error, i, ncpus; 878 struct pmc_classdep *pcd; 879 enum pmc_cputype cputype; 880 struct pmc_mdep *pmc_mdep; 881 enum pmc_class class; 882 char *name; 883 884 /* 885 * The presence of hardware performance counters on the AMD 886 * Athlon, Duron or later processors, is _not_ indicated by 887 * any of the processor feature flags set by the 'CPUID' 888 * instruction, so we only check the 'instruction family' 889 * field returned by CPUID for instruction family >= 6. 890 */ 891 892 name = NULL; 893 switch (cpu_id & 0xF00) { 894 #if defined(__i386__) 895 case 0x600: /* Athlon(tm) processor */ 896 classindex = PMC_MDEP_CLASS_INDEX_K7; 897 cputype = PMC_CPU_AMD_K7; 898 class = PMC_CLASS_K7; 899 name = "K7"; 900 break; 901 #endif 902 case 0xF00: /* Athlon64/Opteron processor */ 903 classindex = PMC_MDEP_CLASS_INDEX_K8; 904 cputype = PMC_CPU_AMD_K8; 905 class = PMC_CLASS_K8; 906 name = "K8"; 907 break; 908 909 default: 910 (void) printf("pmc: Unknown AMD CPU.\n"); 911 return NULL; 912 } 913 914 #ifdef HWPMC_DEBUG 915 amd_pmc_class = class; 916 #endif 917 918 /* 919 * Allocate space for pointers to PMC HW descriptors and for 920 * the MDEP structure used by MI code. 921 */ 922 amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC, 923 M_WAITOK|M_ZERO); 924 925 /* 926 * These processors have two classes of PMCs: the TSC and 927 * programmable PMCs. 928 */ 929 pmc_mdep = pmc_mdep_alloc(2); 930 931 pmc_mdep->pmd_cputype = cputype; 932 933 ncpus = pmc_cpu_max(); 934 935 /* Initialize the TSC. */ 936 error = pmc_tsc_initialize(pmc_mdep, ncpus); 937 if (error) 938 goto error; 939 940 /* Initialize AMD K7 and K8 PMC handling. */ 941 pcd = &pmc_mdep->pmd_classdep[classindex]; 942 943 pcd->pcd_caps = AMD_PMC_CAPS; 944 pcd->pcd_class = class; 945 pcd->pcd_num = AMD_NPMCS; 946 pcd->pcd_ri = pmc_mdep->pmd_npmc; 947 pcd->pcd_width = 48; 948 949 /* fill in the correct pmc name and class */ 950 for (i = 0; i < AMD_NPMCS; i++) { 951 (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name, 952 sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d", 953 name, i); 954 amd_pmcdesc[i].pm_descr.pd_class = class; 955 } 956 957 pcd->pcd_allocate_pmc = amd_allocate_pmc; 958 pcd->pcd_config_pmc = amd_config_pmc; 959 pcd->pcd_describe = amd_describe; 960 pcd->pcd_get_config = amd_get_config; 961 pcd->pcd_get_msr = amd_get_msr; 962 pcd->pcd_pcpu_fini = amd_pcpu_fini; 963 pcd->pcd_pcpu_init = amd_pcpu_init; 964 pcd->pcd_read_pmc = amd_read_pmc; 965 pcd->pcd_release_pmc = amd_release_pmc; 966 pcd->pcd_start_pmc = amd_start_pmc; 967 pcd->pcd_stop_pmc = amd_stop_pmc; 968 pcd->pcd_write_pmc = amd_write_pmc; 969 970 pmc_mdep->pmd_pcpu_init = NULL; 971 pmc_mdep->pmd_pcpu_fini = NULL; 972 pmc_mdep->pmd_intr = amd_intr; 973 pmc_mdep->pmd_switch_in = amd_switch_in; 974 pmc_mdep->pmd_switch_out = amd_switch_out; 975 976 pmc_mdep->pmd_npmc += AMD_NPMCS; 977 978 PMCDBG0(MDP,INI,0,"amd-initialize"); 979 980 return (pmc_mdep); 981 982 error: 983 if (error) { 984 free(pmc_mdep, M_PMC); 985 pmc_mdep = NULL; 986 } 987 988 return (NULL); 989 } 990 991 /* 992 * Finalization code for AMD CPUs. 993 */ 994 995 void 996 pmc_amd_finalize(struct pmc_mdep *md) 997 { 998 #if defined(INVARIANTS) 999 int classindex, i, ncpus, pmcclass; 1000 #endif 1001 1002 pmc_tsc_finalize(md); 1003 1004 KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer", 1005 __LINE__)); 1006 1007 #if defined(INVARIANTS) 1008 switch (md->pmd_cputype) { 1009 #if defined(__i386__) 1010 case PMC_CPU_AMD_K7: 1011 classindex = PMC_MDEP_CLASS_INDEX_K7; 1012 pmcclass = PMC_CLASS_K7; 1013 break; 1014 #endif 1015 default: 1016 classindex = PMC_MDEP_CLASS_INDEX_K8; 1017 pmcclass = PMC_CLASS_K8; 1018 } 1019 1020 KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass, 1021 ("[amd,%d] pmc class mismatch", __LINE__)); 1022 1023 ncpus = pmc_cpu_max(); 1024 1025 for (i = 0; i < ncpus; i++) 1026 KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu", 1027 __LINE__)); 1028 #endif 1029 1030 free(amd_pcpu, M_PMC); 1031 amd_pcpu = NULL; 1032 } 1033