1 /* 2 * Copyright (c) 2003-2004 MARVELL SEMICONDUCTOR ISRAEL, LTD. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 #ifndef __INCmvSatah 27 #define __INCmvSatah 28 29 #ifndef SUPPORT_MV_SATA_GEN_1 30 #define SUPPORT_MV_SATA_GEN_1 1 31 #endif 32 33 #ifndef SUPPORT_MV_SATA_GEN_2 34 #define SUPPORT_MV_SATA_GEN_2 0 35 #endif 36 37 #if SUPPORT_MV_SATA_GEN_1==1 && SUPPORT_MV_SATA_GEN_2==1 38 #define MV_SATA_GEN_1(x) ((x)->sataAdapterGeneration==1) 39 #define MV_SATA_GEN_2(x) ((x)->sataAdapterGeneration==2) 40 #elif SUPPORT_MV_SATA_GEN_1==1 41 #define MV_SATA_GEN_1(x) 1 42 #define MV_SATA_GEN_2(x) 0 43 #elif SUPPORT_MV_SATA_GEN_2==1 44 #define MV_SATA_GEN_1(x) 0 45 #define MV_SATA_GEN_2(x) 1 46 #else 47 #error "Which IC do you support?" 48 #endif 49 50 /* Definitions */ 51 /* MV88SX50XX specific defines */ 52 #define MV_SATA_VENDOR_ID 0x11AB 53 #define MV_SATA_DEVICE_ID_5080 0x5080 54 #define MV_SATA_DEVICE_ID_5081 0x5081 55 #define MV_SATA_DEVICE_ID_6080 0x6080 56 #define MV_SATA_DEVICE_ID_6081 0x6081 57 #define MV_SATA_CHANNELS_NUM 8 58 #define MV_SATA_UNITS_NUM 2 59 #define MV_SATA_PCI_BAR0_SPACE_SIZE (1<<18) /* 256 Kb*/ 60 61 #define CHANNEL_QUEUE_LENGTH 32 62 #define CHANNEL_QUEUE_MASK 0x1F 63 64 #define MV_EDMA_QUEUE_LENGTH 32 /* Up to 32 outstanding */ 65 /* commands per SATA channel*/ 66 #define MV_EDMA_QUEUE_MASK 0x1F 67 #define MV_EDMA_REQUEST_QUEUE_SIZE 1024 /* 32*32 = 1KBytes */ 68 #define MV_EDMA_RESPONSE_QUEUE_SIZE 256 /* 32*8 = 256 Bytes */ 69 70 #define MV_EDMA_REQUEST_ENTRY_SIZE 32 71 #define MV_EDMA_RESPONSE_ENTRY_SIZE 8 72 73 #define MV_EDMA_PRD_ENTRY_SIZE 16 /* 16Bytes*/ 74 #define MV_EDMA_PRD_NO_SNOOP_FLAG 0x00000001 /* MV_BIT0 */ 75 #define MV_EDMA_PRD_EOT_FLAG 0x00008000 /* MV_BIT15 */ 76 77 #define MV_ATA_IDENTIFY_DEV_DATA_LENGTH 256 /* number of words(2 byte)*/ 78 #define MV_ATA_MODEL_NUMBER_LEN 40 79 #define ATA_SECTOR_SIZE 512 80 /* Log messages level defines */ 81 #define MV_DEBUG 0x1 82 #define MV_DEBUG_INIT 0x2 83 #define MV_DEBUG_INTERRUPTS 0x4 84 #define MV_DEBUG_SATA_LINK 0x8 85 #define MV_DEBUG_UDMA_COMMAND 0x10 86 #define MV_DEBUG_NON_UDMA_COMMAND 0x20 87 #define MV_DEBUG_ERROR 0x40 88 89 90 /* Typedefs */ 91 typedef enum mvUdmaType 92 { 93 MV_UDMA_TYPE_READ, MV_UDMA_TYPE_WRITE 94 } MV_UDMA_TYPE; 95 96 typedef enum mvFlushType 97 { 98 MV_FLUSH_TYPE_CALLBACK, MV_FLUSH_TYPE_NONE 99 } MV_FLUSH_TYPE; 100 101 typedef enum mvCompletionType 102 { 103 MV_COMPLETION_TYPE_NORMAL, MV_COMPLETION_TYPE_ERROR, 104 MV_COMPLETION_TYPE_ABORT 105 } MV_COMPLETION_TYPE; 106 107 typedef enum mvEventType 108 { 109 MV_EVENT_TYPE_ADAPTER_ERROR, MV_EVENT_TYPE_SATA_CABLE 110 } MV_EVENT_TYPE; 111 112 typedef enum mvEdmaMode 113 { 114 MV_EDMA_MODE_QUEUED, 115 MV_EDMA_MODE_NOT_QUEUED, 116 MV_EDMA_MODE_NATIVE_QUEUING 117 } MV_EDMA_MODE; 118 119 typedef enum mvEdmaQueueResult 120 { 121 MV_EDMA_QUEUE_RESULT_OK = 0, 122 MV_EDMA_QUEUE_RESULT_EDMA_DISABLED, 123 MV_EDMA_QUEUE_RESULT_FULL, 124 MV_EDMA_QUEUE_RESULT_BAD_LBA_ADDRESS, 125 MV_EDMA_QUEUE_RESULT_BAD_PARAMS 126 } MV_EDMA_QUEUE_RESULT; 127 128 typedef enum mvQueueCommandResult 129 { 130 MV_QUEUE_COMMAND_RESULT_OK = 0, 131 MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED, 132 MV_QUEUE_COMMAND_RESULT_FULL, 133 MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS, 134 MV_QUEUE_COMMAND_RESULT_BAD_PARAMS 135 } MV_QUEUE_COMMAND_RESULT; 136 137 typedef enum mvNonUdmaProtocol 138 { 139 MV_NON_UDMA_PROTOCOL_NON_DATA, 140 MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 141 MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT 142 } MV_NON_UDMA_PROTOCOL; 143 144 145 struct mvDmaRequestQueueEntry; 146 struct mvDmaResponseQueueEntry; 147 struct mvDmaCommandEntry; 148 149 struct mvSataAdapter; 150 struct mvStorageDevRegisters; 151 152 typedef MV_BOOLEAN (* HPTLIBAPI mvSataCommandCompletionCallBack_t)(struct mvSataAdapter *, 153 MV_U8, 154 MV_COMPLETION_TYPE, 155 MV_VOID_PTR, MV_U16, 156 MV_U32, 157 struct mvStorageDevRegisters FAR*); 158 159 typedef enum mvQueuedCommandType 160 { 161 MV_QUEUED_COMMAND_TYPE_UDMA, 162 MV_QUEUED_COMMAND_TYPE_NONE_UDMA 163 } MV_QUEUED_COMMAND_TYPE; 164 165 typedef struct mvUdmaCommandParams 166 { 167 MV_UDMA_TYPE readWrite; 168 MV_BOOLEAN isEXT; 169 MV_U32 lowLBAAddress; 170 MV_U16 highLBAAddress; 171 MV_U16 numOfSectors; 172 MV_U32 prdLowAddr; 173 MV_U32 prdHighAddr; 174 mvSataCommandCompletionCallBack_t callBack; 175 MV_VOID_PTR commandId; 176 } MV_UDMA_COMMAND_PARAMS; 177 178 typedef struct mvNoneUdmaCommandParams 179 { 180 MV_NON_UDMA_PROTOCOL protocolType; 181 MV_BOOLEAN isEXT; 182 MV_U16_PTR bufPtr; 183 MV_U32 count; 184 MV_U16 features; 185 MV_U16 sectorCount; 186 MV_U16 lbaLow; 187 MV_U16 lbaMid; 188 MV_U16 lbaHigh; 189 MV_U8 device; 190 MV_U8 command; 191 mvSataCommandCompletionCallBack_t callBack; 192 MV_VOID_PTR commandId; 193 } MV_NONE_UDMA_COMMAND_PARAMS; 194 195 typedef struct mvQueueCommandInfo 196 { 197 MV_QUEUED_COMMAND_TYPE type; 198 union 199 { 200 MV_UDMA_COMMAND_PARAMS udmaCommand; 201 MV_NONE_UDMA_COMMAND_PARAMS NoneUdmaCommand; 202 } commandParams; 203 } MV_QUEUE_COMMAND_INFO; 204 205 /* The following structure is for the Core Driver internal usage */ 206 typedef struct mvQueuedCommandEntry 207 { 208 MV_BOOLEAN isFreeEntry; 209 MV_U8 commandTag; 210 struct mvQueuedCommandEntry *next; 211 struct mvQueuedCommandEntry *prev; 212 MV_QUEUE_COMMAND_INFO commandInfo; 213 } MV_QUEUED_COMMAND_ENTRY; 214 215 /* The following structures are part of the Core Driver API */ 216 typedef struct mvSataChannel 217 { 218 /* Fields set by Intermediate Application Layer */ 219 MV_U8 channelNumber; 220 MV_BOOLEAN waitingForInterrupt; 221 MV_BOOLEAN lba48Address; 222 MV_BOOLEAN maxReadTransfer; 223 struct mvDmaRequestQueueEntry FAR *requestQueue; 224 struct mvDmaResponseQueueEntry FAR *responseQueue; 225 MV_U32 requestQueuePciHiAddress; 226 MV_U32 requestQueuePciLowAddress; 227 MV_U32 responseQueuePciHiAddress; 228 MV_U32 responseQueuePciLowAddress; 229 /* Fields set by CORE driver */ 230 struct mvSataAdapter *mvSataAdapter; 231 MV_OS_SEMAPHORE semaphore; 232 MV_U32 eDmaRegsOffset; 233 MV_U16 identifyDevice[MV_ATA_IDENTIFY_DEV_DATA_LENGTH]; 234 MV_BOOLEAN EdmaActive; 235 MV_EDMA_MODE queuedDMA; 236 MV_U8 outstandingCommands; 237 MV_BOOLEAN workAroundDone; 238 struct mvQueuedCommandEntry commandsQueue[CHANNEL_QUEUE_LENGTH]; 239 struct mvQueuedCommandEntry *commandsQueueHead; 240 struct mvQueuedCommandEntry *commandsQueueTail; 241 MV_BOOLEAN queueCommandsEnabled; 242 MV_U8 noneUdmaOutstandingCommands; 243 MV_U8 EdmaQueuedCommands; 244 MV_U32 freeIDsStack[MV_EDMA_QUEUE_LENGTH]; 245 MV_U32 freeIDsNum; 246 MV_U32 reqInPtr; 247 MV_U32 rspOutPtr; 248 } MV_SATA_CHANNEL; 249 250 typedef struct mvSataAdapter 251 { 252 /* Fields set by Intermediate Application Layer */ 253 MV_U32 adapterId; 254 MV_U8 pcbVersion; 255 MV_U8 pciConfigRevisionId; 256 MV_U16 pciConfigDeviceId; 257 MV_VOID_PTR IALData; 258 MV_BUS_ADDR_T adapterIoBaseAddress; 259 MV_U32 intCoalThre[MV_SATA_UNITS_NUM]; 260 MV_U32 intTimeThre[MV_SATA_UNITS_NUM]; 261 MV_BOOLEAN (* HPTLIBAPI mvSataEventNotify)(struct mvSataAdapter *, 262 MV_EVENT_TYPE, 263 MV_U32, MV_U32); 264 MV_SATA_CHANNEL *sataChannel[MV_SATA_CHANNELS_NUM]; 265 MV_U32 pciCommand; 266 MV_U32 pciSerrMask; 267 MV_U32 pciInterruptMask; 268 269 /* Fields set by CORE driver */ 270 MV_OS_SEMAPHORE semaphore; 271 MV_U32 mainMask; 272 MV_OS_SEMAPHORE interruptsMaskSem; 273 MV_BOOLEAN implementA0Workarounds; 274 MV_BOOLEAN implement50XXB0Workarounds; 275 MV_BOOLEAN implement50XXB1Workarounds; 276 MV_BOOLEAN implement50XXB2Workarounds; 277 MV_BOOLEAN implement60X1A0Workarounds; 278 MV_BOOLEAN implement60X1A1Workarounds; 279 MV_BOOLEAN implement60X1B0Workarounds; 280 MV_U8 sataAdapterGeneration; 281 MV_U8 failLEDMask; 282 MV_U8 signalAmps[MV_SATA_CHANNELS_NUM]; 283 MV_U8 pre[MV_SATA_CHANNELS_NUM]; 284 MV_BOOLEAN staggaredSpinup[MV_SATA_CHANNELS_NUM]; /* For 60x1 only */ 285 } MV_SATA_ADAPTER; 286 287 typedef struct mvSataAdapterStatus 288 { 289 /* Fields set by CORE driver */ 290 MV_BOOLEAN channelConnected[MV_SATA_CHANNELS_NUM]; 291 MV_U32 pciDLLStatusAndControlRegister; 292 MV_U32 pciCommandRegister; 293 MV_U32 pciModeRegister; 294 MV_U32 pciSERRMaskRegister; 295 MV_U32 intCoalThre[MV_SATA_UNITS_NUM]; 296 MV_U32 intTimeThre[MV_SATA_UNITS_NUM]; 297 MV_U32 R00StatusBridgePortRegister[MV_SATA_CHANNELS_NUM]; 298 }MV_SATA_ADAPTER_STATUS; 299 300 301 typedef struct mvSataChannelStatus 302 { 303 /* Fields set by CORE driver */ 304 MV_BOOLEAN isConnected; 305 MV_U8 modelNumber[MV_ATA_MODEL_NUMBER_LEN]; 306 MV_BOOLEAN DMAEnabled; 307 MV_EDMA_MODE queuedDMA; 308 MV_U8 outstandingCommands; 309 MV_U32 EdmaConfigurationRegister; 310 MV_U32 EdmaRequestQueueBaseAddressHighRegister; 311 MV_U32 EdmaRequestQueueInPointerRegister; 312 MV_U32 EdmaRequestQueueOutPointerRegister; 313 MV_U32 EdmaResponseQueueBaseAddressHighRegister; 314 MV_U32 EdmaResponseQueueInPointerRegister; 315 MV_U32 EdmaResponseQueueOutPointerRegister; 316 MV_U32 EdmaCommandRegister; 317 MV_U32 PHYModeRegister; 318 }MV_SATA_CHANNEL_STATUS; 319 320 /* this structure used by the IAL defines the PRD entries used by the EDMA HW */ 321 typedef struct mvSataEdmaPRDEntry 322 { 323 volatile MV_U32 lowBaseAddr; 324 volatile MV_U16 byteCount; 325 volatile MV_U16 flags; 326 volatile MV_U32 highBaseAddr; 327 volatile MV_U32 reserved; 328 }MV_SATA_EDMA_PRD_ENTRY; 329 330 /* API Functions */ 331 332 /* CORE driver Adapter Management */ 333 MV_BOOLEAN HPTLIBAPI mvSataInitAdapter(MV_SATA_ADAPTER *pAdapter); 334 335 MV_BOOLEAN HPTLIBAPI mvSataShutdownAdapter(MV_SATA_ADAPTER *pAdapter); 336 337 MV_BOOLEAN HPTLIBAPI mvSataGetAdapterStatus(MV_SATA_ADAPTER *pAdapter, 338 MV_SATA_ADAPTER_STATUS *pAdapterStatus); 339 340 MV_U32 HPTLIBAPI mvSataReadReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset); 341 342 MV_VOID HPTLIBAPI mvSataWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset, 343 MV_U32 regValue); 344 345 MV_VOID HPTLIBAPI mvEnableAutoFlush(MV_VOID); 346 MV_VOID HPTLIBAPI mvDisableAutoFlush(MV_VOID); 347 348 349 /* CORE driver SATA Channel Management */ 350 MV_BOOLEAN HPTLIBAPI mvSataConfigureChannel(MV_SATA_ADAPTER *pAdapter, 351 MV_U8 channelIndex); 352 353 MV_BOOLEAN HPTLIBAPI mvSataRemoveChannel(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); 354 355 MV_BOOLEAN HPTLIBAPI mvSataIsStorageDeviceConnected(MV_SATA_ADAPTER *pAdapter, 356 MV_U8 channelIndex); 357 358 MV_BOOLEAN HPTLIBAPI mvSataChannelHardReset(MV_SATA_ADAPTER *pAdapter, 359 MV_U8 channelIndex); 360 361 MV_BOOLEAN HPTLIBAPI mvSataConfigEdmaMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, 362 MV_EDMA_MODE eDmaMode, MV_U8 maxQueueDepth); 363 364 MV_BOOLEAN HPTLIBAPI mvSataEnableChannelDma(MV_SATA_ADAPTER *pAdapter, 365 MV_U8 channelIndex); 366 367 MV_BOOLEAN HPTLIBAPI mvSataDisableChannelDma(MV_SATA_ADAPTER *pAdapter, 368 MV_U8 channelIndex); 369 370 MV_BOOLEAN HPTLIBAPI mvSataFlushDmaQueue(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, 371 MV_FLUSH_TYPE flushType); 372 373 MV_U8 HPTLIBAPI mvSataNumOfDmaCommands(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); 374 375 MV_BOOLEAN HPTLIBAPI mvSataSetIntCoalParams (MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit, 376 MV_U32 intCoalThre, MV_U32 intTimeThre); 377 378 MV_BOOLEAN HPTLIBAPI mvSataSetChannelPhyParams(MV_SATA_ADAPTER *pAdapter, 379 MV_U8 channelIndex, 380 MV_U8 signalAmps, MV_U8 pre); 381 382 MV_BOOLEAN HPTLIBAPI mvSataChannelPhyShutdown(MV_SATA_ADAPTER *pAdapter, 383 MV_U8 channelIndex); 384 385 MV_BOOLEAN HPTLIBAPI mvSataChannelPhyPowerOn(MV_SATA_ADAPTER *pAdapter, 386 MV_U8 channelIndex); 387 388 MV_BOOLEAN HPTLIBAPI mvSataChannelSetEdmaLoopBackMode(MV_SATA_ADAPTER *pAdapter, 389 MV_U8 channelIndex, 390 MV_BOOLEAN loopBackOn); 391 392 MV_BOOLEAN HPTLIBAPI mvSataGetChannelStatus(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, 393 MV_SATA_CHANNEL_STATUS *pChannelStatus); 394 395 /* Execute UDMA ATA commands */ 396 MV_EDMA_QUEUE_RESULT HPTLIBAPI mvSataQueueUDmaCommand(MV_SATA_ADAPTER *pAdapter, 397 MV_U8 channelIndex, 398 MV_UDMA_TYPE readWrite, 399 MV_U32 lowLBAAddr, 400 MV_U16 highLBAAddr, 401 MV_U16 sectorCount, 402 MV_U32 prdLowAddr, 403 MV_U32 prdHighAddr, 404 mvSataCommandCompletionCallBack_t callBack, 405 MV_VOID_PTR commandId); 406 407 MV_QUEUE_COMMAND_RESULT HPTLIBAPI mvSataQueueCommand(MV_SATA_ADAPTER *pAdapter, 408 MV_U8 channelIndex, 409 MV_QUEUE_COMMAND_INFO FAR *pCommandParams); 410 411 /* Interrupt Service Routine */ 412 MV_BOOLEAN HPTLIBAPI mvSataInterruptServiceRoutine(MV_SATA_ADAPTER *pAdapter); 413 414 MV_BOOLEAN HPTLIBAPI mvSataMaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter); 415 416 MV_BOOLEAN HPTLIBAPI mvSataUnmaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter); 417 418 /* Command Completion and Event Notification (user implemented) */ 419 MV_BOOLEAN HPTLIBAPI mvSataEventNotify(MV_SATA_ADAPTER *, MV_EVENT_TYPE , 420 MV_U32, MV_U32); 421 422 /* 423 * Staggered spin-ip support and SATA interface speed control 424 * (relevant for 60x1 adapters) 425 */ 426 MV_BOOLEAN HPTLIBAPI mvSataEnableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter); 427 MV_BOOLEAN HPTLIBAPI mvSataDisableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter); 428 429 #endif 430