1718cf2ccSPedro F. Giffuni /*- 2*4d846d26SWarner Losh * SPDX-License-Identifier: BSD-2-Clause 3718cf2ccSPedro F. Giffuni * 4d2bd3ab9SScott Long * Copyright (c) 2004-2005 MARVELL SEMICONDUCTOR ISRAEL, LTD. 51713e81bSScott Long * All rights reserved. 61713e81bSScott Long * 71713e81bSScott Long * Redistribution and use in source and binary forms, with or without 81713e81bSScott Long * modification, are permitted provided that the following conditions 91713e81bSScott Long * are met: 101713e81bSScott Long * 1. Redistributions of source code must retain the above copyright 111713e81bSScott Long * notice, this list of conditions and the following disclaimer. 121713e81bSScott Long * 2. Redistributions in binary form must reproduce the above copyright 131713e81bSScott Long * notice, this list of conditions and the following disclaimer in the 141713e81bSScott Long * documentation and/or other materials provided with the distribution. 151713e81bSScott Long * 161713e81bSScott Long * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 171713e81bSScott Long * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 181713e81bSScott Long * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 191713e81bSScott Long * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 201713e81bSScott Long * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 211713e81bSScott Long * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 221713e81bSScott Long * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 231713e81bSScott Long * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 241713e81bSScott Long * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 251713e81bSScott Long * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 261713e81bSScott Long * SUCH DAMAGE. 271713e81bSScott Long */ 281713e81bSScott Long #ifndef __INCmvSatah 291713e81bSScott Long #define __INCmvSatah 301713e81bSScott Long 311713e81bSScott Long #ifndef SUPPORT_MV_SATA_GEN_1 321713e81bSScott Long #define SUPPORT_MV_SATA_GEN_1 1 331713e81bSScott Long #endif 341713e81bSScott Long 351713e81bSScott Long #ifndef SUPPORT_MV_SATA_GEN_2 361713e81bSScott Long #define SUPPORT_MV_SATA_GEN_2 0 371713e81bSScott Long #endif 381713e81bSScott Long 3964470755SXin LI #ifndef SUPPORT_MV_SATA_GEN_2E 4064470755SXin LI #define SUPPORT_MV_SATA_GEN_2E 0 4164470755SXin LI #endif 4264470755SXin LI 4364470755SXin LI #if (SUPPORT_MV_SATA_GEN_1 + SUPPORT_MV_SATA_GEN_2 + SUPPORT_MV_SATA_GEN_2E) > 1 4464470755SXin LI 451713e81bSScott Long #define MV_SATA_GEN_1(x) ((x)->sataAdapterGeneration==1) 4664470755SXin LI #define MV_SATA_GEN_2(x) ((x)->sataAdapterGeneration>=2) 4764470755SXin LI #define MV_SATA_GEN_2E(x) ((x)->sataAdapterGeneration==3) 4864470755SXin LI 491713e81bSScott Long #elif SUPPORT_MV_SATA_GEN_1==1 5064470755SXin LI 511713e81bSScott Long #define MV_SATA_GEN_1(x) 1 521713e81bSScott Long #define MV_SATA_GEN_2(x) 0 5364470755SXin LI #define MV_SATA_GEN_2E(x) 0 5464470755SXin LI 551713e81bSScott Long #elif SUPPORT_MV_SATA_GEN_2==1 5664470755SXin LI 571713e81bSScott Long #define MV_SATA_GEN_1(x) 0 581713e81bSScott Long #define MV_SATA_GEN_2(x) 1 5964470755SXin LI #define MV_SATA_GEN_2E(x) 0 6064470755SXin LI 6164470755SXin LI #elif SUPPORT_MV_SATA_GEN_2E==1 6264470755SXin LI 6364470755SXin LI #define MV_SATA_GEN_1(x) 0 6464470755SXin LI #define MV_SATA_GEN_2(x) 1 /* gen2E impiles gen2 */ 6564470755SXin LI #define MV_SATA_GEN_2E(x) 1 6664470755SXin LI 671713e81bSScott Long #else 681713e81bSScott Long #error "Which IC do you support?" 691713e81bSScott Long #endif 701713e81bSScott Long 711713e81bSScott Long /* Definitions */ 721713e81bSScott Long /* MV88SX50XX specific defines */ 731713e81bSScott Long #define MV_SATA_VENDOR_ID 0x11AB 741713e81bSScott Long #define MV_SATA_DEVICE_ID_5080 0x5080 751713e81bSScott Long #define MV_SATA_DEVICE_ID_5081 0x5081 761713e81bSScott Long #define MV_SATA_DEVICE_ID_6080 0x6080 771713e81bSScott Long #define MV_SATA_DEVICE_ID_6081 0x6081 7864470755SXin LI 7964470755SXin LI #if defined(RR2310) || defined(RR1740) || defined(RR2210) || defined (RR2522) 8064470755SXin LI #define MV_SATA_CHANNELS_NUM 4 8164470755SXin LI #define MV_SATA_UNITS_NUM 1 8264470755SXin LI #else 831713e81bSScott Long #define MV_SATA_CHANNELS_NUM 8 841713e81bSScott Long #define MV_SATA_UNITS_NUM 2 8564470755SXin LI #endif 8664470755SXin LI 871713e81bSScott Long #define MV_SATA_PCI_BAR0_SPACE_SIZE (1<<18) /* 256 Kb*/ 881713e81bSScott Long 891713e81bSScott Long #define CHANNEL_QUEUE_LENGTH 32 901713e81bSScott Long #define CHANNEL_QUEUE_MASK 0x1F 911713e81bSScott Long 921713e81bSScott Long #define MV_EDMA_QUEUE_LENGTH 32 /* Up to 32 outstanding */ 931713e81bSScott Long /* commands per SATA channel*/ 941713e81bSScott Long #define MV_EDMA_QUEUE_MASK 0x1F 951713e81bSScott Long #define MV_EDMA_REQUEST_QUEUE_SIZE 1024 /* 32*32 = 1KBytes */ 961713e81bSScott Long #define MV_EDMA_RESPONSE_QUEUE_SIZE 256 /* 32*8 = 256 Bytes */ 971713e81bSScott Long 981713e81bSScott Long #define MV_EDMA_REQUEST_ENTRY_SIZE 32 991713e81bSScott Long #define MV_EDMA_RESPONSE_ENTRY_SIZE 8 1001713e81bSScott Long 1011713e81bSScott Long #define MV_EDMA_PRD_ENTRY_SIZE 16 /* 16Bytes*/ 1021713e81bSScott Long #define MV_EDMA_PRD_NO_SNOOP_FLAG 0x00000001 /* MV_BIT0 */ 1031713e81bSScott Long #define MV_EDMA_PRD_EOT_FLAG 0x00008000 /* MV_BIT15 */ 1041713e81bSScott Long 1051713e81bSScott Long #define MV_ATA_IDENTIFY_DEV_DATA_LENGTH 256 /* number of words(2 byte)*/ 1061713e81bSScott Long #define MV_ATA_MODEL_NUMBER_LEN 40 1071713e81bSScott Long #define ATA_SECTOR_SIZE 512 1081713e81bSScott Long /* Log messages level defines */ 1091713e81bSScott Long #define MV_DEBUG 0x1 1101713e81bSScott Long #define MV_DEBUG_INIT 0x2 1111713e81bSScott Long #define MV_DEBUG_INTERRUPTS 0x4 1121713e81bSScott Long #define MV_DEBUG_SATA_LINK 0x8 1131713e81bSScott Long #define MV_DEBUG_UDMA_COMMAND 0x10 1141713e81bSScott Long #define MV_DEBUG_NON_UDMA_COMMAND 0x20 1151713e81bSScott Long #define MV_DEBUG_ERROR 0x40 1161713e81bSScott Long 1171713e81bSScott Long 1181713e81bSScott Long /* Typedefs */ 1191713e81bSScott Long typedef enum mvUdmaType 1201713e81bSScott Long { 1211713e81bSScott Long MV_UDMA_TYPE_READ, MV_UDMA_TYPE_WRITE 1221713e81bSScott Long } MV_UDMA_TYPE; 1231713e81bSScott Long 1241713e81bSScott Long typedef enum mvFlushType 1251713e81bSScott Long { 1261713e81bSScott Long MV_FLUSH_TYPE_CALLBACK, MV_FLUSH_TYPE_NONE 1271713e81bSScott Long } MV_FLUSH_TYPE; 1281713e81bSScott Long 1291713e81bSScott Long typedef enum mvCompletionType 1301713e81bSScott Long { 1311713e81bSScott Long MV_COMPLETION_TYPE_NORMAL, MV_COMPLETION_TYPE_ERROR, 1321713e81bSScott Long MV_COMPLETION_TYPE_ABORT 1331713e81bSScott Long } MV_COMPLETION_TYPE; 1341713e81bSScott Long 1351713e81bSScott Long typedef enum mvEventType 1361713e81bSScott Long { 1371713e81bSScott Long MV_EVENT_TYPE_ADAPTER_ERROR, MV_EVENT_TYPE_SATA_CABLE 1381713e81bSScott Long } MV_EVENT_TYPE; 1391713e81bSScott Long 1401713e81bSScott Long typedef enum mvEdmaMode 1411713e81bSScott Long { 1421713e81bSScott Long MV_EDMA_MODE_QUEUED, 1431713e81bSScott Long MV_EDMA_MODE_NOT_QUEUED, 1441713e81bSScott Long MV_EDMA_MODE_NATIVE_QUEUING 1451713e81bSScott Long } MV_EDMA_MODE; 1461713e81bSScott Long 1471713e81bSScott Long typedef enum mvEdmaQueueResult 1481713e81bSScott Long { 1491713e81bSScott Long MV_EDMA_QUEUE_RESULT_OK = 0, 1501713e81bSScott Long MV_EDMA_QUEUE_RESULT_EDMA_DISABLED, 1511713e81bSScott Long MV_EDMA_QUEUE_RESULT_FULL, 1521713e81bSScott Long MV_EDMA_QUEUE_RESULT_BAD_LBA_ADDRESS, 1531713e81bSScott Long MV_EDMA_QUEUE_RESULT_BAD_PARAMS 1541713e81bSScott Long } MV_EDMA_QUEUE_RESULT; 1551713e81bSScott Long 1561713e81bSScott Long typedef enum mvQueueCommandResult 1571713e81bSScott Long { 1581713e81bSScott Long MV_QUEUE_COMMAND_RESULT_OK = 0, 1591713e81bSScott Long MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED, 1601713e81bSScott Long MV_QUEUE_COMMAND_RESULT_FULL, 1611713e81bSScott Long MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS, 1621713e81bSScott Long MV_QUEUE_COMMAND_RESULT_BAD_PARAMS 1631713e81bSScott Long } MV_QUEUE_COMMAND_RESULT; 1641713e81bSScott Long 1651713e81bSScott Long typedef enum mvNonUdmaProtocol 1661713e81bSScott Long { 1671713e81bSScott Long MV_NON_UDMA_PROTOCOL_NON_DATA, 1681713e81bSScott Long MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1691713e81bSScott Long MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT 1701713e81bSScott Long } MV_NON_UDMA_PROTOCOL; 1711713e81bSScott Long 1721713e81bSScott Long 1731713e81bSScott Long struct mvDmaRequestQueueEntry; 1741713e81bSScott Long struct mvDmaResponseQueueEntry; 1751713e81bSScott Long struct mvDmaCommandEntry; 1761713e81bSScott Long 1771713e81bSScott Long struct mvSataAdapter; 1781713e81bSScott Long struct mvStorageDevRegisters; 1791713e81bSScott Long 1801713e81bSScott Long typedef MV_BOOLEAN (* HPTLIBAPI mvSataCommandCompletionCallBack_t)(struct mvSataAdapter *, 1811713e81bSScott Long MV_U8, 1821713e81bSScott Long MV_COMPLETION_TYPE, 1831713e81bSScott Long MV_VOID_PTR, MV_U16, 1841713e81bSScott Long MV_U32, 18564470755SXin LI struct mvStorageDevRegisters SS_SEG*); 1861713e81bSScott Long 1871713e81bSScott Long typedef enum mvQueuedCommandType 1881713e81bSScott Long { 1891713e81bSScott Long MV_QUEUED_COMMAND_TYPE_UDMA, 1901713e81bSScott Long MV_QUEUED_COMMAND_TYPE_NONE_UDMA 1911713e81bSScott Long } MV_QUEUED_COMMAND_TYPE; 1921713e81bSScott Long 1931713e81bSScott Long typedef struct mvUdmaCommandParams 1941713e81bSScott Long { 1951713e81bSScott Long MV_UDMA_TYPE readWrite; 1961713e81bSScott Long MV_BOOLEAN isEXT; 1971713e81bSScott Long MV_U32 lowLBAAddress; 1981713e81bSScott Long MV_U16 highLBAAddress; 1991713e81bSScott Long MV_U16 numOfSectors; 2001713e81bSScott Long MV_U32 prdLowAddr; 2011713e81bSScott Long MV_U32 prdHighAddr; 2021713e81bSScott Long mvSataCommandCompletionCallBack_t callBack; 2031713e81bSScott Long MV_VOID_PTR commandId; 2041713e81bSScott Long } MV_UDMA_COMMAND_PARAMS; 2051713e81bSScott Long 2061713e81bSScott Long typedef struct mvNoneUdmaCommandParams 2071713e81bSScott Long { 2081713e81bSScott Long MV_NON_UDMA_PROTOCOL protocolType; 2091713e81bSScott Long MV_BOOLEAN isEXT; 2101713e81bSScott Long MV_U16_PTR bufPtr; 2111713e81bSScott Long MV_U32 count; 2121713e81bSScott Long MV_U16 features; 2131713e81bSScott Long MV_U16 sectorCount; 2141713e81bSScott Long MV_U16 lbaLow; 2151713e81bSScott Long MV_U16 lbaMid; 2161713e81bSScott Long MV_U16 lbaHigh; 2171713e81bSScott Long MV_U8 device; 2181713e81bSScott Long MV_U8 command; 2191713e81bSScott Long mvSataCommandCompletionCallBack_t callBack; 2201713e81bSScott Long MV_VOID_PTR commandId; 2211713e81bSScott Long } MV_NONE_UDMA_COMMAND_PARAMS; 2221713e81bSScott Long 2231713e81bSScott Long typedef struct mvQueueCommandInfo 2241713e81bSScott Long { 2251713e81bSScott Long MV_QUEUED_COMMAND_TYPE type; 2261713e81bSScott Long union 2271713e81bSScott Long { 2281713e81bSScott Long MV_UDMA_COMMAND_PARAMS udmaCommand; 2291713e81bSScott Long MV_NONE_UDMA_COMMAND_PARAMS NoneUdmaCommand; 2301713e81bSScott Long } commandParams; 2311713e81bSScott Long } MV_QUEUE_COMMAND_INFO; 2321713e81bSScott Long 2331713e81bSScott Long /* The following structure is for the Core Driver internal usage */ 2341713e81bSScott Long typedef struct mvQueuedCommandEntry 2351713e81bSScott Long { 2361713e81bSScott Long MV_BOOLEAN isFreeEntry; 2371713e81bSScott Long MV_U8 commandTag; 2381713e81bSScott Long struct mvQueuedCommandEntry *next; 2391713e81bSScott Long struct mvQueuedCommandEntry *prev; 2401713e81bSScott Long MV_QUEUE_COMMAND_INFO commandInfo; 2411713e81bSScott Long } MV_QUEUED_COMMAND_ENTRY; 2421713e81bSScott Long 2431713e81bSScott Long /* The following structures are part of the Core Driver API */ 2441713e81bSScott Long typedef struct mvSataChannel 2451713e81bSScott Long { 2461713e81bSScott Long /* Fields set by Intermediate Application Layer */ 2471713e81bSScott Long MV_U8 channelNumber; 2481713e81bSScott Long MV_BOOLEAN waitingForInterrupt; 2491713e81bSScott Long MV_BOOLEAN lba48Address; 2501713e81bSScott Long MV_BOOLEAN maxReadTransfer; 25164470755SXin LI struct mvDmaRequestQueueEntry SS_SEG *requestQueue; 25264470755SXin LI struct mvDmaResponseQueueEntry SS_SEG *responseQueue; 2531713e81bSScott Long MV_U32 requestQueuePciHiAddress; 2541713e81bSScott Long MV_U32 requestQueuePciLowAddress; 2551713e81bSScott Long MV_U32 responseQueuePciHiAddress; 2561713e81bSScott Long MV_U32 responseQueuePciLowAddress; 2571713e81bSScott Long /* Fields set by CORE driver */ 2581713e81bSScott Long struct mvSataAdapter *mvSataAdapter; 2591713e81bSScott Long MV_OS_SEMAPHORE semaphore; 2601713e81bSScott Long MV_U32 eDmaRegsOffset; 2611713e81bSScott Long MV_U16 identifyDevice[MV_ATA_IDENTIFY_DEV_DATA_LENGTH]; 2621713e81bSScott Long MV_BOOLEAN EdmaActive; 2631713e81bSScott Long MV_EDMA_MODE queuedDMA; 2641713e81bSScott Long MV_U8 outstandingCommands; 2651713e81bSScott Long MV_BOOLEAN workAroundDone; 2661713e81bSScott Long struct mvQueuedCommandEntry commandsQueue[CHANNEL_QUEUE_LENGTH]; 2671713e81bSScott Long struct mvQueuedCommandEntry *commandsQueueHead; 2681713e81bSScott Long struct mvQueuedCommandEntry *commandsQueueTail; 2691713e81bSScott Long MV_BOOLEAN queueCommandsEnabled; 2701713e81bSScott Long MV_U8 noneUdmaOutstandingCommands; 2711713e81bSScott Long MV_U8 EdmaQueuedCommands; 27264470755SXin LI MV_U32 freeIDsStack[CHANNEL_QUEUE_LENGTH]; 2731713e81bSScott Long MV_U32 freeIDsNum; 2741713e81bSScott Long MV_U32 reqInPtr; 2751713e81bSScott Long MV_U32 rspOutPtr; 2761713e81bSScott Long } MV_SATA_CHANNEL; 2771713e81bSScott Long 2781713e81bSScott Long typedef struct mvSataAdapter 2791713e81bSScott Long { 2801713e81bSScott Long /* Fields set by Intermediate Application Layer */ 2811713e81bSScott Long MV_U32 adapterId; 2821713e81bSScott Long MV_U8 pcbVersion; 2831713e81bSScott Long MV_U8 pciConfigRevisionId; 2841713e81bSScott Long MV_U16 pciConfigDeviceId; 2851713e81bSScott Long MV_VOID_PTR IALData; 2861713e81bSScott Long MV_BUS_ADDR_T adapterIoBaseAddress; 2871713e81bSScott Long MV_U32 intCoalThre[MV_SATA_UNITS_NUM]; 2881713e81bSScott Long MV_U32 intTimeThre[MV_SATA_UNITS_NUM]; 2891713e81bSScott Long MV_BOOLEAN (* HPTLIBAPI mvSataEventNotify)(struct mvSataAdapter *, 2901713e81bSScott Long MV_EVENT_TYPE, 2911713e81bSScott Long MV_U32, MV_U32); 2921713e81bSScott Long MV_SATA_CHANNEL *sataChannel[MV_SATA_CHANNELS_NUM]; 2931713e81bSScott Long MV_U32 pciCommand; 2941713e81bSScott Long MV_U32 pciSerrMask; 2951713e81bSScott Long MV_U32 pciInterruptMask; 2961713e81bSScott Long 2971713e81bSScott Long /* Fields set by CORE driver */ 2981713e81bSScott Long MV_OS_SEMAPHORE semaphore; 2991713e81bSScott Long MV_U32 mainMask; 3001713e81bSScott Long MV_OS_SEMAPHORE interruptsMaskSem; 3011713e81bSScott Long MV_BOOLEAN implementA0Workarounds; 3021713e81bSScott Long MV_BOOLEAN implement50XXB0Workarounds; 3031713e81bSScott Long MV_BOOLEAN implement50XXB1Workarounds; 3041713e81bSScott Long MV_BOOLEAN implement50XXB2Workarounds; 3051713e81bSScott Long MV_BOOLEAN implement60X1A0Workarounds; 3061713e81bSScott Long MV_BOOLEAN implement60X1A1Workarounds; 3071713e81bSScott Long MV_BOOLEAN implement60X1B0Workarounds; 30864470755SXin LI MV_BOOLEAN implement7042A0Workarounds; 30964470755SXin LI MV_BOOLEAN implement7042A1Workarounds; 3101713e81bSScott Long MV_U8 sataAdapterGeneration; 31164470755SXin LI MV_BOOLEAN isPEX; 3121713e81bSScott Long MV_U8 failLEDMask; 3131713e81bSScott Long MV_U8 signalAmps[MV_SATA_CHANNELS_NUM]; 3141713e81bSScott Long MV_U8 pre[MV_SATA_CHANNELS_NUM]; 3151713e81bSScott Long MV_BOOLEAN staggaredSpinup[MV_SATA_CHANNELS_NUM]; /* For 60x1 only */ 3161713e81bSScott Long } MV_SATA_ADAPTER; 3171713e81bSScott Long 3181713e81bSScott Long typedef struct mvSataAdapterStatus 3191713e81bSScott Long { 3201713e81bSScott Long /* Fields set by CORE driver */ 3211713e81bSScott Long MV_BOOLEAN channelConnected[MV_SATA_CHANNELS_NUM]; 3221713e81bSScott Long MV_U32 pciDLLStatusAndControlRegister; 3231713e81bSScott Long MV_U32 pciCommandRegister; 3241713e81bSScott Long MV_U32 pciModeRegister; 3251713e81bSScott Long MV_U32 pciSERRMaskRegister; 3261713e81bSScott Long MV_U32 intCoalThre[MV_SATA_UNITS_NUM]; 3271713e81bSScott Long MV_U32 intTimeThre[MV_SATA_UNITS_NUM]; 3281713e81bSScott Long MV_U32 R00StatusBridgePortRegister[MV_SATA_CHANNELS_NUM]; 3291713e81bSScott Long }MV_SATA_ADAPTER_STATUS; 3301713e81bSScott Long 3311713e81bSScott Long 3321713e81bSScott Long typedef struct mvSataChannelStatus 3331713e81bSScott Long { 3341713e81bSScott Long /* Fields set by CORE driver */ 3351713e81bSScott Long MV_BOOLEAN isConnected; 3361713e81bSScott Long MV_U8 modelNumber[MV_ATA_MODEL_NUMBER_LEN]; 3371713e81bSScott Long MV_BOOLEAN DMAEnabled; 3381713e81bSScott Long MV_EDMA_MODE queuedDMA; 3391713e81bSScott Long MV_U8 outstandingCommands; 3401713e81bSScott Long MV_U32 EdmaConfigurationRegister; 3411713e81bSScott Long MV_U32 EdmaRequestQueueBaseAddressHighRegister; 3421713e81bSScott Long MV_U32 EdmaRequestQueueInPointerRegister; 3431713e81bSScott Long MV_U32 EdmaRequestQueueOutPointerRegister; 3441713e81bSScott Long MV_U32 EdmaResponseQueueBaseAddressHighRegister; 3451713e81bSScott Long MV_U32 EdmaResponseQueueInPointerRegister; 3461713e81bSScott Long MV_U32 EdmaResponseQueueOutPointerRegister; 3471713e81bSScott Long MV_U32 EdmaCommandRegister; 3481713e81bSScott Long MV_U32 PHYModeRegister; 3491713e81bSScott Long }MV_SATA_CHANNEL_STATUS; 3501713e81bSScott Long 3511713e81bSScott Long /* this structure used by the IAL defines the PRD entries used by the EDMA HW */ 3521713e81bSScott Long typedef struct mvSataEdmaPRDEntry 3531713e81bSScott Long { 3541713e81bSScott Long volatile MV_U32 lowBaseAddr; 3551713e81bSScott Long volatile MV_U16 byteCount; 3561713e81bSScott Long volatile MV_U16 flags; 3571713e81bSScott Long volatile MV_U32 highBaseAddr; 3581713e81bSScott Long volatile MV_U32 reserved; 3591713e81bSScott Long }MV_SATA_EDMA_PRD_ENTRY; 3601713e81bSScott Long 3611713e81bSScott Long /* API Functions */ 3621713e81bSScott Long 3631713e81bSScott Long /* CORE driver Adapter Management */ 3641713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataInitAdapter(MV_SATA_ADAPTER *pAdapter); 3651713e81bSScott Long 3661713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataShutdownAdapter(MV_SATA_ADAPTER *pAdapter); 3671713e81bSScott Long 3681713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataGetAdapterStatus(MV_SATA_ADAPTER *pAdapter, 3691713e81bSScott Long MV_SATA_ADAPTER_STATUS *pAdapterStatus); 3701713e81bSScott Long 3711713e81bSScott Long MV_U32 HPTLIBAPI mvSataReadReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset); 3721713e81bSScott Long 3731713e81bSScott Long MV_VOID HPTLIBAPI mvSataWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset, 3741713e81bSScott Long MV_U32 regValue); 3751713e81bSScott Long 3761713e81bSScott Long MV_VOID HPTLIBAPI mvEnableAutoFlush(MV_VOID); 3771713e81bSScott Long MV_VOID HPTLIBAPI mvDisableAutoFlush(MV_VOID); 3781713e81bSScott Long 3791713e81bSScott Long 3801713e81bSScott Long /* CORE driver SATA Channel Management */ 3811713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataConfigureChannel(MV_SATA_ADAPTER *pAdapter, 3821713e81bSScott Long MV_U8 channelIndex); 3831713e81bSScott Long 3841713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataRemoveChannel(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); 3851713e81bSScott Long 3861713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataIsStorageDeviceConnected(MV_SATA_ADAPTER *pAdapter, 3871713e81bSScott Long MV_U8 channelIndex); 3881713e81bSScott Long 3891713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataChannelHardReset(MV_SATA_ADAPTER *pAdapter, 3901713e81bSScott Long MV_U8 channelIndex); 3911713e81bSScott Long 3921713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataConfigEdmaMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, 3931713e81bSScott Long MV_EDMA_MODE eDmaMode, MV_U8 maxQueueDepth); 3941713e81bSScott Long 3951713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataEnableChannelDma(MV_SATA_ADAPTER *pAdapter, 3961713e81bSScott Long MV_U8 channelIndex); 3971713e81bSScott Long 3981713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataDisableChannelDma(MV_SATA_ADAPTER *pAdapter, 3991713e81bSScott Long MV_U8 channelIndex); 4001713e81bSScott Long 4011713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataFlushDmaQueue(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, 4021713e81bSScott Long MV_FLUSH_TYPE flushType); 4031713e81bSScott Long 4041713e81bSScott Long MV_U8 HPTLIBAPI mvSataNumOfDmaCommands(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex); 4051713e81bSScott Long 4061713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataSetIntCoalParams (MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit, 4071713e81bSScott Long MV_U32 intCoalThre, MV_U32 intTimeThre); 4081713e81bSScott Long 4091713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataSetChannelPhyParams(MV_SATA_ADAPTER *pAdapter, 4101713e81bSScott Long MV_U8 channelIndex, 4111713e81bSScott Long MV_U8 signalAmps, MV_U8 pre); 4121713e81bSScott Long 4131713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataChannelPhyShutdown(MV_SATA_ADAPTER *pAdapter, 4141713e81bSScott Long MV_U8 channelIndex); 4151713e81bSScott Long 4161713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataChannelPhyPowerOn(MV_SATA_ADAPTER *pAdapter, 4171713e81bSScott Long MV_U8 channelIndex); 4181713e81bSScott Long 4191713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataChannelSetEdmaLoopBackMode(MV_SATA_ADAPTER *pAdapter, 4201713e81bSScott Long MV_U8 channelIndex, 4211713e81bSScott Long MV_BOOLEAN loopBackOn); 4221713e81bSScott Long 4231713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataGetChannelStatus(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex, 4241713e81bSScott Long MV_SATA_CHANNEL_STATUS *pChannelStatus); 4251713e81bSScott Long 4261713e81bSScott Long MV_QUEUE_COMMAND_RESULT HPTLIBAPI mvSataQueueCommand(MV_SATA_ADAPTER *pAdapter, 4271713e81bSScott Long MV_U8 channelIndex, 42864470755SXin LI MV_QUEUE_COMMAND_INFO SS_SEG *pCommandParams); 4291713e81bSScott Long 4301713e81bSScott Long /* Interrupt Service Routine */ 4311713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataInterruptServiceRoutine(MV_SATA_ADAPTER *pAdapter); 4321713e81bSScott Long 4331713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataMaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter); 4341713e81bSScott Long 4351713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataUnmaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter); 4361713e81bSScott Long 4371713e81bSScott Long /* Command Completion and Event Notification (user implemented) */ 4381713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataEventNotify(MV_SATA_ADAPTER *, MV_EVENT_TYPE , 4391713e81bSScott Long MV_U32, MV_U32); 4401713e81bSScott Long 4411713e81bSScott Long /* 4421713e81bSScott Long * Staggered spin-ip support and SATA interface speed control 4431713e81bSScott Long * (relevant for 60x1 adapters) 4441713e81bSScott Long */ 4451713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataEnableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter); 4461713e81bSScott Long MV_BOOLEAN HPTLIBAPI mvSataDisableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter); 4471713e81bSScott Long 4481713e81bSScott Long #endif 449