1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/malloc.h> 35 #include <sys/resource.h> 36 #include <sys/time.h> 37 #include <sys/callout.h> 38 #include <sys/signalvar.h> 39 #include <sys/eventhandler.h> 40 #include <sys/proc.h> 41 #include <sys/kthread.h> 42 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #include <sys/sx.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #ifndef __KERNEL__ 51 #define __KERNEL__ 52 #endif 53 54 #include <dev/hptmv/global.h> 55 #include <dev/hptmv/hptintf.h> 56 #include <dev/hptmv/osbsd.h> 57 #include <dev/hptmv/access601.h> 58 59 60 #ifdef DEBUG 61 #ifdef DEBUG_LEVEL 62 int hpt_dbg_level = DEBUG_LEVEL; 63 #else 64 int hpt_dbg_level = 0; 65 #endif 66 #endif 67 68 #define MV_ERROR printf 69 70 /* 71 * CAM SIM entry points 72 */ 73 static int hpt_probe (device_t dev); 74 static void launch_worker_thread(void); 75 static int hpt_attach(device_t dev); 76 static int hpt_detach(device_t dev); 77 static int hpt_shutdown(device_t dev); 78 static void hpt_poll(struct cam_sim *sim); 79 static void hpt_intr(void *arg); 80 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 81 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 82 83 static device_method_t driver_methods[] = { 84 /* Device interface */ 85 DEVMETHOD(device_probe, hpt_probe), 86 DEVMETHOD(device_attach, hpt_attach), 87 DEVMETHOD(device_detach, hpt_detach), 88 89 DEVMETHOD(device_shutdown, hpt_shutdown), 90 DEVMETHOD_END 91 }; 92 93 static driver_t hpt_pci_driver = { 94 __str(PROC_DIR_NAME), 95 driver_methods, 96 sizeof(IAL_ADAPTER_T) 97 }; 98 99 #define __DRIVER_MODULE(p1, p2, p3, p4, p5) DRIVER_MODULE(p1, p2, p3, p4, p5) 100 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, 0, 0); 101 MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1); 102 103 #define ccb_ccb_ptr spriv_ptr0 104 #define ccb_adapter ccb_h.spriv_ptr1 105 106 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 107 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 108 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 109 static void ccb_done(union ccb *ccb); 110 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 111 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 112 static void hpt_intr_locked(IAL_ADAPTER_T *pAdapter); 113 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 114 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 115 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 116 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 117 static int fResetActiveCommands(PVBus _vbus_p); 118 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 119 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 120 static void hptmv_handle_event_disconnect(void *data); 121 static void hptmv_handle_event_connect(void *data); 122 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 123 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 124 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 125 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 126 int logical); 127 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 128 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 129 MV_U16 responseFlags, MV_U32 timeStamp, 130 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 131 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 132 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 133 134 #define ccb_ccb_ptr spriv_ptr0 135 #define ccb_adapter ccb_h.spriv_ptr1 136 137 static struct sx hptmv_list_lock; 138 SX_SYSINIT(hptmv_list_lock, &hptmv_list_lock, "hptmv list"); 139 IAL_ADAPTER_T *gIal_Adapter = NULL; 140 IAL_ADAPTER_T *pCurAdapter = NULL; 141 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 142 143 typedef struct st_HPT_DPC { 144 IAL_ADAPTER_T *pAdapter; 145 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 146 void *arg; 147 UCHAR flags; 148 } ST_HPT_DPC; 149 150 #define MAX_DPC 16 151 UCHAR DPC_Request_Nums = 0; 152 static ST_HPT_DPC DpcQueue[MAX_DPC]; 153 static int DpcQueue_First=0; 154 static int DpcQueue_Last = 0; 155 static struct mtx DpcQueue_Lock; 156 MTX_SYSINIT(hpmtv_dpc_lock, &DpcQueue_Lock, "hptmv dpc", MTX_DEF); 157 158 char DRIVER_VERSION[] = "v1.16"; 159 160 /******************************************************************************* 161 * Name: hptmv_free_channel 162 * 163 * Description: free allocated queues for the given channel 164 * 165 * Parameters: pMvSataAdapter - pointer to the RR18xx controller this 166 * channel connected to. 167 * channelNum - channel number. 168 * 169 ******************************************************************************/ 170 static void 171 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 172 { 173 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 174 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 175 } 176 177 static void failDevice(PVDevice pVDev) 178 { 179 PVBus _vbus_p = pVDev->pVBus; 180 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 181 182 pVDev->u.disk.df_on_line = 0; 183 pVDev->vf_online = 0; 184 if (pVDev->pfnDeviceFailed) 185 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 186 187 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 188 189 #ifndef FOR_DEMO 190 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 191 pAdapter->beeping = 1; 192 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 193 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 194 } 195 #endif 196 } 197 198 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 199 200 static void 201 handleEdmaError(_VBUS_ARG PCommand pCmd) 202 { 203 PDevice pDevice = &pCmd->pVDevice->u.disk; 204 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 205 206 if (!pDevice->df_on_line) { 207 KdPrint(("Device is offline")); 208 pCmd->Result = RETURN_BAD_DEVICE; 209 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 210 return; 211 } 212 213 if (pCmd->RetryCount++>5) { 214 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 215 failed: 216 failDevice(pCmd->pVDevice); 217 pCmd->Result = RETURN_IDE_ERROR; 218 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 219 return; 220 } 221 222 /* reset the channel and retry the command */ 223 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 224 goto failed; 225 226 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 227 228 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 229 fDeviceSendCommand(_VBUS_P pCmd); 230 } 231 232 /**************************************************************** 233 * Name: hptmv_init_channel 234 * 235 * Description: allocate request and response queues for the EDMA of the 236 * given channel and sets other fields. 237 * 238 * Parameters: 239 * pAdapter - pointer to the emulated adapter data structure 240 * channelNum - channel number. 241 * Return: 0 on success, otherwise on failure 242 ****************************************************************/ 243 static int 244 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 245 { 246 MV_SATA_CHANNEL *pMvSataChannel; 247 dma_addr_t req_dma_addr; 248 dma_addr_t rsp_dma_addr; 249 250 if (channelNum >= MV_SATA_CHANNELS_NUM) 251 { 252 MV_ERROR("RR18xx[%d]: Bad channelNum=%d", 253 pAdapter->mvSataAdapter.adapterId, channelNum); 254 return -1; 255 } 256 257 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 258 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 259 pMvSataChannel->channelNumber = channelNum; 260 pMvSataChannel->lba48Address = MV_FALSE; 261 pMvSataChannel->maxReadTransfer = MV_FALSE; 262 263 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 264 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 265 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 266 267 268 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 269 270 /* check the 1K alignment of the request queue*/ 271 if (req_dma_addr & 0x3ff) 272 { 273 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned," 274 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 275 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 276 return -1; 277 } 278 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 279 pMvSataChannel->requestQueuePciHiAddress = 0; 280 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p", 281 pAdapter->mvSataAdapter.adapterId, channelNum, 282 pMvSataChannel->requestQueue)); 283 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 284 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 285 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 286 287 /* check the 256 alignment of the response queue*/ 288 if (rsp_dma_addr & 0xff) 289 { 290 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte " 291 "aligned, dma_addr=%llx\n", 292 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 293 return -1; 294 } 295 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 296 pMvSataChannel->responseQueuePciHiAddress = 0; 297 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p", 298 pAdapter->mvSataAdapter.adapterId, channelNum, 299 pMvSataChannel->responseQueue)); 300 301 pAdapter->mvChannel[channelNum].online = MV_TRUE; 302 return 0; 303 } 304 305 /****************************************************************************** 306 * Name: hptmv_parse_identify_results 307 * 308 * Description: this functions parses the identify command results, checks 309 * that the connected deives can be accesed by RR18xx EDMA, 310 * and updates the channel structure accordingly. 311 * 312 * Parameters: pMvSataChannel, pointer to the channel data structure. 313 * 314 * Returns: =0 ->success, < 0 ->failure. 315 * 316 ******************************************************************************/ 317 static int 318 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 319 { 320 MV_U16 *iden = pMvSataChannel->identifyDevice; 321 322 /*LBA addressing*/ 323 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 324 { 325 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 326 return -1; 327 } 328 else 329 { 330 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 331 } 332 /*DMA support*/ 333 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 334 { 335 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 336 return -1; 337 } 338 else 339 { 340 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 341 } 342 /* PIO */ 343 if ((iden[IDEN_VALID] & 2) == 0) 344 { 345 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 346 return -1; 347 } 348 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 349 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 350 351 /*UDMA*/ 352 if ((iden[IDEN_VALID] & 4) == 0) 353 { 354 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 355 return -1; 356 } 357 358 /* 48 bit address */ 359 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 360 { 361 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 362 pMvSataChannel->lba48Address = MV_TRUE; 363 } 364 else 365 { 366 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 367 pMvSataChannel->lba48Address = MV_FALSE; 368 } 369 return 0; 370 } 371 372 static void 373 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 374 { 375 PVDevice pVDev = &pAdapter->VDevices[channel]; 376 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 377 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 378 379 pMvSataChannel->outstandingCommands = 0; 380 381 pVDev->u.disk.mv = pMvSataChannel; 382 pVDev->u.disk.df_on_line = 1; 383 pVDev->u.disk.pVBus = &pAdapter->VBus; 384 pVDev->pVBus = &pAdapter->VBus; 385 386 #ifdef SUPPORT_48BIT_LBA 387 if (pMvSataChannel->lba48Address == MV_TRUE) 388 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 389 else 390 #endif 391 if(IdentifyData[53] & 1) { 392 pVDev->u.disk.dDeRealCapacity = 393 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 394 (IdentifyData[61]<<16 | IdentifyData[60]) : 395 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 396 } else 397 pVDev->u.disk.dDeRealCapacity = 398 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 399 400 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 401 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 402 403 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 404 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 405 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 406 } 407 } 408 409 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 410 { 411 PVDevice pVDev; 412 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 413 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 414 415 if (!pMvSataChannel) return; 416 417 if (plugged) 418 { 419 pVDev = &(pAdapter->VDevices[channelIndex]); 420 init_vdev_params(pAdapter, channelIndex); 421 422 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 423 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 424 425 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 426 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 427 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 428 pVDev->vf_online = 1; 429 430 #ifdef SUPPORT_ARRAY 431 if(pVDev->pParent) 432 { 433 int iMember; 434 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 435 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 436 pVDev->pParent->u.array.pMember[iMember] = NULL; 437 pVDev->pParent = NULL; 438 } 439 #endif 440 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 441 fCheckBootable(pVDev); 442 RegisterVDevice(pVDev); 443 444 #ifndef FOR_DEMO 445 if (pAdapter->beeping) { 446 pAdapter->beeping = 0; 447 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 448 } 449 #endif 450 451 } 452 else 453 { 454 pVDev = &(pAdapter->VDevices[channelIndex]); 455 failDevice(pVDev); 456 } 457 } 458 459 static int 460 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 461 { 462 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 463 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 464 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 465 MV_U32 udmaMode,pioMode; 466 467 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId, 468 channelNum)); 469 470 471 /* Software reset channel */ 472 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 473 { 474 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 475 pMvSataAdapter->adapterId, channelNum); 476 return -1; 477 } 478 479 /* Hardware reset channel */ 480 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 481 { 482 /* If failed, try again - this is when trying to hardreset a channel */ 483 /* when drive is just spinning up */ 484 StallExec(5000000); /* wait 5 sec before trying again */ 485 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 486 { 487 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n", 488 pMvSataAdapter->adapterId, channelNum); 489 return -1; 490 } 491 } 492 493 /* identify device*/ 494 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 495 { 496 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n" 497 , pMvSataAdapter->adapterId, channelNum); 498 return -1; 499 } 500 if (hptmv_parse_identify_results(pMvSataChannel)) 501 { 502 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n" 503 , pMvSataAdapter->adapterId, channelNum); 504 return -1; 505 } 506 507 /* mvStorageDevATASetFeatures */ 508 /* Disable 8 bit PIO in case CFA enabled */ 509 if (pMvSataChannel->identifyDevice[86] & 4) 510 { 511 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n", 512 pMvSataAdapter->adapterId)); 513 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 514 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 515 0, 0, 0) == MV_FALSE) 516 { 517 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures" 518 " failed\n", pMvSataAdapter->adapterId, channelNum); 519 return -1; 520 } 521 } 522 /* Write cache */ 523 #ifdef ENABLE_WRITE_CACHE 524 if (pMvSataChannel->identifyDevice[82] & 0x20) 525 { 526 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 527 { 528 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 529 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 530 0, 0, 0) == MV_FALSE) 531 { 532 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 533 pMvSataAdapter->adapterId, channelNum); 534 return -1; 535 } 536 } 537 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n", 538 pMvSataAdapter->adapterId, channelNum)); 539 } 540 else 541 { 542 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n", 543 pMvSataAdapter->adapterId, channelNum)); 544 } 545 #else /* disable write cache */ 546 { 547 if (pMvSataChannel->identifyDevice[85] & 0x20) 548 { 549 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n", 550 pMvSataAdapter->adapterId, channelNum)); 551 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 552 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 553 0, 0, 0) == MV_FALSE) 554 { 555 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 556 pMvSataAdapter->adapterId, channelNum); 557 return -1; 558 } 559 } 560 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n", 561 pMvSataAdapter->adapterId, channelNum)); 562 } 563 #endif 564 565 /* Set transfer mode */ 566 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n", 567 pMvSataAdapter->adapterId)); 568 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 569 MV_ATA_SET_FEATURES_TRANSFER, 570 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 571 MV_FALSE) 572 { 573 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 574 pMvSataAdapter->adapterId, channelNum); 575 return -1; 576 } 577 578 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 579 { 580 pioMode = MV_ATA_TRANSFER_PIO_4; 581 } 582 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 583 { 584 pioMode = MV_ATA_TRANSFER_PIO_3; 585 } 586 else 587 { 588 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 589 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 590 } 591 592 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n", 593 pMvSataAdapter->adapterId)); 594 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 595 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 596 MV_ATA_SET_FEATURES_TRANSFER, 597 pioMode, 0, 0, 0) == MV_FALSE) 598 { 599 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 600 pMvSataAdapter->adapterId, channelNum); 601 return -1; 602 } 603 604 udmaMode = MV_ATA_TRANSFER_UDMA_0; 605 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 606 { 607 udmaMode = MV_ATA_TRANSFER_UDMA_6; 608 } 609 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 610 { 611 udmaMode = MV_ATA_TRANSFER_UDMA_5; 612 } 613 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 614 { 615 udmaMode = MV_ATA_TRANSFER_UDMA_4; 616 } 617 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 618 { 619 udmaMode = MV_ATA_TRANSFER_UDMA_3; 620 } 621 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 622 { 623 udmaMode = MV_ATA_TRANSFER_UDMA_2; 624 } 625 626 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n", 627 pMvSataAdapter->adapterId, udmaMode & 0xf)); 628 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 629 630 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 631 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 632 0, 0, 0) == MV_FALSE) 633 { 634 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 635 pMvSataAdapter->adapterId, channelNum); 636 return -1; 637 }*/ 638 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 639 return TRUE; 640 else 641 do 642 { 643 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 644 MV_ATA_SET_FEATURES_TRANSFER, 645 pChannelInfo->maxUltraDmaModeSupported, 646 0, 0, 0) == MV_FALSE) 647 { 648 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 649 { 650 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 651 { 652 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 653 pMvSataChannel->eDmaRegsOffset + 654 0x11c, /* command reg */ 655 MV_ATA_COMMAND_IDLE_IMMEDIATE); 656 mvMicroSecondsDelay(10000); 657 mvSataChannelHardReset(pMvSataAdapter, channelNum); 658 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 659 return FALSE; 660 } 661 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 662 return FALSE; 663 pChannelInfo->maxUltraDmaModeSupported--; 664 continue; 665 } 666 else return FALSE; 667 } 668 break; 669 }while (1); 670 671 /* Read look ahead */ 672 #ifdef ENABLE_READ_AHEAD 673 if (pMvSataChannel->identifyDevice[82] & 0x40) 674 { 675 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 676 { 677 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 678 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 679 0, 0) == MV_FALSE) 680 { 681 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 682 pMvSataAdapter->adapterId, channelNum); 683 return -1; 684 } 685 } 686 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n", 687 pMvSataAdapter->adapterId, channelNum)); 688 } 689 else 690 { 691 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n", 692 pMvSataAdapter->adapterId, channelNum)); 693 } 694 #else 695 { 696 if (pMvSataChannel->identifyDevice[86] & 0x20) 697 { 698 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n", 699 pMvSataAdapter->adapterId, channelNum)); 700 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 701 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 702 0, 0) == MV_FALSE) 703 { 704 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n", 705 pMvSataAdapter->adapterId, channelNum); 706 return -1; 707 } 708 } 709 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n", 710 pMvSataAdapter->adapterId, channelNum)); 711 } 712 #endif 713 714 715 { 716 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n", 717 pMvSataAdapter->adapterId, 718 channelNum)); 719 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 720 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 721 { 722 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 723 pMvSataAdapter->adapterId, channelNum); 724 return -1; 725 } 726 } 727 /* Enable EDMA */ 728 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 729 { 730 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n", 731 pMvSataAdapter->adapterId, channelNum); 732 return -1; 733 } 734 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n", 735 pMvSataAdapter->adapterId, channelNum); 736 737 #ifndef FOR_DEMO 738 set_fail_led(pMvSataAdapter, channelNum, 0); 739 #endif 740 return 0; 741 } 742 743 static void 744 hptmv_handle_event(void * data, int flag) 745 { 746 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 747 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 748 MV_U8 channelIndex; 749 750 mtx_assert(&pAdapter->lock, MA_OWNED); 751 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 752 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 753 { 754 switch(pAdapter->sataEvents[channelIndex]) 755 { 756 case SATA_EVENT_CHANNEL_CONNECTED: 757 /* Handle only connects */ 758 if (flag == 1) 759 break; 760 KdPrint(("RR18xx [%d,%d]: new device connected\n", 761 pMvSataAdapter->adapterId, channelIndex)); 762 hptmv_init_channel(pAdapter, channelIndex); 763 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 764 { 765 MV_ERROR("RR18xx [%d,%d] Failed to configure\n", 766 pMvSataAdapter->adapterId, channelIndex); 767 hptmv_free_channel(pAdapter, channelIndex); 768 } 769 else 770 { 771 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 772 if (start_channel( pAdapter, channelIndex)) 773 { 774 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n", 775 pMvSataAdapter->adapterId, channelIndex); 776 hptmv_free_channel(pAdapter, channelIndex); 777 } 778 else 779 { 780 device_change(pAdapter, channelIndex, TRUE); 781 } 782 } 783 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 784 break; 785 786 case SATA_EVENT_CHANNEL_DISCONNECTED: 787 /* Handle only disconnects */ 788 if (flag == 0) 789 break; 790 KdPrint(("RR18xx [%d,%d]: device disconnected\n", 791 pMvSataAdapter->adapterId, channelIndex)); 792 /* Flush pending commands */ 793 if(pMvSataAdapter->sataChannel[channelIndex]) 794 { 795 _VBUS_INST(&pAdapter->VBus) 796 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 797 MV_FLUSH_TYPE_CALLBACK); 798 CheckPendingCall(_VBUS_P0); 799 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 800 hptmv_free_channel(pAdapter, channelIndex); 801 pMvSataAdapter->sataChannel[channelIndex] = NULL; 802 KdPrint(("RR18xx [%d,%d]: channel removed\n", 803 pMvSataAdapter->adapterId, channelIndex)); 804 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 805 Check_Idle_Call(pAdapter); 806 } 807 else 808 { 809 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n", 810 pMvSataAdapter->adapterId, channelIndex)); 811 } 812 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 813 break; 814 815 case SATA_EVENT_NO_CHANGE: 816 break; 817 818 default: 819 break; 820 } 821 } 822 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 823 } 824 825 #define EVENT_CONNECT 1 826 #define EVENT_DISCONNECT 0 827 828 static void 829 hptmv_handle_event_connect(void *data) 830 { 831 hptmv_handle_event (data, 0); 832 } 833 834 static void 835 hptmv_handle_event_disconnect(void *data) 836 { 837 hptmv_handle_event (data, 1); 838 } 839 840 static MV_BOOLEAN 841 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 842 MV_U32 param1, MV_U32 param2) 843 { 844 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 845 846 switch (eventType) 847 { 848 case MV_EVENT_TYPE_SATA_CABLE: 849 { 850 MV_U8 channel = param2; 851 852 if (param1 == EVENT_CONNECT) 853 { 854 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 855 KdPrint(("RR18xx [%d,%d]: device connected event received\n", 856 pMvSataAdapter->adapterId, channel)); 857 /* Delete previous timers (if multiple drives connected in the same time */ 858 callout_reset(&pAdapter->event_timer_connect, 10 * hz, hptmv_handle_event_connect, pAdapter); 859 } 860 else if (param1 == EVENT_DISCONNECT) 861 { 862 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 863 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n", 864 pMvSataAdapter->adapterId, channel)); 865 device_change(pAdapter, channel, FALSE); 866 /* Delete previous timers (if multiple drives disconnected in the same time */ 867 /*callout_reset(&pAdapter->event_timer_disconnect, 10 * hz, hptmv_handle_event_disconnect, pAdapter); */ 868 /*It is not necessary to wait, handle it directly*/ 869 hptmv_handle_event_disconnect(pAdapter); 870 } 871 else 872 { 873 874 MV_ERROR("RR18xx: illegal value for param1(%d) at " 875 "connect/disconnect event, host=%d\n", param1, 876 pMvSataAdapter->adapterId ); 877 878 } 879 } 880 break; 881 case MV_EVENT_TYPE_ADAPTER_ERROR: 882 KdPrint(("RR18xx: DEVICE error event received, pci cause " 883 "reg=%x, don't how to handle this\n", param1)); 884 return MV_TRUE; 885 default: 886 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n", 887 pMvSataAdapter->adapterId, eventType); 888 return MV_FALSE; 889 } 890 return MV_TRUE; 891 } 892 893 static int 894 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 895 { 896 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 897 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 898 if (pAdapter->requestsArrayBaseAddr == NULL) 899 { 900 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request" 901 " queues\n", pAdapter->mvSataAdapter.adapterId); 902 return -1; 903 } 904 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 905 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 906 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 907 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 908 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 909 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 910 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 911 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 912 913 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 914 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 915 { 916 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n", 917 pAdapter->mvSataAdapter.adapterId); 918 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 919 return -1; 920 } 921 /* response queues */ 922 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 923 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 924 if (pAdapter->responsesArrayBaseAddr == NULL) 925 { 926 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response" 927 " queues\n", pAdapter->mvSataAdapter.adapterId); 928 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 929 return -1; 930 } 931 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 932 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 933 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 934 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 935 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 936 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 937 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 938 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 939 940 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 941 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 942 { 943 MV_ERROR("RR18xx[%d]: Error in Response Queues Alignment\n", 944 pAdapter->mvSataAdapter.adapterId); 945 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 946 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 947 return -1; 948 } 949 return 0; 950 } 951 952 static void 953 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 954 { 955 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 956 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 957 } 958 959 static PVOID 960 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 961 { 962 PVOID ret; 963 if (pAdapter->pFreePRDLink) { 964 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 965 ret = pAdapter->pFreePRDLink; 966 pAdapter->pFreePRDLink = *(void**)ret; 967 return ret; 968 } 969 return NULL; 970 } 971 972 static void 973 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 974 { 975 *(void**)PRDTable = pAdapter->pFreePRDLink; 976 pAdapter->pFreePRDLink = PRDTable; 977 } 978 979 extern PVDevice fGetFirstChild(PVDevice pLogical); 980 extern void fResetBootMark(PVDevice pLogical); 981 static void 982 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 983 { 984 PVDevice pPhysical, pLogical; 985 PVBus pVBus; 986 int i,j; 987 988 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 989 pPhysical = &(pAdapter->VDevices[i]); 990 pLogical = pPhysical; 991 while (pLogical->pParent) pLogical = pLogical->pParent; 992 if (pLogical->vf_online==0) { 993 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 994 continue; 995 } 996 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 997 continue; 998 999 pVBus = &pAdapter->VBus; 1000 if(pVBus) 1001 { 1002 j=0; 1003 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1004 if(j<MAX_VDEVICE_PER_VBUS){ 1005 pVBus->pVDevice[j] = pLogical; 1006 pLogical->pVBus = pVBus; 1007 1008 if (j>0 && pLogical->vf_bootmark) { 1009 if (pVBus->pVDevice[0]->vf_bootmark) { 1010 fResetBootMark(pLogical); 1011 } 1012 else { 1013 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1014 pVBus->pVDevice[0] = pLogical; 1015 } 1016 } 1017 } 1018 } 1019 } 1020 } 1021 1022 PVDevice 1023 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1024 { 1025 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1026 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1027 LBA_T thiscap, maxcap = MAX_LBA_T; 1028 PVDevice pVDevice, pFind = NULL; 1029 int i; 1030 1031 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1032 { 1033 pVDevice = &pAdapter->VDevices[i]; 1034 if(!pVDevice) 1035 continue; 1036 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1037 /* find the smallest usable spare disk */ 1038 if (pVDevice->VDeviceType==VD_SPARE && 1039 pVDevice->u.disk.df_on_line && 1040 thiscap < maxcap && 1041 thiscap >= capacity) 1042 { 1043 maxcap = pVDevice->VDeviceCapacity; 1044 pFind = pVDevice; 1045 } 1046 } 1047 return pFind; 1048 } 1049 1050 /****************************************************************** 1051 * IO ATA Command 1052 *******************************************************************/ 1053 int HPTLIBAPI 1054 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1055 { 1056 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1057 } 1058 1059 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1060 { 1061 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1062 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1063 MV_U8 channelIndex = pSataChannel->channelNumber; 1064 UCHAR mvMode; 1065 /* 508x don't use MW-DMA? */ 1066 if (NewMode>4 && NewMode<8) NewMode = 4; 1067 pDev->bDeModeSetting = NewMode; 1068 if (NewMode<=4) 1069 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1070 else 1071 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1072 1073 /*To fix 88i8030 bug*/ 1074 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1075 mvMode = MV_ATA_TRANSFER_UDMA_0; 1076 1077 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1078 /* Flush pending commands */ 1079 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1080 1081 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1082 MV_ATA_SET_FEATURES_TRANSFER, 1083 mvMode, 0, 0, 0) == MV_FALSE) 1084 { 1085 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1086 } 1087 /* Enable EDMA */ 1088 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1089 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1090 } 1091 1092 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth) 1093 { 1094 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1095 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1096 MV_U8 channelIndex = pSataChannel->channelNumber; 1097 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1098 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1099 int dmaActive = pSataChannel->queueCommandsEnabled; 1100 int ret = 0; 1101 1102 if (dmaActive) { 1103 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1104 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1105 } 1106 1107 if (enable) { 1108 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED && 1109 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) { 1110 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1; 1111 channelInfo->queueDepth = (depth==32)? 31 : depth; 1112 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth); 1113 ret = 1; 1114 } 1115 } 1116 else 1117 { 1118 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) { 1119 channelInfo->queueDepth = 2; 1120 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0); 1121 ret = 1; 1122 } 1123 } 1124 1125 if (dmaActive) 1126 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1127 return ret; 1128 } 1129 1130 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth) 1131 { 1132 return 0; 1133 } 1134 1135 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable) 1136 { 1137 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1138 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1139 MV_U8 channelIndex = pSataChannel->channelNumber; 1140 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1141 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1142 int dmaActive = pSataChannel->queueCommandsEnabled; 1143 int ret = 0; 1144 1145 if (dmaActive) { 1146 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1147 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1148 } 1149 1150 if ((pSataChannel->identifyDevice[82] & (0x20))) { 1151 if (enable) { 1152 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1153 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0)) 1154 { 1155 channelInfo->writeCacheEnabled = MV_TRUE; 1156 ret = 1; 1157 } 1158 } 1159 else { 1160 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1161 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0)) 1162 { 1163 channelInfo->writeCacheEnabled = MV_FALSE; 1164 ret = 1; 1165 } 1166 } 1167 } 1168 1169 if (dmaActive) 1170 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1171 return ret; 1172 } 1173 1174 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable) 1175 { 1176 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1177 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1178 MV_U8 channelIndex = pSataChannel->channelNumber; 1179 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1180 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1181 int dmaActive = pSataChannel->queueCommandsEnabled; 1182 int ret = 0; 1183 1184 if (dmaActive) { 1185 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1186 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1187 } 1188 1189 if ((pSataChannel->identifyDevice[82] & (0x40))) { 1190 if (enable) { 1191 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1192 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0)) 1193 { 1194 channelInfo->readAheadEnabled = MV_TRUE; 1195 ret = 1; 1196 } 1197 } 1198 else { 1199 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1200 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0)) 1201 { 1202 channelInfo->readAheadEnabled = MV_FALSE; 1203 ret = 1; 1204 } 1205 } 1206 } 1207 1208 if (dmaActive) 1209 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1210 return ret; 1211 } 1212 1213 #ifdef SUPPORT_ARRAY 1214 #define IdeRegisterVDevice fCheckArray 1215 #else 1216 void 1217 IdeRegisterVDevice(PDevice pDev) 1218 { 1219 PVDevice pVDev = Map2pVDevice(pDev); 1220 1221 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1222 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1223 pVDev->vf_online = 1; 1224 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1225 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1226 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1227 } 1228 #endif 1229 1230 static __inline PBUS_DMAMAP 1231 dmamap_get(struct IALAdapter * pAdapter) 1232 { 1233 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1234 if (p) 1235 pAdapter->pbus_dmamap_list = p-> next; 1236 return p; 1237 } 1238 1239 static __inline void 1240 dmamap_put(PBUS_DMAMAP p) 1241 { 1242 p->next = p->pAdapter->pbus_dmamap_list; 1243 p->pAdapter->pbus_dmamap_list = p; 1244 } 1245 1246 static int num_adapters = 0; 1247 static int 1248 init_adapter(IAL_ADAPTER_T *pAdapter) 1249 { 1250 PVBus _vbus_p = &pAdapter->VBus; 1251 MV_SATA_ADAPTER *pMvSataAdapter; 1252 int i, channel, rid; 1253 1254 PVDevice pVDev; 1255 1256 mtx_init(&pAdapter->lock, "hptsleeplock", NULL, MTX_DEF); 1257 callout_init_mtx(&pAdapter->event_timer_connect, &pAdapter->lock, 0); 1258 callout_init_mtx(&pAdapter->event_timer_disconnect, &pAdapter->lock, 0); 1259 1260 sx_xlock(&hptmv_list_lock); 1261 pAdapter->next = 0; 1262 1263 if(gIal_Adapter == NULL){ 1264 gIal_Adapter = pAdapter; 1265 pCurAdapter = gIal_Adapter; 1266 } 1267 else { 1268 pCurAdapter->next = pAdapter; 1269 pCurAdapter = pAdapter; 1270 } 1271 sx_xunlock(&hptmv_list_lock); 1272 1273 pAdapter->outstandingCommands = 0; 1274 1275 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1276 _vbus_p->OsExt = (void *)pAdapter; 1277 pMvSataAdapter->IALData = pAdapter; 1278 1279 if (bus_dma_tag_create(bus_get_dma_tag(pAdapter->hpt_dev),/* parent */ 1280 4, /* alignment */ 1281 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1282 BUS_SPACE_MAXADDR, /* lowaddr */ 1283 BUS_SPACE_MAXADDR, /* highaddr */ 1284 NULL, NULL, /* filter, filterarg */ 1285 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1286 MAX_SG_DESCRIPTORS, /* nsegments */ 1287 0x10000, /* maxsegsize */ 1288 BUS_DMA_WAITOK, /* flags */ 1289 busdma_lock_mutex, /* lockfunc */ 1290 &pAdapter->lock, /* lockfuncarg */ 1291 &pAdapter->io_dma_parent /* tag */)) 1292 { 1293 return ENXIO; 1294 } 1295 1296 1297 if (hptmv_allocate_edma_queues(pAdapter)) 1298 { 1299 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n"); 1300 return ENOMEM; 1301 } 1302 1303 /* also map EPROM address */ 1304 rid = 0x10; 1305 if (!(pAdapter->mem_res = bus_alloc_resource_any(pAdapter->hpt_dev, 1306 SYS_RES_MEMORY, &rid, RF_ACTIVE)) 1307 || 1308 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1309 { 1310 MV_ERROR("RR18xx: Failed to remap memory space\n"); 1311 hptmv_free_edma_queues(pAdapter); 1312 return ENXIO; 1313 } 1314 else 1315 { 1316 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1317 } 1318 1319 pMvSataAdapter->adapterId = num_adapters++; 1320 /* get the revision ID */ 1321 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1322 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1323 1324 /* init RR18xx */ 1325 pMvSataAdapter->intCoalThre[0]= 1; 1326 pMvSataAdapter->intCoalThre[1]= 1; 1327 pMvSataAdapter->intTimeThre[0] = 1; 1328 pMvSataAdapter->intTimeThre[1] = 1; 1329 pMvSataAdapter->pciCommand = 0x0107E371; 1330 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1331 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1332 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1333 1334 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1335 { 1336 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n", 1337 pMvSataAdapter->adapterId); 1338 unregister: 1339 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1340 hptmv_free_edma_queues(pAdapter); 1341 return ENXIO; 1342 } 1343 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1344 1345 #ifndef FOR_DEMO 1346 set_fail_leds(pMvSataAdapter, 0); 1347 #endif 1348 1349 /* setup command blocks */ 1350 KdPrint(("Allocate command blocks\n")); 1351 _vbus_(pFreeCommands) = 0; 1352 pAdapter->pCommandBlocks = 1353 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1354 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1355 if (!pAdapter->pCommandBlocks) { 1356 MV_ERROR("insufficient memory\n"); 1357 goto unregister; 1358 } 1359 1360 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1361 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1362 } 1363 1364 /*Set up the bus_dmamap*/ 1365 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1366 if(!pAdapter->pbus_dmamap) { 1367 MV_ERROR("insufficient memory\n"); 1368 free(pAdapter->pCommandBlocks, M_DEVBUF); 1369 goto unregister; 1370 } 1371 1372 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1373 pAdapter->pbus_dmamap_list = 0; 1374 for (i=0; i < MAX_QUEUE_COMM; i++) { 1375 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1376 pmap->pAdapter = pAdapter; 1377 dmamap_put(pmap); 1378 1379 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1380 MV_ERROR("Can not allocate dma map\n"); 1381 free(pAdapter->pCommandBlocks, M_DEVBUF); 1382 free(pAdapter->pbus_dmamap, M_DEVBUF); 1383 goto unregister; 1384 } 1385 callout_init_mtx(&pmap->timeout, &pAdapter->lock, 0); 1386 } 1387 /* setup PRD Tables */ 1388 KdPrint(("Allocate PRD Tables\n")); 1389 pAdapter->pFreePRDLink = 0; 1390 1391 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1392 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1393 1394 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1395 if (!pAdapter->prdTableAddr) { 1396 MV_ERROR("insufficient PRD Tables\n"); 1397 goto unregister; 1398 } 1399 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1400 { 1401 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1402 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1403 { 1404 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1405 FreePRDTable(pAdapter, PRDTable); 1406 PRDTable += PRD_ENTRIES_SIZE; 1407 } 1408 } 1409 1410 /* enable the adapter interrupts */ 1411 1412 /* configure and start the connected channels*/ 1413 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1414 { 1415 pAdapter->mvChannel[channel].online = MV_FALSE; 1416 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1417 == MV_TRUE) 1418 { 1419 KdPrint(("RR18xx[%d]: channel %d is connected\n", 1420 pMvSataAdapter->adapterId, channel)); 1421 1422 if (hptmv_init_channel(pAdapter, channel) == 0) 1423 { 1424 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1425 { 1426 MV_ERROR("RR18xx[%d]: Failed to configure channel" 1427 " %d\n",pMvSataAdapter->adapterId, channel); 1428 hptmv_free_channel(pAdapter, channel); 1429 } 1430 else 1431 { 1432 if (start_channel(pAdapter, channel)) 1433 { 1434 MV_ERROR("RR18xx[%d]: Failed to start channel," 1435 " channel=%d\n",pMvSataAdapter->adapterId, 1436 channel); 1437 hptmv_free_channel(pAdapter, channel); 1438 } 1439 pAdapter->mvChannel[channel].online = MV_TRUE; 1440 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1441 channel, 1442 MV_TRUE);*/ 1443 } 1444 } 1445 } 1446 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1447 pAdapter->mvChannel[channel].online, channel)); 1448 } 1449 1450 #ifdef SUPPORT_ARRAY 1451 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1452 pVDev = ArrayTables(i); 1453 mArFreeArrayTable(pVDev); 1454 } 1455 #endif 1456 1457 KdPrint(("Initialize Devices\n")); 1458 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1459 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1460 if (pMvSataChannel) { 1461 init_vdev_params(pAdapter, channel); 1462 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1463 } 1464 } 1465 #ifdef SUPPORT_ARRAY 1466 CheckArrayCritical(_VBUS_P0); 1467 #endif 1468 _vbus_p->nInstances = 1; 1469 fRegisterVdevice(pAdapter); 1470 1471 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1472 pVDev = _vbus_p->pVDevice[channel]; 1473 if (pVDev && pVDev->vf_online) 1474 fCheckBootable(pVDev); 1475 } 1476 1477 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1478 init_raid5_memory(_VBUS_P0); 1479 _vbus_(r5).enable_write_back = 1; 1480 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1481 #endif 1482 1483 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1484 return 0; 1485 } 1486 1487 int 1488 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1489 { 1490 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1491 1492 mvSataDisableChannelDma(pMvSataAdapter, channel); 1493 /* Flush pending commands */ 1494 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1495 1496 /* Software reset channel */ 1497 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1498 { 1499 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 1500 pMvSataAdapter->adapterId, channel); 1501 hptmv_free_channel(pAdapter, channel); 1502 return -1; 1503 } 1504 1505 /* Hardware reset channel */ 1506 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1507 { 1508 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n", 1509 pMvSataAdapter->adapterId, channel); 1510 hptmv_free_channel(pAdapter, channel); 1511 return -1; 1512 } 1513 1514 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1515 { 1516 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n", 1517 pMvSataAdapter->adapterId, channel); 1518 hptmv_free_channel(pAdapter, channel); 1519 return -1; 1520 }else 1521 { 1522 MV_ERROR("channel %d: perform recalibrate command", channel); 1523 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1524 MV_NON_UDMA_PROTOCOL_NON_DATA, 1525 MV_FALSE, 1526 NULL, /* pBuffer*/ 1527 0, /* count */ 1528 0, /*features*/ 1529 /* sectorCount */ 1530 0, 1531 0, /* lbaLow */ 1532 0, /* lbaMid */ 1533 /* lbaHigh */ 1534 0, 1535 0, /* device */ 1536 /* command */ 1537 0x10)) 1538 MV_ERROR("channel %d: recalibrate failed", channel); 1539 1540 /* Set transfer mode */ 1541 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1542 MV_ATA_SET_FEATURES_TRANSFER, 1543 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1544 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1545 MV_ATA_SET_FEATURES_TRANSFER, 1546 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1547 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1548 MV_ATA_SET_FEATURES_TRANSFER, 1549 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1550 { 1551 MV_ERROR("channel %d: Set Features failed", channel); 1552 hptmv_free_channel(pAdapter, channel); 1553 return -1; 1554 } 1555 /* Enable EDMA */ 1556 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1557 { 1558 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1559 hptmv_free_channel(pAdapter, channel); 1560 return -1; 1561 } 1562 } 1563 return 0; 1564 } 1565 1566 static int 1567 fResetActiveCommands(PVBus _vbus_p) 1568 { 1569 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1570 MV_U8 channel; 1571 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1572 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1573 MvSataResetChannel(pMvSataAdapter,channel); 1574 } 1575 return 0; 1576 } 1577 1578 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1579 { 1580 UINT cont; 1581 ULONG ticks = 0; 1582 MV_U8 channel; 1583 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1584 MV_SATA_CHANNEL *pMvSataChannel; 1585 1586 do { 1587 check_cmds: 1588 cont = 0; 1589 CheckPendingCall(_VBUS_P0); 1590 #ifdef _RAID5N_ 1591 dataxfer_poll(); 1592 xor_poll(); 1593 #endif 1594 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1595 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1596 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1597 { 1598 while (pMvSataChannel->outstandingCommands) { 1599 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1600 StallExec(1000); 1601 if (ticks++ > 3000) { 1602 MvSataResetChannel(pMvSataAdapter,channel); 1603 goto check_cmds; 1604 } 1605 } 1606 else 1607 ticks = 0; 1608 } 1609 cont = 1; 1610 } 1611 } 1612 } while (cont); 1613 } 1614 1615 void 1616 fResetVBus(_VBUS_ARG0) 1617 { 1618 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1619 1620 /* some commands may already finished. */ 1621 CheckPendingCall(_VBUS_P0); 1622 1623 fResetActiveCommands(_vbus_p); 1624 /* 1625 * the other pending commands may still be finished successfully. 1626 */ 1627 fCompleteAllCommandsSynchronously(_vbus_p); 1628 1629 /* Now there should be no pending commands. No more action needed. */ 1630 CheckIdleCall(_VBUS_P0); 1631 1632 KdPrint(("fMvResetBus() done")); 1633 } 1634 1635 /*No rescan function*/ 1636 void 1637 fRescanAllDevice(_VBUS_ARG0) 1638 { 1639 } 1640 1641 static MV_BOOLEAN 1642 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1643 MV_U8 channelNum, 1644 MV_COMPLETION_TYPE comp_type, 1645 MV_VOID_PTR commandId, 1646 MV_U16 responseFlags, 1647 MV_U32 timeStamp, 1648 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1649 { 1650 PCommand pCmd = (PCommand) commandId; 1651 _VBUS_INST(pCmd->pVDevice->pVBus) 1652 1653 if (pCmd->uScratch.sata_param.prdAddr) 1654 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1655 1656 switch (comp_type) 1657 { 1658 case MV_COMPLETION_TYPE_NORMAL: 1659 pCmd->Result = RETURN_SUCCESS; 1660 break; 1661 case MV_COMPLETION_TYPE_ABORT: 1662 pCmd->Result = RETURN_BUS_RESET; 1663 break; 1664 case MV_COMPLETION_TYPE_ERROR: 1665 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1666 pMvSataAdapter->adapterId, channelNum, responseFlags); 1667 1668 if (responseFlags & 4) { 1669 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1670 " LBA high %x, device %x, status %x\n", 1671 registerStruct->errorRegister, 1672 registerStruct->sectorCountRegister, 1673 registerStruct->lbaLowRegister, 1674 registerStruct->lbaMidRegister, 1675 registerStruct->lbaHighRegister, 1676 registerStruct->deviceRegister, 1677 registerStruct->statusRegister); 1678 } 1679 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1680 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1681 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1682 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1683 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1684 pCmd->pVDevice->u.disk.QueueLength--; 1685 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1686 return TRUE; 1687 1688 default: 1689 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1690 return MV_FALSE; 1691 } 1692 1693 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1694 pCmd->uScratch.sata_param.cmd_priv --; 1695 return TRUE; 1696 } 1697 pCmd->pVDevice->u.disk.QueueLength--; 1698 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1699 return TRUE; 1700 } 1701 1702 void 1703 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1704 { 1705 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1706 MV_SATA_ADAPTER *pMvSataAdapter; 1707 MV_SATA_CHANNEL *pMvSataChannel; 1708 PVDevice pVDevice = pCmd->pVDevice; 1709 PDevice pDevice = &pVDevice->u.disk; 1710 LBA_T Lba = pCmd->uCmd.Ide.Lba; 1711 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1712 1713 MV_QUEUE_COMMAND_RESULT result; 1714 MV_QUEUE_COMMAND_INFO commandInfo; 1715 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1716 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1717 1718 MV_BOOLEAN is48bit; 1719 MV_U8 channel; 1720 int i=0; 1721 1722 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1723 1724 if (!pDevice->df_on_line) { 1725 MV_ERROR("Device is offline"); 1726 pCmd->Result = RETURN_BAD_DEVICE; 1727 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1728 return; 1729 } 1730 1731 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1732 pMvSataChannel = pDevice->mv; 1733 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1734 channel = pMvSataChannel->channelNumber; 1735 1736 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1737 Lba += pDevice->dDeHiddenLba; 1738 /* check LBA */ 1739 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1740 pCmd->Result = RETURN_INVALID_REQUEST; 1741 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1742 return; 1743 } 1744 1745 /* 1746 * always use 48bit LBA if drive supports it. 1747 * Some Seagate drives report error if you use a 28-bit command 1748 * to access sector 0xfffffff. 1749 */ 1750 is48bit = pMvSataChannel->lba48Address; 1751 1752 switch (pCmd->uCmd.Ide.Command) 1753 { 1754 case IDE_COMMAND_READ: 1755 case IDE_COMMAND_WRITE: 1756 if (pDevice->bDeModeSetting<8) goto pio; 1757 1758 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1759 pUdmaParams->isEXT = is48bit; 1760 pUdmaParams->numOfSectors = nSector; 1761 pUdmaParams->lowLBAAddress = Lba; 1762 pUdmaParams->highLBAAddress = 0; 1763 pUdmaParams->prdHighAddr = 0; 1764 pUdmaParams->callBack = CommandCompletionCB; 1765 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1766 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1767 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1768 else 1769 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1770 1771 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1772 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1773 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1774 } 1775 else { 1776 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1777 pio: 1778 mvSataDisableChannelDma(pMvSataAdapter, channel); 1779 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1780 1781 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1782 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1783 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1784 } 1785 else { 1786 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1787 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1788 goto finish_cmd; 1789 } 1790 } 1791 1792 do { 1793 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1794 ULONG_PTR addr = tmpSg->dSgAddress; 1795 if (size & 0x1ff) { 1796 pCmd->Result = RETURN_INVALID_REQUEST; 1797 goto finish_cmd; 1798 } 1799 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1800 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1801 is48bit, 1802 (MV_U16_PTR)addr, 1803 size >> 1, /* count */ 1804 0, /* features N/A */ 1805 (MV_U16)(size>>9), /*sector count*/ 1806 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1807 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1808 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1809 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1810 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1811 )==MV_FALSE) 1812 { 1813 pCmd->Result = RETURN_IDE_ERROR; 1814 goto finish_cmd; 1815 } 1816 Lba += size>>9; 1817 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1818 } 1819 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1820 pCmd->Result = RETURN_SUCCESS; 1821 finish_cmd: 1822 mvSataEnableChannelDma(pMvSataAdapter,channel); 1823 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1824 return; 1825 } 1826 } 1827 1828 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1829 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1830 if (!pPRDTable) { 1831 pCmd->Result = RETURN_DEVICE_BUSY; 1832 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1833 HPT_ASSERT(0); 1834 return; 1835 } 1836 1837 do{ 1838 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1839 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1840 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1841 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1842 pPRDTable[i].reserved = 0; 1843 i++; 1844 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1845 1846 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1847 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1848 pUdmaParams->numOfSectors = 0; 1849 } 1850 1851 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1852 1853 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1854 1855 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1856 { 1857 queue_failed: 1858 switch (result) 1859 { 1860 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1861 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1862 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1863 pCmd->Result = RETURN_IDE_ERROR; 1864 break; 1865 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1866 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1867 " disabled adapter %d channel %d\n", 1868 pMvSataAdapter->adapterId, channel); 1869 mvSataEnableChannelDma(pMvSataAdapter,channel); 1870 pCmd->Result = RETURN_IDE_ERROR; 1871 break; 1872 case MV_QUEUE_COMMAND_RESULT_FULL: 1873 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1874 " Full adapter %d channel %d\n", 1875 pMvSataAdapter->adapterId, channel); 1876 pCmd->Result = RETURN_DEVICE_BUSY; 1877 break; 1878 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1879 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1880 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1881 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1882 pCmd->Result = RETURN_IDE_ERROR; 1883 break; 1884 default: 1885 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1886 " command\n", result); 1887 pCmd->Result = RETURN_IDE_ERROR; 1888 } 1889 if(pPRDTable) 1890 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1891 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1892 } 1893 pDevice->QueueLength++; 1894 return; 1895 1896 case IDE_COMMAND_VERIFY: 1897 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1898 pNoUdmaParams->bufPtr = NULL; 1899 pNoUdmaParams->callBack = CommandCompletionCB; 1900 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1901 pNoUdmaParams->count = 0; 1902 pNoUdmaParams->features = 0; 1903 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1904 1905 pCmd->uScratch.sata_param.cmd_priv = 1; 1906 if (pMvSataChannel->lba48Address == MV_TRUE){ 1907 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1908 pNoUdmaParams->isEXT = MV_TRUE; 1909 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1910 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1911 pNoUdmaParams->lbaLow = 1912 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1913 pNoUdmaParams->sectorCount = nSector; 1914 pNoUdmaParams->device = 0x40; 1915 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1916 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1917 goto queue_failed; 1918 } 1919 return; 1920 } 1921 else{ 1922 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1923 pNoUdmaParams->isEXT = MV_FALSE; 1924 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1925 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1926 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1927 pNoUdmaParams->sectorCount = 0xff & nSector; 1928 pNoUdmaParams->device = (MV_U8)(0x40 | 1929 ((Lba & 0xf000000) >> 24)); 1930 pNoUdmaParams->callBack = CommandCompletionCB; 1931 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1932 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1933 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1934 goto queue_failed; 1935 } 1936 } 1937 break; 1938 default: 1939 pCmd->Result = RETURN_INVALID_REQUEST; 1940 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1941 break; 1942 } 1943 } 1944 1945 /********************************************************** 1946 * 1947 * Probe the hostadapter. 1948 * 1949 **********************************************************/ 1950 static int 1951 hpt_probe(device_t dev) 1952 { 1953 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 1954 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 1955 #ifdef FOR_DEMO 1956 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 1957 #endif 1958 )) 1959 { 1960 KdPrintI((CONTROLLER_NAME " found\n")); 1961 device_set_desc(dev, CONTROLLER_NAME); 1962 return (BUS_PROBE_DEFAULT); 1963 } 1964 else 1965 return(ENXIO); 1966 } 1967 1968 /*********************************************************** 1969 * 1970 * Auto configuration: attach and init a host adapter. 1971 * 1972 ***********************************************************/ 1973 static int 1974 hpt_attach(device_t dev) 1975 { 1976 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 1977 int rid; 1978 union ccb *ccb; 1979 struct cam_devq *devq; 1980 struct cam_sim *hpt_vsim; 1981 1982 device_printf(dev, "%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 1983 1984 pAdapter->hpt_dev = dev; 1985 1986 rid = init_adapter(pAdapter); 1987 if (rid) 1988 return rid; 1989 1990 rid = 0; 1991 if ((pAdapter->hpt_irq = bus_alloc_resource_any(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) 1992 { 1993 hpt_printk(("can't allocate interrupt\n")); 1994 return(ENXIO); 1995 } 1996 1997 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, 1998 INTR_TYPE_CAM | INTR_MPSAFE, 1999 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr)) 2000 { 2001 hpt_printk(("can't set up interrupt\n")); 2002 free(pAdapter, M_DEVBUF); 2003 return(ENXIO); 2004 } 2005 2006 2007 ccb = xpt_alloc_ccb(); 2008 ccb->ccb_h.pinfo.priority = 1; 2009 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 2010 2011 /* 2012 * Create the device queue for our SIM(s). 2013 */ 2014 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 2015 { 2016 KdPrint(("ENXIO\n")); 2017 return ENOMEM; 2018 } 2019 2020 /* 2021 * Construct our SIM entry 2022 */ 2023 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2024 pAdapter, device_get_unit(pAdapter->hpt_dev), 2025 &pAdapter->lock, 1, 8, devq); 2026 if (hpt_vsim == NULL) { 2027 cam_simq_free(devq); 2028 return ENOMEM; 2029 } 2030 2031 mtx_lock(&pAdapter->lock); 2032 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS) 2033 { 2034 cam_sim_free(hpt_vsim, /*free devq*/ TRUE); 2035 mtx_unlock(&pAdapter->lock); 2036 hpt_vsim = NULL; 2037 return ENXIO; 2038 } 2039 2040 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 2041 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 2042 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 2043 { 2044 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 2045 cam_sim_free(hpt_vsim, /*free_devq*/TRUE); 2046 mtx_unlock(&pAdapter->lock); 2047 hpt_vsim = NULL; 2048 return ENXIO; 2049 } 2050 mtx_unlock(&pAdapter->lock); 2051 2052 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 2053 ccb->ccb_h.func_code = XPT_SASYNC_CB; 2054 ccb->csa.event_enable = AC_LOST_DEVICE; 2055 ccb->csa.callback = hpt_async; 2056 ccb->csa.callback_arg = hpt_vsim; 2057 xpt_action((union ccb *)ccb); 2058 xpt_free_ccb(ccb); 2059 2060 if (device_get_unit(dev) == 0) { 2061 /* Start the work thread. XXX */ 2062 launch_worker_thread(); 2063 } 2064 2065 return 0; 2066 } 2067 2068 static int 2069 hpt_detach(device_t dev) 2070 { 2071 return (EBUSY); 2072 } 2073 2074 2075 /*************************************************************** 2076 * The poll function is used to simulate the interrupt when 2077 * the interrupt subsystem is not functioning. 2078 * 2079 ***************************************************************/ 2080 static void 2081 hpt_poll(struct cam_sim *sim) 2082 { 2083 2084 hpt_intr_locked((void *)cam_sim_softc(sim)); 2085 } 2086 2087 /**************************************************************** 2088 * Name: hpt_intr 2089 * Description: Interrupt handler. 2090 ****************************************************************/ 2091 static void 2092 hpt_intr(void *arg) 2093 { 2094 IAL_ADAPTER_T *pAdapter; 2095 2096 pAdapter = arg; 2097 mtx_lock(&pAdapter->lock); 2098 hpt_intr_locked(pAdapter); 2099 mtx_unlock(&pAdapter->lock); 2100 } 2101 2102 static void 2103 hpt_intr_locked(IAL_ADAPTER_T *pAdapter) 2104 { 2105 2106 mtx_assert(&pAdapter->lock, MA_OWNED); 2107 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2108 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2109 { 2110 _VBUS_INST(&pAdapter->VBus) 2111 CheckPendingCall(_VBUS_P0); 2112 } 2113 2114 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2115 } 2116 2117 /********************************************************** 2118 * Asynchronous Events 2119 *********************************************************/ 2120 #if (!defined(UNREFERENCED_PARAMETER)) 2121 #define UNREFERENCED_PARAMETER(x) (void)(x) 2122 #endif 2123 2124 static void 2125 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2126 void * arg) 2127 { 2128 /* debug XXXX */ 2129 panic("Here"); 2130 UNREFERENCED_PARAMETER(callback_arg); 2131 UNREFERENCED_PARAMETER(code); 2132 UNREFERENCED_PARAMETER(path); 2133 UNREFERENCED_PARAMETER(arg); 2134 2135 } 2136 2137 static void 2138 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2139 { 2140 int i; 2141 2142 hpt_printk(("flush all devices\n")); 2143 2144 /* flush all devices */ 2145 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2146 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2147 if(pVDev) fFlushVDev(pVDev); 2148 } 2149 } 2150 2151 static int 2152 hpt_shutdown(device_t dev) 2153 { 2154 IAL_ADAPTER_T *pAdapter; 2155 2156 pAdapter = device_get_softc(dev); 2157 2158 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh); 2159 mtx_lock(&pAdapter->lock); 2160 FlushAdapter(pAdapter); 2161 mtx_unlock(&pAdapter->lock); 2162 /* give the flush some time to happen, 2163 *otherwise "shutdown -p now" will make file system corrupted */ 2164 DELAY(1000 * 1000 * 5); 2165 return 0; 2166 } 2167 2168 void 2169 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2170 { 2171 _VBUS_INST(&pAdapter->VBus) 2172 2173 if (mWaitingForIdle(_VBUS_P0)) { 2174 CheckIdleCall(_VBUS_P0); 2175 #ifdef SUPPORT_ARRAY 2176 { 2177 int i; 2178 PVDevice pArray; 2179 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2180 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2181 continue; 2182 else if (pArray->u.array.rf_auto_rebuild) { 2183 KdPrint(("auto rebuild.\n")); 2184 pArray->u.array.rf_auto_rebuild = 0; 2185 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2186 } 2187 } 2188 } 2189 #endif 2190 } 2191 /* launch the awaiting commands blocked by mWaitingForIdle */ 2192 while(pAdapter->pending_Q!= NULL) 2193 { 2194 _VBUS_INST(&pAdapter->VBus) 2195 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2196 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2197 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2198 } 2199 } 2200 2201 static void 2202 ccb_done(union ccb *ccb) 2203 { 2204 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2205 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2206 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2207 2208 dmamap_put(pmap); 2209 xpt_done(ccb); 2210 2211 pAdapter->outstandingCommands--; 2212 2213 if (pAdapter->outstandingCommands == 0) 2214 { 2215 if(DPC_Request_Nums == 0) 2216 Check_Idle_Call(pAdapter); 2217 wakeup(pAdapter); 2218 } 2219 } 2220 2221 /**************************************************************** 2222 * Name: hpt_action 2223 * Description: Process a queued command from the CAM layer. 2224 * Parameters: sim - Pointer to SIM object 2225 * ccb - Pointer to SCSI command structure. 2226 ****************************************************************/ 2227 2228 void 2229 hpt_action(struct cam_sim *sim, union ccb *ccb) 2230 { 2231 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2232 PBUS_DMAMAP pmap; 2233 _VBUS_INST(&pAdapter->VBus) 2234 2235 mtx_assert(&pAdapter->lock, MA_OWNED); 2236 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2237 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2238 2239 switch (ccb->ccb_h.func_code) 2240 { 2241 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2242 { 2243 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2244 2245 if (ccb->ccb_h.target_lun) { 2246 ccb->ccb_h.status = CAM_LUN_INVALID; 2247 xpt_done(ccb); 2248 return; 2249 } 2250 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2251 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2252 ccb->ccb_h.status = CAM_TID_INVALID; 2253 xpt_done(ccb); 2254 return; 2255 } 2256 2257 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2258 Check_Idle_Call(pAdapter); 2259 2260 pmap = dmamap_get(pAdapter); 2261 HPT_ASSERT(pmap); 2262 ccb->ccb_adapter = pmap; 2263 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2264 2265 if (mWaitingForIdle(_VBUS_P0)) 2266 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2267 else 2268 OsSendCommand(_VBUS_P ccb); 2269 2270 /* KdPrint(("leave scsiio\n")); */ 2271 break; 2272 } 2273 2274 case XPT_RESET_BUS: 2275 KdPrint(("reset bus\n")); 2276 fResetVBus(_VBUS_P0); 2277 xpt_done(ccb); 2278 break; 2279 2280 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2281 case XPT_ABORT: /* Abort the specified CCB */ 2282 case XPT_TERM_IO: /* Terminate the I/O process */ 2283 /* XXX Implement */ 2284 ccb->ccb_h.status = CAM_REQ_INVALID; 2285 xpt_done(ccb); 2286 break; 2287 2288 case XPT_GET_TRAN_SETTINGS: 2289 case XPT_SET_TRAN_SETTINGS: 2290 /* XXX Implement */ 2291 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2292 xpt_done(ccb); 2293 break; 2294 2295 case XPT_CALC_GEOMETRY: 2296 cam_calc_geometry(&ccb->ccg, 1); 2297 xpt_done(ccb); 2298 break; 2299 2300 case XPT_PATH_INQ: /* Path routing inquiry */ 2301 { 2302 struct ccb_pathinq *cpi = &ccb->cpi; 2303 2304 cpi->version_num = 1; /* XXX??? */ 2305 cpi->hba_inquiry = PI_SDTR_ABLE; 2306 cpi->target_sprt = 0; 2307 /* Not necessary to reset bus */ 2308 cpi->hba_misc = PIM_NOBUSRESET; 2309 cpi->hba_eng_cnt = 0; 2310 2311 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2312 cpi->max_lun = 0; 2313 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2314 2315 cpi->bus_id = cam_sim_bus(sim); 2316 cpi->base_transfer_speed = 3300; 2317 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2318 strlcpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2319 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2320 cpi->unit_number = cam_sim_unit(sim); 2321 cpi->transport = XPORT_SPI; 2322 cpi->transport_version = 2; 2323 cpi->protocol = PROTO_SCSI; 2324 cpi->protocol_version = SCSI_REV_2; 2325 cpi->ccb_h.status = CAM_REQ_CMP; 2326 xpt_done(ccb); 2327 break; 2328 } 2329 2330 default: 2331 KdPrint(("invalid cmd\n")); 2332 ccb->ccb_h.status = CAM_REQ_INVALID; 2333 xpt_done(ccb); 2334 break; 2335 } 2336 /* KdPrint(("leave hpt_action..............\n")); */ 2337 } 2338 2339 /* shall be called at lock_driver() */ 2340 static void 2341 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2342 { 2343 if(*ccb_Q == NULL) 2344 ccb->ccb_h.ccb_ccb_ptr = ccb; 2345 else { 2346 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2347 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2348 } 2349 2350 *ccb_Q = ccb; 2351 } 2352 2353 /* shall be called at lock_driver() */ 2354 static void 2355 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2356 { 2357 union ccb *TempCCB; 2358 2359 TempCCB = *ccb_Q; 2360 2361 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2362 *ccb_Q = NULL; 2363 else { 2364 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2365 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2366 2367 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2368 2369 if(*ccb_Q == ccb) 2370 *ccb_Q = TempCCB; 2371 } 2372 } 2373 2374 #ifdef SUPPORT_ARRAY 2375 /*************************************************************************** 2376 * Function: hpt_worker_thread 2377 * Description: Do background rebuilding. Execute in kernel thread context. 2378 * Returns: None 2379 ***************************************************************************/ 2380 static void hpt_worker_thread(void) 2381 { 2382 2383 for(;;) { 2384 mtx_lock(&DpcQueue_Lock); 2385 while (DpcQueue_First!=DpcQueue_Last) { 2386 ST_HPT_DPC p; 2387 p = DpcQueue[DpcQueue_First]; 2388 DpcQueue_First++; 2389 DpcQueue_First %= MAX_DPC; 2390 DPC_Request_Nums++; 2391 mtx_unlock(&DpcQueue_Lock); 2392 p.dpc(p.pAdapter, p.arg, p.flags); 2393 2394 mtx_lock(&p.pAdapter->lock); 2395 mtx_lock(&DpcQueue_Lock); 2396 DPC_Request_Nums--; 2397 /* since we may have prevented Check_Idle_Call, do it here */ 2398 if (DPC_Request_Nums==0) { 2399 if (p.pAdapter->outstandingCommands == 0) { 2400 _VBUS_INST(&p.pAdapter->VBus); 2401 Check_Idle_Call(p.pAdapter); 2402 CheckPendingCall(_VBUS_P0); 2403 } 2404 } 2405 mtx_unlock(&p.pAdapter->lock); 2406 mtx_unlock(&DpcQueue_Lock); 2407 2408 /*Schedule out*/ 2409 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2410 /* abort rebuilding process. */ 2411 IAL_ADAPTER_T *pAdapter; 2412 PVDevice pArray; 2413 PVBus _vbus_p; 2414 int i; 2415 2416 sx_slock(&hptmv_list_lock); 2417 pAdapter = gIal_Adapter; 2418 2419 while(pAdapter != NULL){ 2420 mtx_lock(&pAdapter->lock); 2421 _vbus_p = &pAdapter->VBus; 2422 2423 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2424 { 2425 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2426 continue; 2427 else if (pArray->u.array.rf_rebuilding || 2428 pArray->u.array.rf_verifying || 2429 pArray->u.array.rf_initializing) 2430 { 2431 pArray->u.array.rf_abort_rebuild = 1; 2432 } 2433 } 2434 mtx_unlock(&pAdapter->lock); 2435 pAdapter = pAdapter->next; 2436 } 2437 sx_sunlock(&hptmv_list_lock); 2438 } 2439 mtx_lock(&DpcQueue_Lock); 2440 } 2441 mtx_unlock(&DpcQueue_Lock); 2442 2443 /*Remove this debug option*/ 2444 /* 2445 #ifdef DEBUG 2446 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2447 pause("hptrdy", 2*hz); 2448 #endif 2449 */ 2450 kproc_suspend_check(curproc); 2451 pause("-", 2*hz); /* wait for something to do */ 2452 } 2453 } 2454 2455 static struct proc *hptdaemonproc; 2456 static struct kproc_desc hpt_kp = { 2457 "hpt_wt", 2458 hpt_worker_thread, 2459 &hptdaemonproc 2460 }; 2461 2462 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2463 static void 2464 launch_worker_thread(void) 2465 { 2466 IAL_ADAPTER_T *pAdapTemp; 2467 2468 kproc_start(&hpt_kp); 2469 2470 sx_slock(&hptmv_list_lock); 2471 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2472 2473 _VBUS_INST(&pAdapTemp->VBus) 2474 int i; 2475 PVDevice pVDev; 2476 2477 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2478 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2479 continue; 2480 else{ 2481 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2482 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2483 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2484 } 2485 } 2486 sx_sunlock(&hptmv_list_lock); 2487 2488 /* 2489 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished. 2490 */ 2491 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, 2492 SHUTDOWN_PRI_LAST); 2493 } 2494 /* 2495 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2496 */ 2497 2498 #endif 2499 2500 /********************************************************************************/ 2501 2502 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2503 { 2504 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2505 2506 if (logical) { 2507 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2508 pSg->wSgSize = ccb->csio.dxfer_len; 2509 pSg->wSgFlag = SG_FLAG_EOT; 2510 return TRUE; 2511 } 2512 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2513 HPT_ASSERT(0); 2514 return FALSE; 2515 } 2516 2517 /*******************************************************************************/ 2518 ULONG HPTLIBAPI 2519 GetStamp(void) 2520 { 2521 /* 2522 * the system variable, ticks, can't be used since it hasn't yet been active 2523 * when our driver starts (ticks==0, it's a invalid stamp value) 2524 */ 2525 ULONG stamp; 2526 do { stamp = random(); } while (stamp==0); 2527 return stamp; 2528 } 2529 2530 2531 static void 2532 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2533 { 2534 int i; 2535 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2536 2537 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2538 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2539 #ifndef SERIAL_CMDS 2540 inquiryData->CommandQueue = 1; 2541 #endif 2542 2543 switch(pVDev->VDeviceType) { 2544 case VD_SINGLE_DISK: 2545 case VD_ATAPI: 2546 case VD_REMOVABLE: 2547 /* Set the removable bit, if applicable. */ 2548 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2549 inquiryData->RemovableMedia = 1; 2550 2551 /* Fill in vendor identification fields. */ 2552 for (i = 0; i < 20; i += 2) { 2553 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2554 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2555 2556 } 2557 2558 /* Initialize unused portion of product id. */ 2559 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2560 2561 /* firmware revision */ 2562 for (i = 0; i < 4; i += 2) 2563 { 2564 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2565 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2566 } 2567 break; 2568 default: 2569 memcpy(&inquiryData->VendorId, "RR18xx ", 8); 2570 #ifdef SUPPORT_ARRAY 2571 switch(pVDev->VDeviceType){ 2572 case VD_RAID_0: 2573 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2574 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2575 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2576 else 2577 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2578 break; 2579 case VD_RAID_1: 2580 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2581 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2582 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2583 else 2584 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2585 break; 2586 case VD_RAID_5: 2587 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2588 break; 2589 case VD_JBOD: 2590 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2591 break; 2592 } 2593 #endif 2594 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2595 break; 2596 } 2597 } 2598 2599 static void 2600 hpt_timeout(void *arg) 2601 { 2602 PBUS_DMAMAP pmap = (PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter; 2603 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2604 _VBUS_INST(&pAdapter->VBus) 2605 2606 mtx_assert(&pAdapter->lock, MA_OWNED); 2607 fResetVBus(_VBUS_P0); 2608 } 2609 2610 static void 2611 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2612 { 2613 PCommand pCmd = (PCommand)arg; 2614 union ccb *ccb = pCmd->pOrgCommand; 2615 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2616 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2617 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2618 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2619 FPSCAT_GATH psg = pCmd->pSgTable; 2620 int idx; 2621 _VBUS_INST(pVDev->pVBus) 2622 2623 HPT_ASSERT(pCmd->cf_physical_sg); 2624 2625 if (error) 2626 panic("busdma error"); 2627 2628 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2629 2630 if (nsegs != 0) { 2631 for (idx = 0; idx < nsegs; idx++, psg++) { 2632 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2633 psg->wSgSize = segs[idx].ds_len; 2634 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2635 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2636 } 2637 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2638 2639 if (pCmd->cf_data_in) { 2640 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, 2641 BUS_DMASYNC_PREREAD); 2642 } 2643 else if (pCmd->cf_data_out) { 2644 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, 2645 BUS_DMASYNC_PREWRITE); 2646 } 2647 } 2648 2649 callout_reset(&pmap->timeout, 20 * hz, hpt_timeout, ccb); 2650 pVDev->pfnSendCommand(_VBUS_P pCmd); 2651 CheckPendingCall(_VBUS_P0); 2652 } 2653 2654 2655 2656 static void HPTLIBAPI 2657 OsSendCommand(_VBUS_ARG union ccb *ccb) 2658 { 2659 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2660 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2661 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2662 struct ccb_scsiio *csio = &ccb->csio; 2663 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2664 2665 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2666 ccb, 2667 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2668 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2669 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2670 )); 2671 2672 pAdapter->outstandingCommands++; 2673 2674 if (pVDev == NULL || pVDev->vf_online == 0) { 2675 ccb->ccb_h.status = CAM_REQ_INVALID; 2676 ccb_done(ccb); 2677 goto Command_Complished; 2678 } 2679 2680 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2681 { 2682 case TEST_UNIT_READY: 2683 case START_STOP_UNIT: 2684 case SYNCHRONIZE_CACHE: 2685 /* FALLTHROUGH */ 2686 ccb->ccb_h.status = CAM_REQ_CMP; 2687 break; 2688 2689 case INQUIRY: 2690 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2691 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2692 ccb_h->status = CAM_REQ_CMP; 2693 break; 2694 2695 case READ_CAPACITY: 2696 { 2697 UCHAR *rbuf=csio->data_ptr; 2698 unsigned int cap; 2699 2700 if (pVDev->VDeviceCapacity > 0xfffffffful) { 2701 cap = 0xfffffffful; 2702 } else { 2703 cap = pVDev->VDeviceCapacity - 1; 2704 } 2705 2706 rbuf[0] = (UCHAR)(cap>>24); 2707 rbuf[1] = (UCHAR)(cap>>16); 2708 rbuf[2] = (UCHAR)(cap>>8); 2709 rbuf[3] = (UCHAR)cap; 2710 /* Claim 512 byte blocks (big-endian). */ 2711 rbuf[4] = 0; 2712 rbuf[5] = 0; 2713 rbuf[6] = 2; 2714 rbuf[7] = 0; 2715 2716 ccb_h->status = CAM_REQ_CMP; 2717 break; 2718 } 2719 2720 case 0x9e: /*SERVICE_ACTION_IN*/ 2721 { 2722 UCHAR *rbuf = csio->data_ptr; 2723 LBA_T cap = pVDev->VDeviceCapacity - 1; 2724 2725 rbuf[0] = (UCHAR)(cap>>56); 2726 rbuf[1] = (UCHAR)(cap>>48); 2727 rbuf[2] = (UCHAR)(cap>>40); 2728 rbuf[3] = (UCHAR)(cap>>32); 2729 rbuf[4] = (UCHAR)(cap>>24); 2730 rbuf[5] = (UCHAR)(cap>>16); 2731 rbuf[6] = (UCHAR)(cap>>8); 2732 rbuf[7] = (UCHAR)cap; 2733 rbuf[8] = 0; 2734 rbuf[9] = 0; 2735 rbuf[10] = 2; 2736 rbuf[11] = 0; 2737 2738 ccb_h->status = CAM_REQ_CMP; 2739 break; 2740 } 2741 2742 case READ_6: 2743 case WRITE_6: 2744 case READ_10: 2745 case WRITE_10: 2746 case 0x88: /* READ_16 */ 2747 case 0x8a: /* WRITE_16 */ 2748 case 0x13: 2749 case 0x2f: 2750 { 2751 UCHAR Cdb[16]; 2752 UCHAR CdbLength; 2753 _VBUS_INST(pVDev->pVBus) 2754 PCommand pCmd = AllocateCommand(_VBUS_P0); 2755 int error; 2756 HPT_ASSERT(pCmd); 2757 2758 CdbLength = csio->cdb_len; 2759 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2760 { 2761 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2762 { 2763 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2764 } 2765 else 2766 { 2767 KdPrintE(("ERROR!!!\n")); 2768 ccb->ccb_h.status = CAM_REQ_INVALID; 2769 break; 2770 } 2771 } 2772 else 2773 { 2774 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2775 } 2776 2777 pCmd->pOrgCommand = ccb; 2778 pCmd->pVDevice = pVDev; 2779 pCmd->pfnCompletion = fOsCommandDone; 2780 pCmd->pfnBuildSgl = fOsBuildSgl; 2781 pCmd->pSgTable = pmap->psg; 2782 2783 switch (Cdb[0]) 2784 { 2785 case READ_6: 2786 case WRITE_6: 2787 case 0x13: 2788 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2789 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2790 break; 2791 2792 case 0x88: /* READ_16 */ 2793 case 0x8a: /* WRITE_16 */ 2794 pCmd->uCmd.Ide.Lba = 2795 (HPT_U64)Cdb[2] << 56 | 2796 (HPT_U64)Cdb[3] << 48 | 2797 (HPT_U64)Cdb[4] << 40 | 2798 (HPT_U64)Cdb[5] << 32 | 2799 (HPT_U64)Cdb[6] << 24 | 2800 (HPT_U64)Cdb[7] << 16 | 2801 (HPT_U64)Cdb[8] << 8 | 2802 (HPT_U64)Cdb[9]; 2803 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13]; 2804 break; 2805 2806 default: 2807 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2808 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2809 break; 2810 } 2811 2812 switch (Cdb[0]) 2813 { 2814 case READ_6: 2815 case READ_10: 2816 case 0x88: /* READ_16 */ 2817 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2818 pCmd->cf_data_in = 1; 2819 break; 2820 2821 case WRITE_6: 2822 case WRITE_10: 2823 case 0x8a: /* WRITE_16 */ 2824 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2825 pCmd->cf_data_out = 1; 2826 break; 2827 case 0x13: 2828 case 0x2f: 2829 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2830 break; 2831 } 2832 /*///////////////////////// */ 2833 pCmd->cf_physical_sg = 1; 2834 error = bus_dmamap_load_ccb(pAdapter->io_dma_parent, 2835 pmap->dma_map, 2836 ccb, 2837 hpt_io_dmamap_callback, 2838 pCmd, BUS_DMA_WAITOK 2839 ); 2840 KdPrint(("bus_dmamap_load return %d\n", error)); 2841 if (error && error!=EINPROGRESS) { 2842 hpt_printk(("bus_dmamap_load error %d\n", error)); 2843 FreeCommand(_VBUS_P pCmd); 2844 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2845 dmamap_put(pmap); 2846 pAdapter->outstandingCommands--; 2847 if (pAdapter->outstandingCommands == 0) 2848 wakeup(pAdapter); 2849 xpt_done(ccb); 2850 } 2851 goto Command_Complished; 2852 } 2853 2854 default: 2855 ccb->ccb_h.status = CAM_REQ_INVALID; 2856 break; 2857 } 2858 ccb_done(ccb); 2859 Command_Complished: 2860 CheckPendingCall(_VBUS_P0); 2861 return; 2862 } 2863 2864 static void HPTLIBAPI 2865 fOsCommandDone(_VBUS_ARG PCommand pCmd) 2866 { 2867 union ccb *ccb = pCmd->pOrgCommand; 2868 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2869 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2870 2871 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 2872 2873 callout_stop(&pmap->timeout); 2874 2875 switch(pCmd->Result) { 2876 case RETURN_SUCCESS: 2877 ccb->ccb_h.status = CAM_REQ_CMP; 2878 break; 2879 case RETURN_BAD_DEVICE: 2880 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 2881 break; 2882 case RETURN_DEVICE_BUSY: 2883 ccb->ccb_h.status = CAM_BUSY; 2884 break; 2885 case RETURN_INVALID_REQUEST: 2886 ccb->ccb_h.status = CAM_REQ_INVALID; 2887 break; 2888 case RETURN_SELECTION_TIMEOUT: 2889 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2890 break; 2891 case RETURN_RETRY: 2892 ccb->ccb_h.status = CAM_BUSY; 2893 break; 2894 default: 2895 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2896 break; 2897 } 2898 2899 if (pCmd->cf_data_in) { 2900 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 2901 } 2902 else if (pCmd->cf_data_out) { 2903 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 2904 } 2905 2906 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 2907 2908 FreeCommand(_VBUS_P pCmd); 2909 ccb_done(ccb); 2910 } 2911 2912 int 2913 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 2914 { 2915 int p; 2916 2917 mtx_lock(&DpcQueue_Lock); 2918 p = (DpcQueue_Last + 1) % MAX_DPC; 2919 if (p==DpcQueue_First) { 2920 KdPrint(("DPC Queue full!\n")); 2921 mtx_unlock(&DpcQueue_Lock); 2922 return -1; 2923 } 2924 2925 DpcQueue[DpcQueue_Last].dpc = dpc; 2926 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 2927 DpcQueue[DpcQueue_Last].arg = arg; 2928 DpcQueue[DpcQueue_Last].flags = flags; 2929 DpcQueue_Last = p; 2930 mtx_unlock(&DpcQueue_Lock); 2931 2932 return 0; 2933 } 2934 2935 #ifdef _RAID5N_ 2936 /* 2937 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 2938 * How about the memory for 5081 request/response array and PRD table? 2939 */ 2940 void 2941 *os_alloc_page(_VBUS_ARG0) 2942 { 2943 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2944 } 2945 2946 void 2947 *os_alloc_dma_page(_VBUS_ARG0) 2948 { 2949 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2950 } 2951 2952 void 2953 os_free_page(_VBUS_ARG void *p) 2954 { 2955 contigfree(p, 0x1000, M_DEVBUF); 2956 } 2957 2958 void 2959 os_free_dma_page(_VBUS_ARG void *p) 2960 { 2961 contigfree(p, 0x1000, M_DEVBUF); 2962 } 2963 2964 void 2965 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 2966 { 2967 UINT i; 2968 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 2969 } 2970 2971 void 2972 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 2973 { 2974 UINT i; 2975 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 2976 } 2977 #endif 2978